EMBEDDED SoPC DESIGN WITH NIOS II PROCESSOR AND VERILOG EXAMPLES www.it-ebooks.info EMBEDDED SoPC DESIGN WITH NIOS II PROCESSOR AND VERILOG EXAMPLES Pong P Chu Cleveland State University WILEY A JOHN WILEY & SONS, INC., PUBLICATION www.it-ebooks.info Copyright © 2012 by John Wiley & Sons, Inc All rights reserved Published by John Wiley & Sons, Inc., Hoboken, New Jersey Published simultaneously in Canada No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748.-6008, or online at http://www.wiley.com/go/permission Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose No warranty may be created or extended by sales representatives or written sales materials The advice and strategies contained herein may not be suitable for your situation You should consult with a professional where appropriate Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (317) 572-3993 or fax (317) 572-4002 Wiley also publishes its books in a variety of electronic formats Some content that appears in print may not be available in electronic formats For more information about Wiley products, visit our web site at www.wiley.com Library of Congress Cataloging-in-Publication Data: Chu, Pong P., 1959Embedded SoPC design with NIOSII processor and Verilog examples / Pong P Chu p cm Includes bibliographical references and index ISBN 978-1-118-01103-4 (hardback) Embedded computer systems Field programmable gate arrays Verilog (Computer hardware description language) I Title TK7895.E42C48 2012 006.2'2—dc23 2011048946 Printed in the United States of America 10 www.it-ebooks.info To my mother, Chi-Te, my wife, Lee, and my daughter, Patricia www.it-ebooks.info CONTENTS Preface xxvu Acknowledgments xxxiii Overview of Embedded System 1.1 1.2 1.3 1.4 1.5 Introduction 1.1.1 Definition of an embedded system 1.1.2 Example systems System design requirements Embedded SoPC systems 1.3.1 Basic development flow Book organization Bibliographic notes PART I BASIC DIGITAL CIRCUITS DEVELOPMENT Combinational Circuit Gate-level Overvie 2.1 2.2 2.3 2.4 1 8 Introduction General description Basic lexical elements and data types 2.3.1 Lexical elements Data types 11 11 12 13 13 14 vii www.it-ebooks.info V¡¡¡ CONTENTS 2.5 2.6 2.7 2.8 2.9 2.4.1 Four-value system 2.4.2 Data type groups 2.4.3 Number representation 2.4.4 Operators Program skeleton 2.5.1 Port declaration 2.5.2 Program body 2.5.3 Signal declaration 2.5.4 Another example Structural description Testbench Bibliographic notes Suggested experiments 2.9.1 Code for gate-level greater-than circuit 2.9.2 Code for gate-level binary decoder Overview of FPGA and EDA Software 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 FPGA 3.1.1 Overview of a general FPGA device 3.1.2 Overview of the Altera Cyclone II devices Overview of the Altera DEI and DE2 boards Development flow Overview of Quartus II Short tutorial of Quartus II 3.5.1 Create the design project 3.5.2 Create a testbench and perform the RTL simulation 3.5.3 Compile the project 3.5.4 Perform timing analysis 3.5.5 Program the FPGA device Short tutorial on the ModelSim HDL simulator Bibliographic notes Suggested experiments 3.8.1 Gate-level greater-than circuit 3.8.2 Gate-level binary decoder 14 14 15 16 16 16 17 18 18 19 22 23 24 24 24 25 25 25 27 30 30 33 35 36 41 41 43 43 45 50 50 50 51 RT-level Combinational Circuit 53 4.1 53 55 55 56 56 Operators 4.1.1 Arithmetic operators 4.1.2 Shift operators 4.1.3 Relational and equality operators 4.1.4 Bitwise, reduction, and logical operators www.it-ebooks.info CONTENTS 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.1.5 Concatenation and replication operators 4.1.6 Conditional operators 4.1.7 Operator precedence 4.1.8 Expression bit-length adjustment 4.1.9 Synthesis of z and x values Always block for a combinational circuit 4.2.1 Basic syntax and behavior 4.2.2 Procedural assignment 4.2.3 Variable data types 4.2.4 Simple examples If statement 4.3.1 Syntax 4.3.2 Examples Case statement 4.4.1 Syntax 4.4.2 Examples 4.4.3 The casez and casex statements 4.4.4 Full case and parallel case Routing structure of conditional control constructs 4.5.1 Priority routing network 4.5.2 Multiplexing network General coding guidelines for an always block 4.6.1 Common errors in combinational circuit codes 4.6.2 Guidelines Parameter and constant 4.7.1 Constant 4.7.2 Parameter 4.7.3 Use of parameters in Verilog-1995 Design examples 4.8.1 Hexadecimal digit to seven-segment LED decoder 4.8.2 Sign-magnitude adder 4.8.3 Barrel shifter 4.8.4 Simplified floating-point adder Bibliographic notes Suggested experiments 4.10.1 Multifunction barrel shifter 4.10.2 Dual-priority encoder 4.10.3 BCD incrementor 4.10.4 Floating-point greater-than circuit 4.10.5 Floating-point and signed integer conversion circuit 4.10.6 Enhanced floating-point adder www.it-ebooks.info ¡X 57 58 59 59 60 62 62 63 63 64 65 65 66 68 68 69 69 70 71 71 73 74 74 77 78 78 79 81 81 81 83 85 87 90 91 91 91 91 92 92 92 X CONTENTS Regular Sequential Circuit Overvie 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 93 Introduction 5.1.1 D FF and register 5.1.2 Synchronous system 5.1.3 Code development HDL code of the FF and register 5.2.1 D FF 5.2.2 Register 5.2.3 Register file 5.2.4 SRAM Simple design examples 5.3.1 Shift register 5.3.2 Binary counter and variant Testbench for sequential circuits Timing analysis 5.5.1 Timing parameters 5.5.2 Timing considerations in Quartus II Case study 5.6.1 Stopwatch 5.6.2 FIFO buffer Cyclone II device embedded memory module 5.7.1 Overview of memory options of DEI board 5.7.2 Overview of embedded M4K module 5.7.3 Methods to incorporate embedded memory module 5.7.4 HDL module to infer synchronous single-port RAM 5.7.5 HDL module to infer synchronous simple dual-port RAM 5.7.6 HDL module to infer synchronous true dual-port RAM 5.7.7 HDL module to infer synchronous ROM 5.7.8 HDL module to specify RAM initial values 5.7.9 FIFO buffer revisited Bibliographic notes Suggested experiments 5.9.1 Programmable square-wave generator 5.9.2 Pulse width modulation circuit 5.9.3 Rotating square circuit 5.9.4 Heartbeat circuit 5.9.5 Rotating LED banner circuit 5.9.6 Enhanced stopwatch 5.9.7 FIFO with data width conversion 5.9.8 Stack 5.9.9 ROM-based sign-magnitude adder 5.9.10 ROM-based temperature conversion www.it-ebooks.info 93 94 94 95 95 96 99 99 102 103 103 104 107 110 110 112 114 114 117 121 121 122 122 124 126 127 129 130 131 132 132 132 133 133 133 134 134 134 134 134 135 CONTENTS FSM 6.1 6.2 6.3 6.4 6.5 X¡ 137 Introduction 6.1.1 Mealy and Moore outputs 6.1.2 FSM representation FSM code development Design examples 6.3.1 Rising-edge detector 6.3.2 Debouncing circuit 6.3.3 Testing circuit Bibliographic notes Suggested experiments 6.5.1 Dual-edge detector 6.5.2 Alternative debouncing circuit 6.5.3 Parking lot occupancy counter 137 138 138 140 143 143 147 151 153 153 153 153 153 FSMD 155 7.1 155 156 156 158 161 161 161 164 166 168 168 171 175 178 181 184 184 184 184 185 185 186 186 187 7.2 7.3 7.4 7.5 Introduction 7.1.1 Single RT operation 7.1.2 ASMD chart 7.1.3 Decision box with a register Code development of an FSMD 7.2.1 Debouncing circuit based on RT methodology 7.2.2 Code with explicit data path components 7.2.3 Code with implicit data path components 7.2.4 Comparison Design examples 7.3.1 Fibonacci number circuit 7.3.2 Division circuit 7.3.3 Binary-to-BCD conversion circuit 7.3.4 Period counter 7.3.5 Accurate low-frequency counter Bibliographic notes Suggested experiments 7.5.1 Alternative debouncing circuit 7.5.2 BCD-to-binary conversion circuit 7.5.3 Fibonacci circuit with BCD I/O: design approach 7.5.4 Fibonacci circuit with BCD I/O: design approach 7.5.5 Auto-scaled low-frequency counter 7.5.6 Reaction timer 7.5.7 Babbage difference engine emulation circuit www.it-ebooks.info XÜ CONTENTS Selected Topics of Verilog Overvie 189 8.1 189 190 191 193 8.2 8.3 8.4 8.5 8.6 8.7 Blockh ig versus nonbiocking assignment 8.1.1 Overview 8.1.2 Combinational circuit 8.1.3 Memory element 8.1.4 Sequential circuit with mixed blocking and nonbiocking assignments Alternative coding style for sequential circuit 8.2.1 Binary counter FSM 8.2.2 FSMD 8.2.3 Summary 8.2.4 Use of the signed data type 8.3.1 Overview 8.3.2 Signed number in Verilog-1995 8.3.3 Signed number in Verilog-2001 Use of function in synthesis 8.4.1 Overview 8.4.2 Examples Additional constructs for testbench development 8.5.1 Always block and initial block 8.5.2 Procedural statements 8.5.3 Timing control 8.5.4 Delay control 8.5.5 Event control 8.5.6 Wait statement 8.5.7 Timescale directive 8.5.8 System functions and tasks User-defined functions and tasks 8.5.9 8.5.10 Example of a comprehensive testbench Bibliographic notes Suggested experiments 8.7.1 Shift register with blocking and nonbiocking assignments 8.7.2 Alternative coding style for BCD counter 8.7.3 Alternative coding style for FIFO buffer 8.7.4 Alternative coding style for Fibonacci circuit 8.7.5 Dual-mode comparator 8.7.6 Enhanced binary counter monitor 8.7.7 Testbench for FIFO buffer PART II BASIC NIOS II SOFTWARE DEVELOPMENT www.it-ebooks.info 194 196 196 198 199 201 201 201 203 203 204 204 205 207 207 207 209 209 210 211 211 212 216 217 223 223 223 224 224 224 224 224 225 SUGGESTED EXPERIMENTS 23.7.2 731 Reduced-size phase-to-amplitude lookup table The size of the lookup table can grow large when high-resolution output is needed However, it can be reduced to one quarter of the original size by taking advantage of the symmetry of the sinusoidal function We only need to include data points in the first quadrant (i.e., between and ξ) and derive the rest data points using the following equations: sin(x) = sin(x) = 8ΐη(π — x) if | < x < π — sin(x — π) if π < x < 2π Design the new DDFS circuit using this approach, derive the HDL code, and verify its operation 23.7.3 Synthetic music player A piece of music is represented by a sequence of notes and their durations We can implement a synthetic music player using the DDFS circuit Derive software, convert a simple song to this format and store them in an array, and verify its operation 23.7.4 Keyboard piano A PS2 keyboard can be used as a piano keyboard to play synthesized music Select 12 keys for the 12 notes and use digits to to select the desired octave Note that the duration of the sustain segment is not fixed It lasts until the amplitude decays to zero or when the key is released Derive software and verify its operation 23.7.5 Keyboard recorder We can combine Experiments 23.7.3 and 23.7.4 and add additional recording functionality Use keys R and T to start and stop the recording session During a recording session, the notes and their durations are stored to an array Use key P to play back the stored information 23.7.6 Hardware envelope generator We can implement the envelope generation function in hardware The circuit should include registers storing the relevant amplitude and segment duration information and an FSMD to generate the envelope points Note that the duration of the sustain segment is not fixed It lasts until the amplitude decays to zero or when the key is released Modify the DDFS IP core to incorporate the new functionality, resynthesize the Nios II system, create the necessary software driver, and verify its operation 23.7.7 Additive harmonic synthesis A harmonic is a signal whose frequency is an integer multiple of the fundamental frequency For example, if the fundamental frequency is / , its harmonics are / , www.it-ebooks.info 732 DIRECT DIGITAL FREQUENCY SYNTHESIS 3/, 4/, · · · One scheme to generate synthesized music is to add attenuated harmonics to the original signal Expand the DDFS IP core to allow the addition of three harmonics The integer multiple and attenuation level of each harmonic can be controlled individually Resynthesize the Nios II system, create the necessary software driver, and verify its operation 23.7.8 Sample-based synthesis The waveform produced by a real music instrument is usually very complex rather than a simple sinusoidal function One scheme to create better sound is to record a sample from a real instrument and store the waveform in the phase-to-amplitude lookup table We can use the microphone input to record a note of an instrument (e.g., a harmonica), extract data points from one cycle, and store the results to the lookup table Derive the software and verify its operation 23.8 23.8.1 SUGGESTED PROJECTS Sound generator A sound generator is an IC chip designed to produce sound and were used widely in early computers and arcade games A representative device is Yamaha YM2149 Search its data sheet on the Web, study its schematics and specifications, and design a similar system using HDL and FPGA 23.8.2 Function generator A function generator is an instrument that can produce various waveform patterns (such as sinusoidal, square, triangular, ramp, etc.) over a range of frequencies and amplitudes It is used to test the response of circuits to common input signals Research the basic operation and layout of a functional generator Use the DDFS circuit to generate the desired waveform and use the VGA monitor and keyboard to create a virtual control panel Note that because of the low sampling rate of an audio DAC, the range of the frequencies is limited between 20 and 20,000 Hz 23.8.3 Full-fledged electric synthesizer An electric synthesizer produces a variety of sounds It can mimic other musical instruments and generate special effects Several previous experiments implement parts of the functionalities Research the functionalities, operation, and layout of an actual music keyboard Expand the DDFS circuit to support a full-fledged electric synthesizer, and use the VGA monitor and keyboard to create a virtual control panel www.it-ebooks.info www.it-ebooks.info : ( e s * q - s j p p sen"»!* ' eseq-otptus zW%\*) »TOt"sjpp !(ΛΠΘ 9ΐ _ ϊΐΒ ' e s e q - s j p p sen"*tB)Atie-j»-sjpp ¡ ( l e e j j o ^πτ ' e s e q - s j p p ζεη"ΐτιβ)1Β1