Solution manual for fundamentals of digital and computer design with VHDL by sandige

Solution Manual for Fundamentals of Digital and Computer Design with VHDL by Sandige 1.16 See Figure P1.16 Distinctive Shape Logic Symbols NOT or Complement operation AND operation OR operation Figure P1.16 1.17 See Figure P1.17 Figure P1.17 1.18 (a) F1  A  B  C , (b) F  B , (c) F  A  B  C  D , (d) F  C (e) F  S  W  Y , (f) F  P  T 1.19 binary digits or bits 1.20 See Figure P1.20 Figure P1.20 1.21 bits or identity elements Full file at https://TestbankDirect.eu/ Solution Manual for Fundamentals of Digital and Computer Design with VHDL by Sandige Full file at https://TestbankDirect.eu/ 1.22 See Figure P1.22 Figure P1.22 1.23 Variable Dominant Rule, Commutative Rule, Distributive Rule, and Complement Rule 1.24 When writing Boolean algebra expressions, the NOT operator has the highest precedence followed by the AND operator followed by the OR operator 1.25 A 1  A (variable dominant rule), A  B  B  A (commutative rule), A  ( B  C )  A  B  A  C (distributive rule), and A  A  (complement rule) 1.26 The dual of a Boolean relationship or a Boolean expression is obtained by interchanging the identity elements (1 and 0) and the binary operators (• and +) while maintaining the order of precedence of the operators using parentheses if required ( X  Y  Z W  A)D  ( X  (Y  Z  W )  A)D  ( X  (Y  Z  W )  A) 1.27 ( A  B  C )D  A  B  C ( X  Y  Z )D  (( X  Y )  Z )D  ( X  Y )  Z ( A  ( B  C  D )  A  D )D  (( A  ( B  (C  D )))  ( A  D ))D  ( A  ( B  (C  D )))  ( A  D )  ( A  B  (C  D ))  ( A  D ) 1.28 Theorems are useful equalities that are helpful in designing logic circuits 1.29 See Figure P1.29 The theorem is the Absorption Theorem T1a: X  ( X  Y )  X Figure P1.29 Full file at https://TestbankDirect.eu/ Solution Manual for Fundamentals of Digital and Computer Design with VHDL by Sandige Full file at https://TestbankDirect.eu/ 1.30 See Figure P1.30 The theorem is the Simplification Theorem T10b: X  X  Y  X  Y Figure P1.30 1.31 See Figure P1.31 The theorem is the Consensus Theorem T4a: A B  AC  B C  A B  AC Figure P1.31 1.32 See Table P1.32 Figure P1.32 1.33 See Table P1.33 Figure P1.33 Full file at https://TestbankDirect.eu/ Solution Manual for Fundamentals of Digital and Computer Design with VHDL by Sandige Full file at https://TestbankDirect.eu/ 1.34 See Table P1.34 Absorption Theorem T1a: X•(X + Y) = X Proof by Perfect Induction Method X Y 0 1 1 EOR X+Y X•(X+Y) 0 1 1 = EOL Proof by Mathematical Manipulation Method (proving that EOL = EOR) X•(X + Y) X•X + X•Y X + X•Y X•1 + X•Y X•(1 + Y) X•1 X Note that EOL = EOR Figure P1.34 Section 1.3 Deriving Boolean Functions from Truth Tables 1.35 (a) F1 ( X , Y )  m(3)  m3  X  Y (b) F2 (Y )  m(0)= m0  Y (c) F3 ( A, B)  m(1, 2,3)  m1  m2  m3  A  B  A  B  A  B 1.36 For minterms place an overbar just over the 0s 1.37 See Figure P1.37 Figure P1.37 1.38 (a) F ( X , Y )  m(2)  m2  X  Y (b) F2 (Y )  m(1)= m1  Y (c) F3 ( A, B)  m(0,1, 2)  m0  m1  m2  A  B  A  B  A  B 1.39 See Figure P1.39 Figure P1.39 Full file at https://TestbankDirect.eu/ Solution Manual for Fundamentals of Digital and Computer Design with VHDL by Sandige Full file at https://TestbankDirect.eu/ 1.40 1.41 For maxterms place an overbar just over the 1s (a) F1 ( X , Y )  M (0,1, 2)  M  M  M  ( X  Y )  ( X  Y )  ( X  Y ) (b) F2 (Y )  M (0)  M  Y (c) F3 ( A, B)  M (1, 2)  ( A  B)  ( A  B ) 1.42 See Figure P1.42 Figure P1.42 1.43 (a) F1 ( X , Y )   M (0,1,3)  M  M  M  ( X  Y )  ( X  Y )  ( X  Y ) (b) F2 (Y )  M (1)  M  Y (c) F3 ( A, B)  M (1,3)  M  M  ( A  B)  ( A  B ) 1.44 See Figure P1.44 Figure P1.44 Section 1.4 Writing VHDL Designs for Simple Gate functions 1.45 CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array) 1.46 the entity and the architecture 1.47 The entity contains the description of the inputs and the outputs, and the architecture contains the description of the actual circuit in terms of a Boolean function or functions 1.48 A VHDL design consists of parts The names of the three parts are the Library Part, Entity Declaration, and Architecture Declaration 1.49 Keywords are reserved words that cannot be used for signal names or labels in VHDL 1.50 The keywords are library, use, all, entity, is, port, in, out, end, architecture, of, is begin, and, and end Full file at https://TestbankDirect.eu/ Solution Manual for Fundamentals of Digital and Computer Design with VHDL by Sandige Full file at https://TestbankDirect.eu/ 1.51 There are three inputs and their names are X, Y, and Z 1.52 See Figure P1.52 Figure P1.52 1.53 See Figure P1.53 Figure P1.53 1.54 See Figure P1.54 Figure P1.54 1.55 See Figure P1.55 Figure P1.55 1.56 See Listing P1.56 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity CSOP1 is port ( a, b, c : in std_logic; f : out std_logic ); end CSOP1; architecture B_function of CSOP1 is begin Full file at https://TestbankDirect.eu/ Solution Manual for Fundamentals of Digital and Computer Design with VHDL by Sandige Full file at https://TestbankDirect.eu/ f