A Survey of Logic Block Architectures For Digital Signal Processing Applications

A Survey of Logic Block Architectures For Digital Signal Processing Applications Presentation Outline  Considerations in Logic Block Design  Computation Requirements  Why Inefficiencies?  Representative Logic Block Architectures  Proposed  Commercial  Conclusions: What is suitable Where? Why DSP??? The Context    Representative of computationally intensive class of applications  datapath oriented and arithmetic oriented Increasingly large use of FPGAs for DSP  multimedia signal processing, communications, and much more To study the “issues” in reconfigurable fabric design for compute intensive applications  What is involved in making a fabric to accelerate multimedia reconfigurable computing possible? Elements of a Reconfigurable Architecture  Logic Block/Processing Element  Differing Grains Fine>>Coarse>>ALUs Routing  Dynamic Reconfiguration  So what’s wrong with the typical FPGA? Meant to be general purpose  lower risks  Toooo Flexible!  Result: Efficiency Gap  Higher Implementation Cost, Larger Delay, Larger Power Consumption than ASICs  Performance vs Flexibility Tradeoff  Postponing Mapping and Silicon Re-use  Solution? See how FPGAs are Used? FPGAs are being used for “classes” of applications  Encryption, DSP, Multimedia etc  Here lies the Key  Design FPGAs for a class of applications  Application Domain Characterization  Application Domain Tuning  Domain Specialization COMPUTATION  defines  ARCHITECTURE  Target Application Characteristics known beforehand? Yes Characterize the application domain Determine a balance b/w flexibilty vs efficiency Tune the architecture according Categorizing the “Computation” Control  Random Logic Implementation  Datapath  Processing of Multi-bit Data  Conflicting Requirements???  Datapath Element Requirements Operates on Word Slices or Bit Slices  Produces multi-bit outputs  Requires many smaller elements to produce each bit output  i.e multiple small LUTs  Control Logic Requirements Produces a single output from many single bit inputs  Benefits from large grain LUT as logic levels gets reduced  Stratix II ALM in Arithmetic Mode Various Configurations in an ALM of Stratix II Multiplier Resources in Stratix II Structure of a DSP Block in Stratix II XILINX Virtex II Pro Architecture Basic Logic Element of Virtex II Pro Dedicated Multipliers in Virtex II Pro ProcessorProgrammable Logic Coupled Architecture PiCoGA Architecture Coupled with a VLIW processor PiCoGA Logic Block Conclusions     Traditional general purpose FPGA inefficient for data path mapping Logic blocks with DSP specific enhancements seem a promising solution Coarse Grained Logic can achieve better application mapping for data path but sacrifice flexibility Dedicated Blocks (Multipliers) increase performance but also increases cost significantly Conclusions PDSPs with embedded FPGA can achieve a good balance between performance and power consumption  So…Which approach is the best?  No single best exists  Suitability of Approaches Highly computationally intensive applications with large amounts of parallelism can use platform FPGAs where often large resources are required and power consumption is not an issue  Here cost/function will be lowest  Suitability of Approaches  Field Programmable Logic based coprocessors can benefit from coarse grained blocks where most control functions are implemented by the PDSP itself Suitability of Approaches  Higher flexibility and lower cost can be achieved with logic blocks with DSP specific enhancements but flexibility to implement control logic in an efficient manner