Springer Series on Signals and Communication Technology Signals and Communication Technology Wireless Network Security Y Xiao, D.-Z Du, X Shen ISBN 978-0-387-28040-0 Terrestrial Trunked Radio – TETRA A Global Security Tool P Stavroulakis ISBN 978-3-540-71190-2 Multirate Statistical Signal Processing O.S Jahromi ISBN 978-1-4020-5316-0 Wireless Ad Hoc and Sensor Networks A Cross-Layer Design Perspective R Jurdak ISBN 978-0-387-39022-2 Positive Trigonometric Polynomials and Signal Processing Applications B Dumitrescu ISBN 978-1-4020-5124-1 Face Biometrics for Personal Identification Multi-Sensory Multi-Modal Systems R.I Hammoud, B.R Abidi, M.A Abidi (Eds.) ISBN 978-3-540-49344-0 Cryptographic Algorithms on Reconfigurable Hardware F Rodr´ıguez-Henr´ıquez ISBN 978-0-387-33883-5 Ad-Hoc Networking Towards Seamless Communications L Gavrilovska ISBN 978-1-4020-5065-7 Multimedia Database Retrieval A Human-Centered Approach P Muneesawang, L Guan ISBN 978-0-387-25627-6 Broadband Fixed Wireless Access A System Perspective M Engels; F Petre ISBN 978-0-387-33956-6 Acoustic MIMO Signal Processing Y Huang, J Benesty, J Chen ISBN 978-3-540-37630-9 Algorithmic Information Theory Mathematics of Digital Information Processing P Seibt ISBN 978-3-540-33218-3 Continuous-Time Signals Y.S Shmaliy ISBN 978-1-4020-4817-3 Interactive Video Algorithms and Technologies R.I Hammoud (Ed.) ISBN 978-3-540-33214-5 Distributed Cooperative Laboratories Networking, Instrumentation, and Measurements F Davoli, S Palazzo, S Zappatore (Eds.) ISBN 978-0-387-29811-5 Topics in Acoustic Echo and Noise Control Selected Methods for the Cancellation of Acoustical Echoes, the Reduction of Background Noise, and Speech Processing E Hänsler, G Schmidt (Eds.) ISBN 978-3-540-33212-1 EM Modeling of Antennas and RF Components for Wireless Communication Systems F Gustrau, D Manteuffel ISBN 978-3-540-28614-1 Orthogonal Frequency Division Multiplexing for Wireless Communications Y Li, G.L Stuber (Eds.) ISBN 978-0-387-29095-9 Advanced Man-Machine Interaction Fundamentals and Implementation K.-F Kraiss ISBN 978-3-540-30618-4 The Variational Bayes Method in Signal Processing V Sˇ m´ıdl, A Quinn ISBN 978-3-540-28819-0 Voice and Speech Quality Perception Assessment and Evaluation U Jekosch ISBN 978-3-540-24095-2 Circuits and Systems Based on Delta Modulation Linear, Nonlinear and Mixed Mode Processing D.G Zrilic ISBN 978-3-540-23751-8 Speech Enhancement J Benesty, S Makino, J Chen (Eds.) ISBN 978-3-540-24039-6 Uwe Meyer-Baese Digital Signal Processing with Field Programmable Gate Arrays Third Edition With 359 Figures and 98 Tables Book with CD-ROM 123 Dr Uwe Meyer-Baese Florida State University College of Engineering Department Electrical & Computer Engineering Pottsdamer St 2525 Tallahassee, Florida 32310 USA E-Mail: Uwe.Meyer-Baese@ieee.org Originally published as a monograph Library of Congress Control Number: 2007933846 ISBN 978-3-540-72612-8 Springer Berlin Heidelberg New York This work is subject to copyright All rights are reserved, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilm or in any other way, and storage in data banks Duplication of this publication or parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965, in its current version, and permission for use must always be obtained from Springer Violations are liable for prosecution under the German Copyright Law Springer is a part of Springer Science+Business Media springer.com © Springer-Verlag Berlin Heidelberg 2007 The use of general descriptive names, registered names, trademarks, etc in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use Typesetting: Data conversion by the author Production: LE-TEX Jelonek, Schmidt & Vöckler GbR, Leipzig Cover Design: WMXDesign GmbH, Heidelberg Printed on acid-free paper 60/3180/YL 543210 To my Parents, Anke and Lisa Preface Field-programmable gate arrays (FPGAs) are on the verge of revolutionizing digital signal processing in the manner that programmable digital signal processors (PDSPs) did nearly two decades ago Many front-end digital signal processing (DSP) algorithms, such as FFTs, FIR or IIR filters, to name just a few, previously built with ASICs or PDSPs, are now most often replaced by FPGAs Modern FPGA families provide DSP arithmetic support with fast-carry chains (Xilinx Virtex, Altera FLEX) that are used to implement multiply-accumulates (MACs) at high speed, with low overhead and low costs [1] Previous FPGA families have most often targeted TTL “glue logic” and did not have the high gate count needed for DSP functions The efficient implementation of these front-end algorithms is the main goal of this book At the beginning of the twenty-first century we find that the two programmable logic device (PLD) market leaders (Altera and Xilinx) both report revenues greater than US$1 billion FPGAs have enjoyed steady growth of more than 20% in the last decade, outperforming ASICs and PDSPs by 10% This comes from the fact that FPGAs have many features in common with ASICs, such as reduction in size, weight, and power dissipation, higher throughput, better security against unauthorized copies, reduced device and inventory cost, and reduced board test costs, and claim advantages over ASICs, such as a reduction in development time (rapid prototyping), in-circuit reprogrammability, lower NRE costs, resulting in more economical designs for solutions requiring less than 1000 units Compared with PDSPs, FPGA design typically exploits parallelism, e.g., implementing multiple multiply-accumulate calls efficiency, e.g., zero product-terms are removed, and pipelining, i.e., each LE has a register, therefore pipelining requires no additional resources Another trend in the DSP hardware design world is the migration from graphical design entries to hardware description language (HDL) Although many DSP algorithms can be described with “signal flow graphs,” it has been found that “code reuse” is much higher with HDL-based entries than with graphical design entries There is a high demand for HDL design engineers and we already find undergraduate classes about logic design with HDLs [2] Unfortunately two HDL languages are popular today The US west coast and Asia area prefer Verilog, while US east coast and Europe more frequently VIII Preface use VHDL For DSP with FPGAs both languages seem to be well suited, although some VHDL examples are a little easier to read because of the supported signed arithmetic and multiply/divide operations in the IEEE VHDL 1076-1987 and 1076-1993 standards The gap is expected to disappear after approval of the Verilog IEEE standard 1364-1999, as it also includes signed arithmetic Other constraints may include personal preferences, EDA library and tool availability, data types, readability, capability, and language extensions using PLIs, as well as commercial, business, and marketing issues, to name just a few [3] Tool providers acknowledge today that both languages have to be supported and this book covers examples in both design languages We are now also in the fortunate situation that “baseline” HDL compilers are available from different sources at essentially no cost for educational use We take advantage of this fact in this book It includes a CD-ROM with Altera’s newest MaxPlusII software, which provides a complete set of design tools, from a content-sensitive editor, compiler, and simulator, to a bitstream generator All examples presented are written in VHDL and Verilog and should be easily adapted to other propriety design-entry systems Xilinx’s “Foundation Series,” ModelTech’s ModelSim compiler, and Synopsys FC2 or FPGA Compiler should work without any changes in the VHDL or Verilog code The book is structured as follows The first chapter starts with a snapshot of today’s FPGA technology, and the devices and tools used to design stateof-the-art DSP systems It also includes a detailed case study of a frequency synthesizer, including compilation steps, simulation, performance evaluation, power estimation, and floor planning This case study is the basis for more than 30 other design examples in subsequent chapters The second chapter focuses on the computer arithmetic aspects, which include possible number representations for DSP FPGA algorithms as well as implementation of basic building blocks, such as adders, multipliers, or sum-of-product computations At the end of the chapter we discuss two very useful computer arithmetic concepts for FPGAs: distributed arithmetic (DA) and the CORDIC algorithm Chapters and deal with theory and implementation of FIR and IIR filters We will review how to determine filter coefficients and discuss possible implementations optimized for size or speed Chapter covers many concepts used in multirate digital signal processing systems, such as decimation, interpolation, and filter banks At the end of Chap we discuss the various possibilities for implementing wavelet processors with two-channel filter banks In Chap 6, implementation of the most important DFT and FFT algorithms is discussed These include Rader, chirp-z, and Goertzel DFT algorithms, as well as Cooley–Tuckey, Good–Thomas, and Winograd FFT algorithms In Chap we discuss more specialized algorithms, which seem to have great potential for improved FPGA implementation when compared with PDSPs These algorithms include number theoretic transforms, algorithms for cryptography and errorcorrection, and communication system implementations Preface IX The appendix includes an overview of the VHDL and Verilog languages, the examples in Verilog HDL, and a short introduction to the utility programs included on the CD-ROM Acknowledgements This book is based on an FPGA communications system design class I taught for four years at the Darmstadt University of Technology; my previous (German) books [4, 5]; and more than 60 Masters thesis projects I have supervised in the last 10 years at Darmstadt University of Technology and the University of Florida at Gainesville I wish to thank all my colleagues who helped me with critical discussions in the lab and at conferences Special thanks to: M Acheroy, D Achilles, F Bock, C Burrus, D Chester, D Childers, J Conway, R Crochiere, K Damm, B Delguette, A Dempster, C Dick, P Duhamel, A Drolshagen, W Endres, H Eveking, S Foo, R Games, A Garcia, O Ghitza, B Harvey, W Hilberg, W Jenkins, A Laine, R Laur, J Mangen, J Massey, J McClellan, F Ohl, S Orr, R Perry, J Ramirez, H Scheich, H Scheid, M Schroeder, D Schulz, F Simons, M Soderstrand, S Stearns, P Vaidyanathan, M Vetterli, H Walter, and J Wietzke I would like to thank my students for the innumerable hours they have spent implementing my FPGA design ideas Special thanks to: D Abdolrahimi, E Allmann, B Annamaier, R Bach, C Brandt, M Brauner, R Bug, J Burros, M Burschel, H Diehl, V Dierkes, A Dietrich, S Dworak, W Fieber, J Guyot, T Hattermann, T Hă auser, H Hausmann, D Herold, T Heute, J Hill, A Hundt, R Huthmann, T Irmler, M Katzenberger, S Kenne, S Kerkmann, V Kleipa, M Koch, T Kră uger, H Leitel, J Maier, A Noll, T Podzimek, W Praefcke, R Resch, M Ră osch, C Scheerer, R Schimpf, B Schlanske, J Schleichert, H Schmitt, P Schreiner, T Schubert, D Schulz, A Schuppert, O Six, O Spiess, O Tamm, W Trautmann, S Ullrich, R Watzel, H Wech, S Wolf, T Wolf, and F Zahn For the English revision I wish to thank my wife Dr Anke Meyer-Bă ase, Dr J Harris, Dr Fred Taylor from the University of Florida at Gainesville, and Paul DeGroot from Springer For financial support I would like to thank the DAAD, DFG, the European Space Agency, and the Max Kade Foundation If you find any errata or have any suggestions to improve this book, please contact me at Uwe.Meyer-Baese@ieee.org or through my publisher Tallahassee, May 2001 Uwe Meyer-Bă ase Preface to Second Edition A new edition of a book is always a good opportunity to keep up with the latest developments in the field and to correct some errors in previous editions To so, I have done the following for this second edition: • Set up a web page for the book at the following URL: http://hometown.aol.de/uwemeyerbaese The site has additional information on DSP with FPGAs, useful links, and additional support for your designs, such as code generators and extra documentation • Corrected the mistakes from the first edition The errata for the first edition can be downloaded from the book web page or from the Springer web page at www.springer.de, by searching for Meyer-Baese • A total of approximately 100 pages have been added to the new edition The major new topics are: – The design of serial and array dividers – The description of a complete floating-point library – A new Chap on adaptive filter design • Altera’s current student version has been updated from 9.23 to 10.2 and all design examples, size and performance measurements, i.e., many tables and plots have been compiled for the EPF10K70RC240-4 device that is on Altera’s university board UP2 Altera’s UP1 board with the EPF10K20RC240-4 has been discontinued • A solution manual for the first edition (with more than 65 exercises and over 33 additional design examples) is available from Amazon Some additional (over 25) new homework exercises are included in the second edition Acknowledgements I would like to thank my colleagues and students for the feedback to the first edition It helped me to improve the book Special thanks to: P Ashenden, P Athanas, D Belc, H Butterweck, S Conners, G Coutu, P Costa, J Hamblen, M Horne, D Hyde, W Li, S Lowe, H Natarajan, S Rao, M Rupp, T Sexton, D Sunkara, P Tomaszewicz, F Verahrami, and Y Yunhua From Altera, I would like to thank B Esposito, J Hanson, R Maroccia, T Mossadak, and A Acevedo (now with Xilinx) for software and hardware support and the permission to include datasheets and MaxPlus II on the CD of this book From my publisher (Springer-Verlag) I would like to thank P Jantzen, F Holzwarth, and Dr Merkle for their continuous support and help over recent years 760 Glossary VHSIC VLIW VLSI Very-high-speed integrated circuit Very long instruction word Very large integrated ICs WDT WFTA WSS Watchdog timer Winograd Fourier transform algorithm Wide sense stationary XC XNOR Xilinx FPGA family Exclusive NOR gate YACC Yet another compiler-compiler D CD-ROM File: “1readme.ps” The accompanying CD-ROM includes • A full version of the Quartus II software • Altera datasheets for Cyclone II devices • All VHDL/Verilog design examples and utility programs and files To install the Quartus II 6.0 web edition software first read the licence agreement carefully Since the Quartus II 6.0 web edition software uses many other tools (e.g., GNU, Berkeley Tools, SUN microsystems tool, etc.) you need to agree to their licence agreements too before installing the software To install the software start the self-extracting file quartusii_60_web_edition.exe on the CD-ROM in the Altera folder After the installation the user must register the software through Altera’s web page at www.altera.com in order to get a permanent licence key Otherwise the temporary licence key expires after the 30-day grace period and the software will no longer run Altera frequently update the Quartus II software to support new devices and you may consider downloading the latest Quartus II version from the Altera webpage directly, but keep in mind that the files are large and that the synthesis results will differ slightly for another version Altera’s University program now delivers the files via download, which can take long time with a 56 Kbit/s MODEM The design examples for the book are located in the directories book3e/vhdl and book3e/verilog for the VHDL and Verilog examples, respectively These directories contain, for each example, the following four files: • • • • The The The The VHDL or Verilog source code (*.vhd and *.v) Quartus project files (*.qpf) Quartus setting files (*.qsf) Simulator wave form file (*.vwf) For the design fun_graf, the block design file (*.bdf) is included in book3e/vhdl For the examples that utilize M4Ks (i.e., fun_text, darom, and trisc0), the memory initialization file (*.mif) can be found on the CD-ROM To simplify the compilation and postprocessing, the source code directories include the additional (*.bat) files and Tcl scripts shown below: 762 D CD-ROM File: “1readme.ps” File Comment qvhdl.tcl Tcl script to compile all design examples Note that the device can be changed from Cyclone II to Flex, Apex or Stratix just by changing the comment sign # in column of the script qclean.bat Cleans all temporary Quartus II compiler files, but not the report files (*.map.rpt), the timing analyzer output files (*.tan.rpt), and the project files *.qpf and *.qsf qveryclean.bat Cleans all temporary compiler files, including all report files (*.rep) and project files Use the DOS prompt and type quartus_sh -t qvhdl.tcl > qvhdl.txt to compile all design examples and then qclean.bat to remove the unnecessary files The Tcl script qvhdl.tcl is included on the CD The Tcl script language developed by the Berkeley Professor John Ousterhout [346, 347, 348] (used by most modern CAD tools: Altera Quartus, Xilinx ISE, ModelTech, etc.) allows a comfortable scripting language to define setting, specify functions, etc Given the fact that many tools also use the graphic toolbox Tcl/Tk we have witnessed that many tools now also looks almost the same Two search procedures (show_fmax and show_resources) are used within the Tcl script qvhdl.tcl to display resources and Registered Performance The script includes all settings and also alternative device definitions The protocol file qvhdl.txt has all the useful synthesis data For the trisc0 processor, for instance, the list for the Cyclone II device EP2C35F672C6 is: trisc0 fmax: 115.65 MHz ( period = 8.647 ns ) trisc0 LEs: 198 / 33,216 ( < % ) trisc0 M4K bits: 5,120 / 483,840 ( % ) trisc0 DSP blocks: / 70 ( % ) The results for all examples are summarized in Table B.1, p 731 Other devices are prespecified and include the EPF10K20RC240-4 and EPF10K70RC240-4 from the UP1 and UP2 University boards, the EP20K200EFC484-2X from the Nios development boards, and three devices from other DSP boards available from Altera, i.e., the EP1S10F484C5, EP1S25F780C5, and EP2S60F1020C4ES Using Compilers Other Then Quartus II Synopsys FPGA CompilerII The main advantage of using the FPGA CompilerII (FC2) from Synopsys was that it was possible to synthesize examples for other devices like Xilinx, Vantis, Actel, or QuickLogic with the same tool The Tcl scripts vhdl.fc2, and verilog.fc2, D CD-ROM File: “1readme.ps” 763 respectively, were provided the necessary commands for the shell mode of FC2, i.e., fc2_shell in the second edition of the book [57] Synopsys, however, since 2006 no longer supports the FPGA CompilerII and it is therefore not a good idea to use the compiler anymore since the newer devices can not be selected Model Technology By using the synthesizable public-domain models provided by the EDIF organization (at www.edif.org), it is also possible to use other VHDL/Verilog simulators then Quartus II Using MTI and VHDL For VHDL, the two files 220pack.vhd and 220model.vhd must first be compiled For the ModelSim simulator vsim from Model Technology Inc., the script mti_vhdl.do can be used for device-independent compilation and simulation of the design examples The script is shown below: # -# Model Technology VHDL compiler script for the book # Digital Signal Processing with FPGAs (3.edition) # Author-EMAIL: Uwe.Meyer-Baese@ieee.org # -echo Create Library directory lpm vlib lpm echo Compile lpm package vcom -work lpm -explicit -quiet 220pack.vhd 220model.vhd echo Compile chapter entitys vcom -work lpm -quiet example.vhd fun_text.vhd echo vcom vcom vcom Compile chapter entitys -work lpm -explicit -quiet add1p.vhd add2p.vhd -work lpm -explicit -quiet add3p.vhd mul_ser.vhd -work lpm -explicit -quiet cordic.vhd echo vcom vcom echo vcom vcom vcom Compile chapter components -work lpm -explicit -quiet case3.vhd case5p.vhd -work lpm -explicit -quiet case3s.vhd Compile chapter entitys -work lpm -explicit -quiet fir_gen.vhd fir_srg.vhd -work lpm -explicit -quiet dafsm.vhd darom.vhd -work lpm -explicit -quiet dasign.vhd dapara.vhd echo Compile chapter entitys vcom -work lpm -explicit -quiet iir.vhd iir_pipe.vhd vcom -work lpm -explicit -quiet iir_par.vhd echo Compile chapter entitys vcom -work lpm -explicit -quiet cic3r32.vhd cic3s32.vhd vcom -work lpm -explicit -quiet db4poly.vhd db4latti.vhd echo Compile chapter entitys 764 D CD-ROM File: “1readme.ps” vcom -work lpm -explicit -quiet rader7.vhd ccmul.vhd vcom -work lpm -explicit -quiet bfproc.vhd echo Compile chapter entitys vcom -work lpm -explicit -quiet rader7.vhd ccmul.vhd vcom -work lpm -explicit -quiet bfproc.vhd echo Compile edition entitys vcom -work lpm -explicit -quiet div_res.vhd div_aegp.vhd vcom -work lpm -explicit -quiet fir_lms.vhd fir6dlms.vhd echo Compile edition entitys from chapter vcom -work lpm -explicit -quiet cmul7p8.vhd arctan.vhd vcom -work lpm -explicit -quiet ln.vhd sqrt.vhd echo Compile edition entitys from chapter vcom -work lpm -explicit -quiet rc_sinc.vhd farrow.vhd vcom -work lpm -explicit -quiet cmoms.vhd echo Compile edition entitys from chapter vcom -work lpm -explicit -quiet reg_file.vhd trisc0.vhd Start the ModelSim simulator and then type mti_vhdl.do to execute the script Using MTI and Verilog Using the Verilog interface with the lpm library from EDIF, i.e., 220model.v, needs some additional effort When using 220model.v it is necessary to specify all ports in the Verilog lpm components There is an extra directory book3e/verilog/mti, which provides the design examples with a full set of lpm port specifications The designs use ‘\include "220model.v" at the beginning of each Verilog file to include the lpm components, if necessary Use the script mti_v1.csh and mti_v2.csh to compile all Verilog design examples with Model Technology’s vcom compiler In order to load the memory initialization file (*.mif), it is required to be familiar with the programming language interface (PLI) of the Verilog 1364-1995 IEEE standard (see LRM Sect 17, p 228 ff) With this powerful PLI interface, conventional C programs can be dynamically loaded into the Verilog compiler In order to generate a dynamically loaded object from the program convert_hex2ver.c, the path for the include files veriuser.h and acc_user.h must be specified Use -I when using the gcc or cc compiler under SUN Solaris Using, for instance, the gcc compiler under SUN Solaris for the Model Technology Compiler, the following commands are used to produce the shared object: gcc -c -I//modeltech/include convert_hex2ver.c ld -G -B symbolic -o convert_hex2ver.sl convert_hex2ver.o By doing so, ld will generate a warning “Symbol referencing errors,” because all symbols are first resolved within the shared library at link time, but these warnings can be ignored It is then possible to use these shared objects, for instance, with Model Technology’s vsim in the first design example fun_text.v, with D CD-ROM File: “1readme.ps” vsim -pli convert_hex2verl.sl 765 lpm.fun_text To learn more about PLIs, check out the Verilog IEEE standard 1364-1995, or the vendor’s user manual of your Verilog compiler We can use the script mti_v1.do to compile all Verilog examples with MTI’s vlog Just type mti_v1.do in the ModelTech command line But vlog does not perform a check of the correct component port instantiations or shared objects A second script, mti_v2.do, can be used for this purpose Start the vsim simulator (without loading a design) and execute the DO file with mti_v2.do to perform the check for all designs Using Xilinx ISE The conversion of designs from Altera Quartus II to Xilinx ISE seems to be easy if we use standard HDL Unfortunately there a couple of issues that needs to be addressed We assume that the ModelTech simulation environment and the web version (i.e., no core generation) is used We like to discuss in the following a couple of items that address the ISE/ModelTech design entry We describe the Xilinx ISE 6.2 web edition and ModelTech 5.7g version 1) The Xilinx simulation with timing (“Post-Place & Route”) uses a bitwise simulation model on the LUT level Back annotations are only done for the I/O ports, and are ALL from type standard_logic or standard_logic_vector In order to match the behavior and the simulation with timing we therefore need to use only the standard_logic or standard_logic_vector data type for I/O As a consequence no integers, generic, or custom I/O data type, (e.g., like the subtype byte see cordic.vhd) can be used 2) The ISE software supports the development of testbenches with the “Test Bench Waveform.” Use New Source under the Project menu This waveform will give you a quick way to generate a testbench that is used by ModelTech, both for behavior as well as simulation with timing There are some benefits and drawbacks with the testbencher For instance, you can not assign negative integers in the waveforms, you need to build the two’s complement, i.e., equivalent unsigned number by hand 3) If you have feedback, you need to initialize the register to zero in your HDL code You can not this with the testbencher: for instance, ModelTech initialize all integer signals to the smallest value, i.e., −128 for a 8-bit number, if you add two integers, the result will be −128 − 128 = −256 < −128 and ModelTech will stop and report an overflow Some designs, e.g., cordic, cic3r32, cic3s32, only work correctly in behavior simulation if all integers are changed to standard_logic_vector data type Changing I/O ports alone and using the conversion function does not always guarantee correct simulation results 4) Simulation with timing usually needs one clock cycle more than behavior code until all logic is settled The input stimuli should therefore be zero in the first clock cycle (ca 100 ns) and, if you want to match behavior and timing simulation, and the design uses a (small) FSM for control, you need to add a synchronous or asynchronous reset You need to this for the following 2/e designs: dafsm, dadrom, dasign, db4latti, db4poly, div aegp, div res, iir par, mul ser, rader7 Just add a control part for the FSM like this: 766 D CD-ROM File: “1readme.ps” IF rising_edge(clk) THEN -IF reset = ’1’ THEN -state