System on chip interfaces for low power design

System on Chip Interfaces for Low Power Design System on Chip Interfaces for Low Power Design Sanjeeb Mishra Neeraj Kumar Singh Vijayakrishnan Rousseau AMSTERDAM • BOSTON • HEIDELBERG • LONDON NEW YORK • OXFORD • PARIS • SAN DIEGO SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO Morgan Kaufmann is an imprint of Elsevier Acquiring Editor: Todd Green Editorial Project Manager: Lindsay Lawrence Project Manager: Punithavathy Govindaradjane Designer: Alan Studholme Morgan Kaufmann is an imprint of Elsevier 225 Wyman Street, Waltham, MA 02451, USA Copyright # 2016 Sanjeeb Mishra, Neeraj Kumar Singh, and Vijayakrishnan Rousseau Published by Elsevier Inc All rights reserved Intel owns copyright for the materials created by the Authors in the scope of the Author’s employment at Intel The views and opinions expressed in this work are those of the authors and not necessarily represent the views of Intel Corporation No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or any information storage and retrieval system, without permission in writing from the publisher Details on how to seek permission, further information about the Publisher’s permissions policies and our arrangements with organizations such as the Copyright Clearance Center and the Copyright Licensing Agency, can be found at our website: www.elsevier.com/permissions This book and the individual contributions contained in it are protected under copyright by the Publisher (other than as may be noted herein) Notices Knowledge and best practice in this field are constantly changing As new research and experience broaden our understanding, changes in research methods, professional practices, or medical treatment may become necessary Practitioners and researchers must always rely on their own experience and knowledge in evaluating and using any information, methods, compounds, or experiments described herein In using such information or methods they should be mindful of their own safety and the safety of others, including parties for whom they have a professional responsibility To the fullest extent of the law, neither the Publisher nor the authors, contributors, or editors, assume any liability for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions, or ideas contained in the material herein ISBN: 978-0-12-801630-5 British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the Library of Congress For information on all MK publications visit our website at www.mkp.com Copyright Permissions Designations used by companies to distinguish their products are often claimed as trademarks or registered trademarks In all instances in which Morgan Kaufmann Publishers is aware of a claim, the product names appear in initial capital or all capital letters Readers, however, should contact the appropriate companies for more complete information regarding trademarks and registration CSI-2℠, D-PHY℠, and DSI℠ are service marks, and SLIMbus® is a registered trademark, of MIPI Alliance, Inc in the US and other countries MIPI, MIPI Alliance, and the dotted rainbow arch and all related trademarks and trade names are the exclusive property of MIPI Alliance, Inc., and cannot be used without its express prior written permission Figures below are Copyright # 2005-2015 by MIPI Alliance, Inc and used by permission All rights reserved Figures 4.35, 4.36, 4.37, 4.38, 4.40, 4.41, 4.42, 4.43, 4.44, 4.45, 4.46, 4.47, 4.48, 4.48, 4.49, 4.50, 4.51, 4.52, 4.53, 4.54, 4.55, 5.12, 5.13, 5.14, 5.17, 5.18, 5.19, 5.20, 5.21, 5.55, 5.57, 5.58, 5.59, 5.60, 5.61, 5.62, and 5.63 Figure below is reprinted with permission granted by ANSI on behalf of INCITS to use material from INCITS 452-2009[R2014] All copyrights remain in full effect All rights reserved Figure 7.6 Figures below are reprinted with permission from the Video Electronics Standards Association, Copyright VESA, www.VESA.org All rights reserved Tables 4.1, 4.2, 4.3, 4.4, 4.5 and 4.6 Figures 4.13, 4.14, 4.15, 4.17, 4.18, 4.19, 4.23, 4.26, 4.27, 4.28, 4.29, 4.30, 4.31, and 4.32 Figures below are reprinted with permission from High-Definition Multimedia Interface Version 1.3a, Copyright, HDMI 1.3a All rights reserved Figures 4.9, 4.10, 4.11, and 4.12 Tables 4.11 and 4.12 Figures below are reprinted with permission from PCI-SIG All rights reserved Figures 5.42, 5.44, 5.46, 5.47, 5.52, and 5.54 Figures below are reprinted with permission from USB 3.0 Copyright Intel Corporation All rights reserved Figures 5.26, 5.27, C.1, C.2, C.3, C.4, and C.5 Figure below is reprinted with permission from Intel® LPC interface specification v1.1, copyright # 2002, Intel Corporation Figure 8.3 v Dedicated to my late brother, Sandeep, who passed away at such a young age —Neeraj Kumar Singh Acknowledgments We would like to express gratitude to the people who helped us through this book; some of them directly and many others indirectly It’s impossible to not risk missing someone, but we will attempt anyway First and foremost, we would like to acknowledge Balamurali Gouthaman for writing the sensor, security, and input/output interface chapters; and Kiran Math for his help on the storage section of the book We would like to thank Stuart Douglas and David Clark for their help in reviewing the concept, structure, and content of the book and arranging for publishing with Elsevier—David, your meticulous reviews helped the book significantly Thank you so much Todd Green, Lindsay Lawrence, Punitha Govindaradjane and all the Elsevier publishing team for the outstanding work, help, guidance, and support; you have gone the extra mile to make the book what it is We would like to thank Intel management, in particular Pramod Mali and Siddanagouda S., for the support and encouragement Above all, we thank our family and friends for their understanding, support, and for being continuous sources of encouragement xv Chapter SoC Design Fundamentals and Evolution This chapter discusses various system design integration methodologies along with their advantages and disadvantages The chapter also explains the motivation for current system designs to move from “system on board” designs toward “system on chip” (SoC) designs In discussing the motivation for the move toward SoC design, the chapter also discusses the typical chip design flow tradeoffs as well as how they influence the design choices INTRODUCTION A system is something that achieves a meaningful purpose Like everything else, it depends on the context A computer system will have hardware components (the actual machinery) and software components, which actually drive the hardware to achieve the purpose For example, talking about a personal computer (also commonly known as a PC), all the electronics are hardware, and the operating system plus additional applications that you use are software However, in the context of this book, by a system we mean the hardware part of the system alone Figure 1.1 shows a rough block diagram of a system The system in the diagram consists of a processing unit along with the input/ output devices, memory, and storage components Typical system components Roughly speaking, a typical system would have a processor to the real processing, a memory component to store the data and code, some kind of input system to receive input, and a unit for output In addition, we should have an interconnection network to connect the various components together so that they work in a coherent manner It should be noted that based on the usage model and applicability of the system, the various components in the system may come in differing formats For example, in a PC environment, keyboard, and mouse may form the input subsystem, whereas in a tablet system they may be replaced by a touch screen, and in a digital CHAPTER SoC Design Fundamentals and Evolution Main memory Input devices Processor Output devices Secondary memory/storage n FIGURE 1.1 A system with memory, processor, input/output, and interconnects health monitoring system the input system may be formed by a group of sensors In addition to the bare essentials, there may be other subsystems like imaging, audio, and communication In Chapter we’ll talk about various subsystems in general, involving: Processor Memory Input and output Interconnects Domain-specific subsystems (camera, audio, communication, and so on) Categorization of computer systems Computer systems are broadly categorized as: general-purpose computer systems like personal computers, embedded systems like temperature control systems, and real-time systems like braking control systems Generalpurpose computing systems are designed to be more flexible so that they can be used for different types of functions, whereas embedded systems are designed to address a specific function and are not meant to be generic They are usually embedded as part of a larger device, and the user seldom directly interacts with such a system Real-time systems are embedded systems with stringent response time requirements All these computing systems are built using the same basic building blocks as shown in Figure 1.1 The flavor of the building blocks may vary from system to system because the design parameters and design requirements are different For example, since embedded systems have a fixed known usage, the components can optimally be chosen to meet that functional requirement The System approach to design general-purpose system, on the other hand, might have to support a range of functionality and workloads, and therefore components need to be chosen keeping in mind the cost and user experience for the range of applications Similarly the components for real-time systems need to be chosen such that they can meet the response time requirement SYSTEM APPROACH TO DESIGN Due to the tighter budget on cost, power, and performance discussed in the previous section, the whole system is being thought about and designed as complete and not as an assembly of discrete pieces The philosophy of system design thereby brings the opportunity to optimize the system for a particular usage There is no real change in the system functionality; it’s just that it is a different way of thinking about the system design We already talked about the typical system components; next we will discuss the hardware software co-design, followed by various system design methodologies Hardware software co-design As discussed earlier, a system in general has some hardware accompanied by some software to achieve the purpose Generally, the system’s functionality as a whole is specified by the bare definition of the system However, what part of the system should be dedicated hardware and what should be software is a decision made by the system architect and designer The process of looking at the system as a whole and making decisions as to what becomes hardware and what becomes a software component is called hardware software co-design Typically there are three factors that influence the decision: n n Input, output, memory, and interconnects need to have hardware (electronics) to the fundamental part expected from them However, each of these blocks typically requires some processing; for example, touch data received from the input block needs to be processed to detect gestures, or the output data needs to be formatted specifically to suit the display These processing parts, generally speaking, are part of the debate as to whether a dedicated hardware piece should the processing or whether the general-purpose processor should be able to take care of the processing in part or full The second factor that contributes to the decision is the experience that we want to deliver to the user What this means is that, depending on the amount of data that needs to be processed, the quality of the output that is expected, the response time to the input, and so on, we have to decide the quality of the dedicated hardware that should be used, CHAPTER SoC Design Fundamentals and Evolution n and also this helps make the decision as to which processing should be done by dedicated hardware and which by software running on the CPU The assumption here is that hardware dedicated to doing specific processing will be faster and more efficient, so wherever we need faster processing, we dedicate hardware to the processing, such as, for example, graphics processing being processed by a graphics processing unit The third factor is the optimality There are certain types of processing that take a lot more time and energy when done by general-purpose processing units as opposed to a specialized custom processor, such as digital signal processing and floating point computations, which have dedicated hardware (DSP unit and floating point unit, respectively) because they are optimally done in hardware System design methodologies Early on, the scale of integration was low, and therefore to create a system it was necessary to put multiple chips, or integrated circuits (ICs), together Today, with very-large-scale integration (VLSI), designing a system on a single chip is possible So, just like any other stream, system design has evolved based on the technological possibilities of the generation Despite the fact that system on a single chip is possible, however, there is no one design that fits all In certain cases the design is so complex that it may not fit on a single chip Why? Based on the transistor size (which is limited by the process technology) and size of the die (again limited by the process technology) there is a limited number of transistors that can be placed on a chip If the functionality is complex and cannot be implemented in that limited number of transistors, the design has to be broken out into multiple chips Also, there are other scalability and modularity reasons for not designing the whole system in one single chip In the following section we’ll discuss the three major system design approaches: system on board (SoB), system on chip (SoC), and system in a package (SiP) or on a package (SoP) System on board SoB stands for system on board This is the earliest evolution of system design Back in the 1970s and 1980s when a single chip could only so much, the system was divided into multiple chips and all these chips were connected via external interconnect interfaces over a printed circuit board SoB designs are still applicable today for large system designs and system designs in which disparate components need to be put together to work as a system 378 APPENDIX C USB 3.0 Non-SuperSpeed Super Speed Fullspeed Highspeed Lowspeed USB 3.0 host Extended connector(s) SuperSpeed extended connector(s) Non-SuperSpeed (USB 2.0) Composite cable SuperSpeed hub SuperSpeed function USB 2.0 hub NonSuperSpeed function USB 3.0 hub USB 3.0 peripheral device Note: Simultaneous operation of SuperSpeed and non-SuperSpeed modes is not allowed for peripheral devices n FIGURE C.4 USB 3.0 architecture Similarly, USB 3.0 devices can be connected to a USB 2.0 bus The mechanical and electrical backward/forwards compatibility for USB 3.0 is again possible due to the composite cable and associated connector assemblies The composite cable and associated connector assemblies basically form the dual bus architecture In other words, USB 3.0 devices have both SuperSpeed and non-SuperSpeed bus interfaces The non-SuperSpeed part of the interface is responsible for providing the backward compatibility with USB 2.0 interface Similarly, USB 3.0 hosts include both SuperSpeed and nonSuperSpeed bus interfaces The non-SuperSpeed part of the interface is responsible for interfacing with USB 2.0 devices if plugged Both the SuperSpeed and non-SuperSpeed parts of the bus interface are parallel buses that may be active simultaneously USB 3.0 hubs, again similar to their USB 2.0 Summary 379 counterparts, are a specific class of USB device The purpose of USB hubs is to provide additional connection points to the bus if more than what is provided by the host is required The physical interface of USB 3.0 also has USB 2.0 electrical, mechanical, in addition to the expected SuperSpeed physical interface for the buses Therefore, USB 3.0 cables have eight primary conductors: three twisted signal pairs for USB data paths and a power pair Figure C.5 shows a logical diagram of the USB connectors The device discovery, configuration, and other characteristics of USB 3.0 remain the same as USB 2.0 Table C.1 attempts a comparison of various USB characteristics between USB 2.0 and USB 3.0 SUMMARY So, as can be seen from the earlier description, USB 3.0, the next-generation USB interface to USB 2.0, is backward-compatible to USB 2.0, and it provides higher speed, better power management, scalability, and interconnectability Despite the fact that USB 3.0 is backward-compatible to USB 2.0, there are some fundamental differences Given USB’s prominence in the market today, and given that USB 3.0 is addressing the data rate concerns that new usage and devices were starting to pose with USB 2.0, and improving the power management even further to lower overall power consumption, USB is going to remain the interface of choice for device interfacing VBUS VBUS D+ D– +++ SSTX+ SSTX– SSRX+ SSRX– +++ GND n FIGURE C.5 USB 3.0 cable connector +++ +++ +++ +++ D+ D– SSRX+ SSRX– SSTX+ SSTX– GND 380 APPENDIX C USB 3.0 Table C.1 Comparison of Key Attributes in USB 2.0 and USB 3.0 Interface Characteristic USB 2.0 USB 3.0 Standard release April 2000 November 2008 Data rate Low-speed (1.5 Mbps), full-speed (12 Mbps), and high-speed (480 Mbps) SuperSpeed (5.0 Gbps) Data interface Half-duplex two-wire differential signaling Unidirectional data flow with negotiated directional bus transitions Dual-simplex, four-wire differential signaling separate from USB 2.0 signaling Simultaneous bidirectional data flows Number of wires (within cable) Bus transaction protocol Host directed, polled traffic flow Packet traffic is broadcast to all devices Host directed, asynchronous traffic flow Packet traffic is explicitly routed Power management Port-level suspend with two levels of entry/exit latency Device-level power management Multilevel link power management supporting idle, sleep, and suspend states Link, device, and function-level power management Bus power Support for low/high bus-powered devices with lower power limits for un-configured and suspended devices Same as for USB 2.0 with a 50% increase for unconfigured power and an 80% increase for configured power Port state transition Port hardware detects connect events System software uses port commands to transition the port into an enabled state Port hardware detects connect events and brings the port into operational state ready for SuperSpeed data communication Maximum cable length 5m 3m Appendix D USB OTG (On The Go) USB On-The-Go, also known as USB OTG, is a specification that allows USB devices such as digital audio players, printers, or mobile phones to act as a host This capability allows some other USB devices like a USB flash drive, digital camera, mouse, or keyboard to be attached to them while allowing them to function normally This kind of capability enables a number of exciting features; for example, a digital camera can directly be connected to printer (acting as host) for printing pictures, or audio player (acting as host) can connect to cell phone and download songs, etc So, fundamentally, use of USB OTG allows these devices to switch back and forth between the roles of host and client devices For instance, a mobile phone may read from removable media as the host device or behave as a USB Mass Storage Device when connected to a host computer MOTIVATION AND PROTOCOL OVERVIEW OF USB OTG USB, the most common interface today, was originally designed as an interface between PCs and peripherals By definition, USB communication occurs between a host and a peripheral The original intent was to place the heavier workload on the PC (host) and to allow USB peripherals to be fairly simple Accordingly, the USB specification requires that PCs most of the work, such as, for example, to provide power to peripherals, and to support all defined speeds and data flow types As computing resources became less expensive, the line between PCs and other products blurred, and therefore many devices that are not PCs in the classic sense have a need to connect directly to peripherals: printers connect directly with cameras, for example, or mobile phones may need to connect to USB headsets, and so on So, to enable these kinds of usage scenarios, these devices added the USB host function; however, they needed to function in ways that differ from standard PC USB hosts: although they need to provide host capability for some devices, they are not required to support the full range of USB peripherals For example, connecting a camera to a printer 381 382 APPENDIX D USB OTG (On The Go) makes a lot of sense, but the printer manufacturers may not think it is quite as important for the printer to support a USB GPS dongle So, these devices acting as USB hosts are defined as Targeted Hosts A Targeted Host is a USB host that supports a specific, targeted set of peripherals The developer of each Targeted Host product defines the set of supported peripherals on a Targeted Peripheral List (TPL) A Targeted Host needs to provide only the power, bus speeds, data flow types, and so on, that the peripherals on its TPL require There are two categories of Targeted Hosts: Embedded Hosts: An Embedded Host (EH) product provides Targeted Host functionality over one or more Standard-A or Micro-AB receptacles EH products may also offer USB peripheral capability, delivered separately via one or more Type-B receptacles On-The-Go: An OTG product is a portable device that uses a single Micro-AB receptacle (and no other USB receptacles) to operate at times as a USB Targeted Host and at times as a USB peripheral OTG devices will operate as a standard peripheral when connected to a standard USB host OTG devices can also be attached to each other There are protocols defined in the specification to identify the master (host) and slave (peripheral) in such cases The USB OTG and EH Supplement to the USB 2.0 specification introduced three new communication protocols: ▪ Attach Detection Protocol allows an OTG device, EH, or USB device to determine attachment status in the absence of power on the USB bus ▪ Session Request Protocol allows both communicating devices to control when the link’s power session is active In standard USB, only the host is capable of doing so This allows fine control over the power consumption ▪ Host Negotiation Protocol (HNP) allows the two devices to exchange their host/peripheral roles, provided both are OTG dual-role devices By using HNP for reversing host/peripheral roles, the USB OTG device is capable of acquiring control of data-transfer scheduling The actual protocol and the framework of data transfer on OTG devices remain the same as USB 2.0 (and USB 3.0 for SuperSpeed OTG devices) The OTG devices will behave as standard USB hosts or devices when connected to standard (non-OTG) USB devices References 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 http://www.uefi.org http://www.trustedcomputinggroup.org http://www.pcisig.com/home AGP3.0 interface specification ACPI 5.0 specification Baytrail platform External Design specification Computer Organization and Design, Fifth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design TCG Specification Architecture Overview version 1.4 SD Host controller Simplified specification version 2.00 http://www.usb.org http://www.mipi.org Information technology – AT attachment – ATA/ATAPI command set (ATA8ACS) revision 4a May 21, 2007 Intel Low Pin Count Interface Specification_v1.1 Document Number 251289–001 https://en.wikipedia.org/wiki/Floyd%E2%80%93Steinberg_dithering https://en.wikipedia.org/wiki/Intel_Display_Power_Saving_Technology Digital Visual Interface DVI Revision 1.0, 02 April 1999 VESA Enhanced Extended Display Identification Data Standard (Defines EDID Structure Version 1, Revision 3) Release A, Revision February 9, 2000 VESA Notebook Panel Standard Version October 22, 2007 VESA DisplayPort Standard Version 1, Revision 1a January 11, 2008 VESA Embedded DisplayPort (eDP) Standard Version 1.4 28 February, 2013 High-Definition Multimedia Interface Specification Version 1.3a November 10, 2006 High-Definition Multimedia Interface Specification Version 1.4a Extraction of 3D Signaling Portion March 4, 2010 Display Data Channel Command Interface Standard Version 1.1 October 29, 2004 VESA Enhanced Display Data Channel (EDDC) Standard Version 1.2 December 26, 2007 DDR2 SDRAM SPECIFICATION JESD79-2F November 2009 PC2–5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification JEDEC Standard No 21C MIPI Alliance Specification for Display Serial Interface (DSI℠) Version 1.3 – MIPI Alliance Specification for D-PHY℠ Version 1.2 MIPI Alliance Specification for Serial Low-power Inter-chip Media Bus (SLIMbus®) Version 1.01.01 383 384 References 30 31 32 33 34 MIPI Alliance Specification for Camera Serial Interface (CSI-2℠) Version 1.00 www.wikipedia.org Universal Serial Bus Specification Revision Texas instrument AN-452 MICROWIRE Serial Interface Philips Semiconductor I2S specification Index Note: Page numbers followed by f indicate figures and t indicate tables A B Accelerated Graphics Port (AGP) access request, 215, 215f addressing modes and bus operation, 214–217 block diagram, 212, 212f CCCC field, 215–216, 216t command definitions, 216–217 core logic, 213 extensions, 218 LLL field, 215–216 memory access pipelining, 213 vs PCI, 214–215 performance-oriented extensions, 211–212 pin description, 217 pipelined operation pipe depth, 213 sample bus sequencing, 214f sideband control signals, 213 state transition, 213–214, 214f versions, 217 ACPI states device states, 26 global and system states mechanical off state (G3), 24f, 26 sleeping state (G1), 24f, 25 soft-off state (G2/S5), 24f, 25 working state (G0/S0), 24, 24f processor states, 26–27, 27f Active power management, 22 Adaptive voltage scaling (AVS), 19, 20f Advanced audio distribution profile (A2DP), 42–43 AGP See Accelerated Graphics Port (AGP) Application-specific integrated circuit (ASIC) advantages, 7–8 disadvantages, Assisted GPS (AGPS), 269–270, 270t, 270f Audio, 39, 39f capture and playback, 39, 39f clock regeneration, 74–75 data delivery rate, 76–77 interfaces, 135–138 Battery charging chemical reactions, 321 overcharging, 321 power management, 49 types, 320–321 USB charging, 324–325 architecture, 329, 330f components, 328–329 connection, 323, 323f legacy devices, 325 power delivery specification, 327–329, 327t specification, 322–324 standard downstream port (SDP), 322 USB-IF BC1.2 specification, 325–327 VBUS, 327–328 Bay Trail platform’s connectivity diagram, 30–51, 32f Big endian systems, 33, 35f Bluetooth, 42–43 classes, 348, 349t computer, 351 connection, 350 inquiry, 350 interfaces UART, 239–243 USB, 243 interference, 349 paging, 350 pairing, 350 pictorial representation, 349, 350f power modes, 350, 351t remote controls, 356 Bulk endpoints, 175 Burst transmission, 122, 123f Bus and fabric technology, 34–35 C Camera control interface (CCI) data transfer protocol, 236 I2C protocol, 236 message formats, 236 read/write operations, 236–237 unsupported I2C features, 237 Camera serial interface (CSI) checksum generation, 231 data-type (DT) classes, 229, 230t ECC, 228, 230 end of transmission (EoT) sequence, 225–228 frame format digital interlaced video example, 234, 235f digital interlaced video example with accurate synchronization timing information, 234, 235f frame end packet, 232 frame start packet, 232 general frame format examples, 234, 234f generic short packet data type codes, 231, 231t packet position of sync, 232, 233f packet sequence in frame transmission, 232 synchronization short packet data type codes, 231, 231t interleaved video data stream examples, 229, 230f layer definition, 224, 225f long packet, 227 low-level protocol, 228 low-power state (LPS), 225–227, 226f packet footer, 228 packet header, 228, 230 packet identifier (PI), 229 packet spacing, 227f, 228–229 physical signaling of packet, 225–227, 226f short packet, 227 start of transmission (SoT), 228 virtual channel (VC) identifier, 229, 229f Card firmware, 252–253, 252f CCI See Camera control interface (CCI) Chip design tradeoff, 10–11 CISC, 33, 34f Clock gating, 19 385 386 Index Clock stretching, 131 Command descriptor block (CDB), 292 Communication interfaces Bluetooth interfaces UART, 239–243 USB, 243 GPS interfaces, 267–271 NFC interfaces, 271–273 2G/3G/4G interfaces, 254–267 Wi-Fi interfaces PCIe, 253 SDIO, 244–253 USB, 253 Computer systems, 2–3, 2f Connected standby power management, 22–23 Control endpoints, 175 CPU endianness, 33, 35f instruction set architecture (ISA), 30–33, 32f RISC and CISC, 33, 34f CSI See Camera serial interface (CSI) D DDC See Display Data Channel (DDC) Debug interfaces, 51 active debugging, 360, 360f JTAG communication model, 364, 364f connectors, 364–365 evolution, 363 interface connectivity diagram, 363, 363f Nexus, 365–366 passive debugging, 359–360, 360f UART, 361 USB, 361–362, 361f Demodulation, 41–42 Device states, 26 Differential GPS (DGPS), 269 Differential signaling, 65, 65f Digital Visual Interface (DVI) differential signaling, 65, 65f parallel digital display interface pixel and timing information transmission, 62, 62f timing diagram, 63–64, 63f serial digital display interface bit periods, 64–65, 65f serializing data, 64–65, 64f TMDS link architecture dual link, 69 single link, 69 transition-minimized differential signaling control codes, 67 running disparity, 66–67 source and sink details, 67–69, 68f XNOR truth table, 66–67, 66t XOR truth table, 66, 66t DigRF BBIC-RFIC interface, 255f, 264–265 versions, 264 v1.12 interface, 265, 265f v3 interface, 266, 266f v4 interface, 266, 266f Display and graphics, 37–38, 38f Display Data Channel (DDC) I2C slave addresses, 58–60, 59t presence detect, 60 purposes, 56 versions, 60, 60t Display interfaces classification, 60–61 DDC (see Display Data Channel (DDC)) DisplayPort (DP), 78–91 DVI, 62–69 EDID (see Extended Display Identification Data (EDID)) external display Digital Visual Interface, 62–69 VGA, 61–62 frame buffer, 53, 54f graphics processing unit (GPU), 53 HDMI (see High-Definition Multimedia Interface (HDMI)) horizontal blanking interval, 54, 55f internal display (see Internal display interface) pixel format, 53–54 RBT, 54–55 rendering, 53 between source and sink, 55, 56f 3D displays fundamentals, 124–125 role, 125 stereoscopy, 124 vertical blanking interval, 54, 55f DisplayPort (DP) audio transmission without video, 88–90 AUX channel operation reply transaction, 82–83 request transaction, 82 self-clocking with Manchester II coding, 81, 81f transaction format, 82, 82f connector, 90–91, 90f data transport channels, 78, 79f Hot plug detect (HPD) uses, 90 link operation link frequency/rate, 85 maximum possible bandwidth, 85, 86t link training pre-emphasis, sample waveform, 84, 84f training pattern, 83 voltage swing, sample waveform, 83–84, 84f main link operation ANSI 8b/10b encoding technique, 80 character to symbol mapping, 80, 81f control/comma/K codes, 81 positive and negative disparities, 80 micro packets secondary streams, 88 transfer unit (TU), 86–88 Display serial interface (DSI) advantages, 103–105 checksum generation for long packet payloads, 123–124 data and multilane management byte packaging, 113, 115f lane distribution and lane merging, 112–116, 114f DPHY signaling, 108–109, 108f, 110f DPHY specification, 107–108, 107f ECC, 122–123 functional layers, 105–107, 106f HS transmission mode end of transmission (EoT), 112, 113f phases, 111f, 112 start of transmission (SoT), 112, 112f LP transmission mode escape mode signaling, 109, 111, 111f phases, 109 state transition during bus turnaround (BTA), 111, 111f packet sequence HS data transmission sequence, 113, 115f virtual channels, 116 packet structure data type code, 117, 118t interleaved data streams, 117, 118f Index 387 long data packet structure, 116–117, 117f short data packet structure, 116–117, 116f pixel data transmission burst transmission, 122, 123f complete video mode, 122, 122f display timing parameters, 119, 120f packet position, 119, 121f pixel packing, 117, 120f video mode interface timing (legend), 119, 121f, 122, 123f system design, 105–107, 105f DVFS See Dynamic voltage and frequency scaling (DVFS) DVI See Digital Visual Interface (DVI) Dynamic power, 15 Dynamic RAM (DRAM) activate command, 276 capacitor leakage, 277–278 DDR SDRAM burst operations, 281 DDR2 SDRAM, 278–279, 279t DDR3 SDRAM, 279–280, 279t signals, 280 transfer rates, 278, 278t rows and columns, 276–277, 276f timing parameters, 276–277, 277t Dynamic voltage and frequency scaling (DVFS), 18–19, 19f E ECC See Error-correction code (ECC) EDID See Extended Display Identification Data (EDID) eDP See Embedded DisplayPort (eDP) EISA bus See Extended ISA (EISA) bus Embedded DisplayPort (eDP) features, 98 power sequencing, 100–102, 101f PSR (see Panel self refresh (PSR)) Endianness, 33, 35f Endpoints enumeration process, 173 and pipes, 175–176, 176f types, 175 Error-correction code (ECC), 122–123, 228, 230 European Committee for Standardization (CEN), 373 Extended Display Identification Data (EDID) block details, 58, 59t block map, 57, 57t blocks, 57, 57t tag description, 58, 58t Extended ISA (EISA) bus, 193 External display interfaces DVI, 62–69 VGA, 61–62 F FM broadcasting, 44–45 Frame format, SPDIF Frequency/voltage throttling, 20 G Global positioning system (GPS), 44 assisted GPS (AGPS), 269–270, 270t, 270f differential GPS (DGPS), 269 UART, 270 USB, 270 working principle, 267–270 Graphics, 37–41, 38f, 40f control and data flow, 192, 192f EISA bus, 193 ISA bus, 193 MCA bus, 193 PCI (see Peripheral Components Interconnect (PCI)) VLBus, 193–194, 194f H Hands-free profile (HFP), 42–43 Hardware software co-design, 3–4 HDMI Licensing, 372 High-Definition Multimedia Interface (HDMI) audio data transmission audio clock regeneration, 74–75 audio data delivery rate, 76–77 audio principles number of channels, 74 sampling rate, 74 sampling size, 74 block diagram, 70–71, 70f connectors, pin assignments Type A, 78, 78t Type B, 78, 79t data encoding and packetization period description, 71, 73t period placement, 71, 72f TMDS periods and encoding, 71, 73f infoframes, 77 TV technology, 69–70 High-speed inter-chip (HSIC) characteristics, 258 vs USB, 258–259, 259–260f and USB signaling and operation, 260–261 High speed synchronous serial interface (HSI), 263–264, 263f Hot plug detect (HPD), 60, 90 HSI See High speed synchronous serial interface (HSI) HSIC See High-speed inter-chip (HSIC) HSync signal, 61 Human interface devices (HIDs), 347–348 I I2C bus See Inter-IC (I2C) bus IC design, 9–10 Idle power management, 22 Imaging, 41 Imaging subsystem See Camera control interface (CCI)Camera serial interface (CSI) Industry standard architecture (ISA), 193 Infoframes, 77 Input device interfaces Bluetooth classes, 348, 349t computer, 351 connection, 350 inquiry, 350 interference, 349 paging, 350 pairing, 350 pictorial representation, 349, 350f power modes, 350, 351t DIN5, 345 keyboard, 345–351 mouse, 351–352 PS/2 interface drawbacks, 346–347 protocol overview, 346 remote controls (see Remote controls) RS232, 351–352, 352f USB, 347–348, 348f 388 Index Institute of Electrical and Electronics Engineers Standards Association (IEEE-SA), 372 Instruction set architecture (ISA), 30–33, 32f Intel SoC Baytrail connectivity diagram, 367–368, 369–370t reference design, 367 Inter-IC (I2C) bus camera control interface (CCI), 236–237 Display Data Channel (DDC), 58–60, 59t features, 128 interface, 271–273, 271–272f multimedia interfaces features, 128 protocol, 128–133 speeds, 134 protocol clock stretching, 131 data format, 130, 131f general call address, 132–133 master-slave relationship, 128–129 multimaster mode, 133, 133f slave address and R/W bit, 131 START and STOP condition, 130, 130f 10-bit addressing, 131–132, 132f, 132t wired and logic, 129–130, 129f security interfaces, 309–310, 310f speeds categories, 134 fast-mode and fast-mode plus, 134 high-speed mode (Hs-mode), 134 Video Graphics Array (VGA), 61 Inter IC sound (I2S) bus three-wire serial bus requirements SDA line, 136–137, 137f three-wire serial bus, 135, 136f word select (WS) line, 137, 137f timing, 137–138 Internal display interface backlight power reduction, 93 challenges, 91 DSI (see Display serial interface (DSI)) embedded DisplayPort, 98–102 LCD operation, 92 LVDS, 95–97 MIPI, 102–124, 104f panel power saving, 92–94 panel power sequence, 92 remote frame buffer with display, 93–94, 94f display memory fetches, 93, 93f eDP, 94 LVDS, 94 MIPI DSI, 94 International Electrotechnical Commission (IEC), 373 International Organization for Standardization (ISO), 373 International Telecommunication Union (ITU), 373 Interrupt endpoints, 175 ISA See Industry standard architecture (ISA) Isochronous endpoints, 175 J Joint Electron Device Engineering Council (JEDEC), 372 Joint test action group (JTAG) communication model, 364, 364f connectors, 364–365 evolution, 363 interface connectivity diagram, 363, 363f JTAG See Joint test action group (JTAG) L Leakage power, 14 Little endian systems, 33, 35f Locality of reference, 47 Low pin count (LPC) interface advantages, 311 block diagram, 312, 313f cycles, 313–314, 314t goals, 311 power management, 314 signal definition, 311–312, 312t supported device classes, 311 Low Voltage Differential Signaling (LVDS) dithering, 95 18 BPP/24 BPP mode, 95 power sequencing, 95–97 6-bit/8-bit single channel data mapping diagrams, 95, 96–97f transmitted data, 95 LVDS See Low Voltage Differential Signaling (LVDS) M MCA bus See Microchannel architecture (MCA) bus Media encode/decode, 40, 40f Memory interfaces See Nonvolatile memoryVolatile memory Messgae pipes, 176 Microchannel architecture (MCA) bus, 193 Micro packets secondary streams, 88 transfer unit (TU) size, 86, 86f timing diagram for 18 BPP, 88, 89f timing diagram for 24 BPP, 87–88, 87f transmission, 87–88, 87f Micro-wire (μ-wire) serial interface shifting in and shifting out, 138, 139f system interface, 139–140, 139f MIPI See Mobile Industry Processor Interface (MIPI) Mobile Industry Processor Interface (MIPI), 102–124, 104f, 371 Mobile telecommunication standards, 43–44 Modularity, 34–35 Modulation, 41–42 Moore’s law, Multimaster bus configuration, 133, 133f MultiMediaCard and secure digital (MMC/SD) physical dimension, 285–286 physical interface, 286 pin diagram, 286–287 Multimedia interfaces audio, inter IC sound (I2S) bus, 135–138 graphics components (see Graphics) I2C bus features, 128 protocol, 128–133 speeds, 134 imaging subsystems (see Camera control interface (CCI); (Camera serial interface (CSI)) micro-wire serial interface, 138–192 Multimedia subsystem audio, 39, 39f Bluetooth, 42–43 communication, 41–45 FM broadcasting, 44–45 global positioning system (GPS), 44 graphics, 39–41, 40f imaging, 41 mobile telecommunication standards, 43–44 Index 389 near field communication (NFC), 45 Wi-Fi/wireless LAN, 43 N Near field communication (NFC), 45 data corruption, 308 data manipulation attacks, 308 eavesdropping, 307 I2C protocol, 309–310, 310f interception attack, 308, 308f interfaces, 271–273 security provisions, 308–309 tag, 307 Network on chip (NoC), 37, 37f Nexus, 365–366 NFC See Near field communication (NFC) Non return to zero inverted (NRZI) encoding bit stuffing, 168–170, 170f internal wire colors, 170–171, 171f scheme, 168 speed identification, 170–171 Nonvolatile memory, 45–47 NRZI encoding See Non return to zero inverted (NRZI) encoding P Packet-switched network, 37, 37f Panel self refresh (PSR) entry, 99, 99f exit, 99–100, 100f SDP, 98–100 system level diagram, 98–99, 99f PCI See Peripheral Components Interconnect (PCI) PCIe See PCI express (PCIe) PCI Express (PCIe) data link layer, 222 design guiding principles, 218–219 :logical block diagram, switch, 219, 220f performance characteristics, 223 physical layer, 222 protocol architecture, 221 software layer, 223 system architecture, 218–219, 220f transaction layer, 223 2G/3G/4G interfaces, 257 Wi-Fi interfaces, 253 Peripheral component interconnect eXtended (PCI-X), 211 Peripheral Component Interconnect Special Interest Group (PCI-SIG), 372 Peripheral Components Interconnect (PCI) AGP addressing modes and bus operation, 214–217 block diagram, 212, 212f core logic, 213 extensions, 218 memory access pipelining, 213 performance-oriented extensions, 211–212 pin description, 217 pipelined operation, 213–214, 214f versions, 217 bus operation arbitration, 204 bridges, 205, 206f burst cycle, 203 command encoding, 202, 202t configuration space decoding, 207–208 data transfer control, 203–204, 204f IO space decoding, 207 memory space decoding, 207, 207t physical address spaces, 205 software generation, 209, 209f Type and Type configuration, 208, 208f design principles data integrity, 198 ease of use, 197 flexibility, 198 high performance, 197, 197t interoperability and reliability, 198 longevity, 198 low cost, 197 software compatibility, 198 PCIe (see PCI Express (PCIe)) PCI Special Interest Group (PCI-SIG), 196–197, 196f PCI 2.3 specification, 196, 196f vs PCI-X, 211 performance improvement collapsing, 210 combining, 210 delayed transaction, 210–211 merging, 210 posted writes, 210 transaction ordering, 210 signal definition additional signals, 201 address and data pins, 199 arbitration pins, 200 :error-reporting pins, 200 interface control pins, 200 interrupt pins, 200–201 JTAG/boundary scan pins, 201 pin list, 198 sideband signals, 201–202 64-bit bus extension signals, 201 SMBus interface pins, 201 system, 198 system architecture, 194–196, 195f Power consumption in IC dynamic power, 15 static power, 14–15 of system, 21–27, 22f Power delivery, 49 Power efficiency, 13, 34–35 Power gating, 20 Power interfaces battery charging (see Battery charging) voltage regulator module (VRM), 319–320 Power management, 49 Power optimization in IC capacitance, 16 power management strategies, 17 power saving (see Power-saving mechanisms) silicon parameters, 17–18, 17f switching activity, 16 voltage, 16 importance, 13–21 at system level ACPI states, 23–27, 24f active power management, 22 connected standby power management, 22–23 idle power management, 22 Power-saving mechanisms adaptive voltage scaling (AVS), 19, 20f clock gating, 19 frequency/voltage throttling, 20 multiple Vdd DVFS, 18–19, 19f static voltage scaling, 18, 18f power gating, 20 process improvement, 20 Presence detect See Hot plug detect (HPD) Processor states, 26–27, 27f PSR See Panel self refresh (PSR) 390 Index R Radio-based remote controls, 355–356 RBT See Reduced blanking timing (RBT) Read only memory (ROM) EPROM, 281–282 limitation, 281 PROM, 281–282 SPI features, 282–283 functionality, 284 multi I/O device, 284–285 SS line, 283–284 system architecture, 283, 283f Reduced blanking timing (RBT), 54–55 Remote controls Bluetooth, 356 IR remotes mechanism, 354 Power On/Off and Volume Up/Down, 353 pros and cons, 355 radio controls, 355–356 Remote frame buffer (RFB), 93–94 RISC, 33, 34f RS-232 communication, 256–257 S SAS See Serial attached SCSI (SAS) Scalability, 34–35 SDA line, 136–137, 137f SDIO See Secure digital input output (SDIO) Secure digital input output (SDIO) card design, 250–251, 250f card types, 250 connectivity diagrams, 245, 245f electrical and timing control, 252 format, 244 functions, 250 interface signals, 245, 245f multi-slot system, 248 SD bus command packet, 246–247, 247f command processing, 246–247 connectivity, 245–246, 245f interface signals, 245f, 246 responses, 247 specification, 247 SD host controller, 245f, 248, 249t SDIO and SD combo cards, 249 software operation, 252–253, 252f Security interfaces NFC data corruption, 308 data manipulation attacks, 308 eavesdropping, 307 I2C protocol, 309–310, 310f interception attack, 308, 308f security provisions, 308–309 tag, 307 smart card contactless smart card, 315 contact smart card, 315 electrical specifications, 315 encryption, 315 PCMCIA interface, 315–316 SDIO interface, 316–317, 316f SIM, 314–315 USB interface, 315 TPM LPC (see Low pin count (LPC) interface) SoC, 310 Sensors, 344t interfaces, 49–51, 50f inter-integrated circuit advantages, 333–334 disadvantage, 335 Linux operating systems, 334 operation, 331–333, 332t sensor hub-based configuration, 334–335, 334f transactions, 331, 332f Windows 8, 334 SPI advantage, 336 configuration, 335, 336f error detection/correction, 337 four-wire serial bus, 335 full-duplex communication, 337 GPIO lines, 337 operation, 335–336 pull-up resistors, 337 UART, 337–338 Bluetooth and GPS chips, 341 clock-skew-related problems, 340 clock synchronization, 340 configuration, 338, 338f features, 339 flow control and error detection, 340–341 operation, 339–340, 339f time-multiplexing, 340 waveform, 338, 339f USB architecture, 341 differential signaling, 341 evaluation boards, 343 HID-Over-USB specification, 343 operation, 342 pipes, 342 power consumption, 343 selective suspend state, 343 Serial ATA, 296–298, 297f Serial attached SCSI (SAS) direct attach, 300 domain, 299 expander attach, 300 expanders, 300 leveraging elements, 299 narrow port, 300 point-to-point configurations, 299–300 protocols, 300–302 specification, 299 wide port, 300 Serial low-power inter-chip media bus (SLIMbus) audio subsystems with legacy interfaces, 140, 141f bandwidth, audio application, 156t, 161 channels, 148–149 clock features, 147–148 clock frequencies cardinal frequencies, 155 natural frequency, 155 root frequency, 155 clock gears, 155, 156t component model, 141, 144f connectivity diagram, 140, 142f data channels and segments, 149, 150f data features, 146–147, 147f data space and control Space, 148–149 device addressing, 149 devices and device class, 143–144, 144f features, 141–158, 142f framer device, 145 frame structure elements, 152–153, 174f frame, 152, 152f subframe, 150f, 153 superframe, 153, 154f generic device, 145, 147f guide channel, 149 information element (IE), 144–145 interface device, 145 low-voltage CMOS (LVCMOS) I/Os, 146 Index 391 manager device, 145 message channel, 149 message flow boot behavior, 157–158, 158f bus management message sequence, 158, 160f device enumeration state diagram, 158, 159f messaging, 150f, 156–157 port, 150, 150f pushed protocol, 151–152 SLIMbus physical layer (PHY), 145–146, 148f transport protocol, 151, 151t value element (VE), 145 Serial Peripheral Interface (SPI) advantage, 336 configuration, 335, 336f error detection/correction, 337 four-wire serial bus, 335 full-duplex communication, 337 GPIO lines, 337 operation, 335–336 pull-up resistors, 337 Small computer system interface (SCSI) architecture model-3, 290–291, 291f blocking and sharing, 294–295 command protocol standard, 293–294, 294t, 294f definition, 287–288 device-independent mechanism, 287 history, 288–290, 289f, 290t initiators and targets CDB, 292 IO operation, 291–292 physical connectors, 292 standards, 293 switch modes, 292 transports, 293 limitation, 295 point-to-point serial transport benefits, 295–296 fibre channel, 296 SAS, 299–302 SATA, 296–298, 297f SER/DES, 295 USB, 298, 298t Standby power, 15 Static power, 14–15 Static voltage scaling, 18, 18f Stream pipes, 176 Subscriber identification module (SIM) card, 314–315 Super speed inter-chip (SSIC) block diagram, 261, 261f M-PHY, 262 standards, 262 System on board (SoB) advantages, 4–5 disadvantages, System on chip (SoC) advantages, 5–6 block diagram, 29, 30f internal, 30f bus and fabric technology, 34–35 connectivity diagram, Bay Trail platform, 32f CPU endianness, 33, 35f instruction set architecture (ISA), 30–33, 32f RISC and CISC, 33, 34f debug interfaces, 51 disadvantages, display and graphics, 37–38, 38f graphic components (see Graphics) input devices, 51 interconnect paradigm, 35–36 memory hierarchy, 46, 46f nonvolatile, 45 volatile, 45 volatile vs nonvolatile, 45–47 multimedia subsystem audio, 39, 39f Bluetooth, 42–43 communication, 41–45 FM broadcasting, 44–45 global positioning system (GPS), 44 graphics, 39–41, 40f imaging, 41 mobile telecommunication standards, 43–44 near field communication (NFC), 45 Wi-Fi/wireless LAN, 43 network on chip (NoC), 37, 37f packet-switched network, 37, 37f power battery charging, 49 delivery, 49 logical connection, 47, 48f management, 49 security, 47, 48f sensor interfaces, 49–51, 50f two-level system bus hierarchy, 36, 36f System on package (SoP) advantages, disadvantages, System on programmable chip (SoPC) advantages, disadvantages, System states mechanical off state (G3), 24f, 26 sleeping state (G1), 24f, 25 soft-off state (G2/S5), 24f, 25 working state (G0/S0), 24, 24f T Telecommunication ecosystem, 254, 254f 10-bit addressing, 131–132, 132f, 132t 3D displays display interface role, 125 fundamentals, 124–125 stereoscopy, 124 3D rendering, 39–40 Time coalescing, 23 Time to market (TTM), 11 Transcode, 40 Transition-minimized differential signaling, 66–69 Trusted Computing Group (TCG), 47 Trusted platform module (TPM) LPC (see Low pin count (LPC) interface) SoC, 310 2G/3G/4G interfaces DigRF, 264–267, 265–266f HSI, 263–264, 263f HSIC (see High-speed inter-chip (HSIC)) modem, 255, 255f PCIe, 257 RS-232, 256–257 SIM card, 255, 256t SSIC, 261–262 USB, 257 U UART See Universal Asynchronous Receiver Transmitter (UART) Universal Asynchronous Receiver Transmitter (UART) block diagram, 241–242, 241f 392 Index Universal Asynchronous Receiver Transmitter (UART) (Continued) Bluetooth controller/host, 242 core system, 242 and GPS chips, 341 clock-skew-related problems, 340 clock synchronization, 340 configuration, 338, 338f connectivity diagram, 242, 243f controller, 240 debug interfaces, 361 features, 339 flow control and error detection, 340–341 GPS interfaces, 270 host system, 240 operation, 339–340, 339f sensor interfaces, 337–341 time-multiplexing, 340 waveform, 338, 339f Universal flash storage (UFS) communication architecture, 303–305, 303f system architecture, 302, 303f Universal Serial Bus (USB) architecture, 161, 341 bandwidth allocation, 185 benefits, 162 Bluetooth interfaces, 243 commercial hub, 164, 164f connectors, 166–171, 167f control pipe, 166 data pipe, 166 data transfers, 166 debug interfaces, 361–362, 361f descriptors configuration, 186, 187t device descriptor table, 185–186, 186t device qualifier, 189 endpoint, 188, 188t interface association descriptor (IAD), 187, 187t interface descriptor, 187, 188t Microsoft OS, 189 report, 189 string, 189, 189t device classes, 190, 190t device functions, 164 differential signaling, 341 electrical characteristics communication states, 168, 169t differential signaling, 167 for high-speed device, 167–168 on low- and full-speed devices, 167 on receiver, 167 transceiver, 168 endpoints enumeration process, 173 and pipes, 175–176, 176f types, 175 enumeration and configuration, 191–192 evaluation boards, 343 GPS interfaces, 270 HID-Over-USB specification, 343 Host Controller Interface Specifications, 165 multi-tier hub and functions, 164–165, 165f NRZI encoding bit stuffing, 168–170, 170f internal wire colors, 170–171, 171f scheme, 168 speed identification, 170–171 operation, 342 packet description data packets, 180, 180f handshake packets, 181 special packets, 181 start of frame (SOF) packet, 179–180, 179f, 180t token packets, 179–181 packet fields, 178–179, 178f, 178t pipes, 164–165, 342 power consumption, 343 protocol end of packet (EOP) pattern, 176 start of frame (SOF), 176 transaction, 176–177, 177f selective suspend state, 343 suspend mode current frame packet, 172–173 global suspend, 173 power states, 173, 174f selective suspend, 173 transactions bulk transfers, 184–185, 199f control transactions, 181–182, 182f control transfer types, 182, 182f IN/read/upstream transactions, 181 interrupt transfers, 183–184, 183f, 186 isochronous transfers, 184, 184f OUT/write/downstream transactions, 181 2G/3G/4G interfaces, 257 USB 1.1, 162 USB 2.0, 162–163, 165 USB 3.0, 163 VBUS power, 171–172 Wi-Fi interfaces, 253 USB See Universal Serial Bus (USB) USB 3.0, 163 architecture, 377, 378f cross configuration, 377 interoperability, 377 logical diagram, 379, 379f mechanism, 377–379 physical interface, 379 power, 377 speed, 375–376 vs USB 2.0, 379, 380t USB 3-A connector, 375, 376f USB 3-B connector, 375, 376f USB Implementers’ Forum (USB-IF), 373 V Very-large-scale integration (VLSI), VESA local bus (VLBus), 193–194, 194f VGA See Video Graphics Array (VGA) Video Electronics Standards Association (VESA), 371 Video Graphics Array (VGA) HSync signal, 61 I2C protocol, 61 VLBus See VESA local bus (VLBus) Volatile memory, 45–47 Voltage regulator module (VRM), 319–320 W Wi-Fi interfaces PCIe, 253 SDIO, 244–253 USB, 253 Wi-Fi/wireless LAN, 43 Wireless communication, 41–42 Word select (WS) line, 137, 137f ... reasons for not designing the whole system in one single chip In the following section we’ll discuss the three major system design approaches: system on board (SoB), system on chip (SoC), and system. .. connected standby power management 22 CHAPTER Understanding Power Consumption Fundamentals Power Power consumption consumed in wake during sleep Active mode power consumption n FIGURE 2.6 Power. .. are designed in at the chip level have a far-reaching impact In the following section we will categorize power consumption in two ways: power consumption at the IC level and power consumption