The architecture of computer hardware and systems software an information technology approach ch09

Chapter 9: Input/Output The Architecture of Computer Hardware and Systems Software: An Information Technology Approach 3rd Edition, Irv Englander John Wiley and Sons 2003 Basic Model  Processing speed or program execution  determined primarily by ability of I/O operations to stay ahead of processor Input Chapter Input / Process Output 9-2 I/O Considerations Speed Issues     CPU operates at speeds much faster than the fastest I/O device Devices operate at different speeds Bursts of data Block data transfer required for some devices Coordination     Several devices perform I/O simultaneously Unexpected input Various input formats Status information needed for each device Chapter Input / 9-3 I/O Device Interface Issues  Different formats  parallel interface  serial interface  Buffering of data  Burst vs stream  Different control requirements  electromechanical Chapter Input / 9-4 Examples of I/O Devices Chapter Input / 9-5 Simple I/O Configuration Chapter Input / 9-6 I/O Modules Functions  Recognizes messages from device(s) addressed to it and accepts commands from the CPU  Provides a buffer where the data from memory can be held until it can be transferred to the disk  Provides the necessary registers and controls to perform a direct memory transfer  Physically controls the device  Copies data from its buffer to the device/from the CPU to its buffer  Notifies with interrupts Chapter Input / 9-7 Input/Output Modules  Programmed I/O  CPU controlled I/O  Interrupt Driven I/O  External input controls  Direct Memory Access Controllers  Method for transferring data between main memory and a device that bypasses the CPU Chapter Input / 9-8 Programmed I/O  I/O data and address registers in CPU  One word transfers  Address information for each I/O device  LMC I/O capability for 100 devices  Full instruction fetch/execute cycle  Primary use:  keyboards  communication with I/O modules (see DMA) Chapter Input / 9-9 Programmed I/O Chapter Input / 9-10 DMA Initiation and Control Chapter Input / 9-25 Basic CPU-Memory-I/O Pathway* Chapter Input / 9-26 Bus Configuration Chapter Input / 9-27 Bus Characteristics        Data width in bits carried simultaneously Throughput, i.e., data transfer rate in bits per second Point-to-Point vs Multipoint Parallel vs Serial Use Distance Protocol Chapter Input / 9-28 Bus Hierarchy  Processor bus: on-chip  Cache bus (backside bus)  Memory bus (front-side bus)  connects the memory subsystem and processor  Local I/O bus  high-speed bus used to connect performance critical peripherals to memory and processor  Examples: PCI, VESA Local Bus  Standard I/O bus  connects slower peripherals (ISA) to Local I/O bus Chapter Input / 9-29 Wintel Bus Systems     ISA: Industry Standard Architecture MCA: Micro Channel Architecture EISA: Extended Industry Standard Architecture Local Bus  PCI: Peripheral Component Interconnect (also Apple, Sun, Compaq Alpha Server)  VLB: VESA (Video Electronics Standards Association) Local Bus  AGP: Accelerated Graphics Port  Point-to-point channel from graphics controller to main memory  Co-exists with PCI Chapter Input / 9-30 Compaq 7000 and 10000 System Architecture Chapter Input / 9-31 External Interface Buses and Ports  Parallel port  Serial port  RS-232C and RS-422 buses  SCSI  Small Computer System Interface  USB, USB-2  Universal Serial Bus  IEEE 1394  Firewire  i.link Chapter Input / 9-32 SCSI Bus  ANSI standard but multiple variations  Really an I/O bus rather than simple interface  Supports multiple devices from a single SCSI port Chapter Input / 9-33 USB  Multipoint bus  Hubs provide multiple connection points for I/O devices  Supports 127 devices Topology Example Root Hub Hub Hub Hub Chapter Input / 9-34 USB and FireWire (IEEE 1394)  Both serial, multipoint bus specifications  Add/remove devices w/o powering down  Packet protocol for isochronous data transfer  Isochronous: delivery at regular time intervals  Guarantee specified throughput Chapter Input / 9-35 USB vs FireWire  USB: slow to medium speed data transfer applications, i.e., storage devices  12 Mbits/sec  USB-2: high-speed data transfer  480Mbits/sec  FireWire: high-speed data transfer, i.e., full motion video with sound  400 Mbits/sec to 3.2 Gbits/sec Chapter Input / 9-36 Typical FireWire Configuration  Network-like characteristics  Device controllers independent Chapter Input / 9-37 Channel Architecture  Used in IBM mainframe computers  Channel subsystem  Separate I/O processor that serves as a CPU for I/O operations  Channel control words  Programs that transfer data between memory and an I/O device using DMA  Subchannels  Connected to a control unit module through one or more channel paths  Similar role to a device controller Chapter Input / 9-38 I/O Channel Architecture Chapter Input / 9-39 ... addressed to it and accepts commands from the CPU  Provides a buffer where the data from memory can be held until it can be transferred to the disk  Provides the necessary registers and controls... Access     Transferring large blocks of data Direct transfer to and from memory CPU not actively involved in transfer itself Required conditions for DMA  The I/O interface and memory must... I/O bus Chapter Input / 9-29 Wintel Bus Systems     ISA: Industry Standard Architecture MCA: Micro Channel Architecture EISA: Extended Industry Standard Architecture Local Bus  PCI: Peripheral