The architecture of computer hardware and systems software an information technology approach ch12

Chapter 12 Three System Examples The Architecture of Computer Hardware and Systems Software: An Information Technology Approach 3rd Edition, Irv Englander John Wiley and Sons  2003 Three System Examples  X86 Family  PowerPC  IBM System 360/370/390/zSeries Family Chapter 12 12-2 The X86 Family         System Overview The CPU Registers Instruction Set Addressing Modes Advanced Design Features CPU Organization The IA-64 Itanium Architecture Chapter 12 12-3 System Overview  Bus-oriented system I/O  Nonmaskable interrupts  Emergency situations  Single maskable interrupt  Supports 32 prioritized interrupts  IRQ0 to IRQ31  Upon receiving an interrupt, the CPU reads an address on the data lines that is used to jump to the interrupt routine Chapter 12 12-4 The CPU  Downward software compatibility  Disabled protected mode  Compatible with the original 8088 architecture  Original Intel 8088 CPU     16-bit processing and registers 16-bit internal data bus 8-bit external data bus 20-bit memory addressing – 1Mbyte total  Current Pentium CPUs     256-bit internal data bus 64-bit external data bus levels of memory caching Added floating point, multimedia, virtual storage, and multitasking support Chapter 12 12-5 Registers  8088, 8086, 80286     general-purpose registers segment registers flag register Instruction pointer, and various control registers  80386 – added segment registers  80486  80-bit floating point registers  Various floating point control registers  Pentium MMX  added registers for multimedia support  Pentium III  128-bit SIMD registers and control register Chapter 12 12-6 General Purpose Registers Chapter 12 12-7 Instruction Set and Format Data transfer Integer arithmetic Branch Bit manipulation, rotate and shift  String manipulation     Chapter 12  Input / Output  Flag  Instructions added in later processors  Floating point  MMX  SIMD 12-8 Chapter 12 12-9 Addressing Modes        Register Immediate Direct Addressing Register Deferred Addressing Base Addressing Indexed Addressing Base Indexed Addressing Chapter 12 12-10 Advanced Design Features  Two levels of system access  Supervisor (privileged) state  User (problem) state  Memory is protected at the segment, page, and block levels  “Hint” bits in branching instructions aid in making accurate branch predictions Chapter 12 12-26 CPU Organization  Superscalar, pipelined design  Cache memory is standard  Execution units in the PowerPC 4751 CPU Chapter 12 12-27 The IBM 360/370/390/zSeries  Architectural Evolution of 360/370/390/zSeries Computers  The CPU  S/390 Registers  Instruction Set  Addressing Modes  Advanced Features  CPU Organization  S/390 Block Diagram Chapter 12 12-28 Architectural Evolution of 360/370/390/ zSeries Computers Chapter 12 12-29 The CPU  Architecture is compatible for every model of the zSeries  24-bit, 31-bit, and 64-bit addressing  16 address space registers permits access to one of fifteen 16EByte spaces  Present and previous Program Status Word (PSW) formats are supported  64-bit partitioned, segmented, and paged virtual storage and cache memory Chapter 12 12-30 zSeries Specifications Chapter 12 12-31 S/390 Registers          16 64-bit general purpose registers 16 64-bit floating point registers 16 special 64-bit control registers 16 access registers Time-of-day clock register Timer register Clock comparator register Prefix register 128-bit Program Status Word (PSW) Chapter 12 12-32 zSeries User Registers Chapter 12 12-33 Instruction Set  All zSystem instructions are 16 bits, 32 bits, or 64 bits in length  General instructions     Data transfer Integer arithmetic and logical operations Branches Shifts  Decimal Instructions  Floating point instructions  Control instructions Chapter 12 12-34 Addressing Modes  Immediate  Register  Storage  Also known as base offset addressing  Storage Indexed  Similar to storage addressing with the addition of an index value Chapter 12 12-35 Address Translation Mechanisms Chapter 12 12-36 Real-to-Absolute Translation Chapter 12 12-37 Advanced Features  Many features can be enabled or disabled with simple control register instructions  Clock synchronization between systems  Cluster support with data integrity control and workload balancing  Built-in diagnostics that can shift work from one CPU to another  Multiple forms of hardware system protection  System Protection Features  Supervisory state  Problem state  Storage access protection is provided at the address space, segment, and page levels  Integrated cryptographic facility  Firewall protection Chapter 12 12-38 CPU Organization  S/360 and S/370  Traditional control unit – arithmetic/logic unit model  More current processors  Modern CPU design with multiple fetch and execution units Chapter 12 12-39 S/390 System Block Diagram Chapter 12 12-40 ... architecture that can be interfaced with standard buses of other personal computers  Permits system components, bus adapters, and devices developed for other computers to be used with the PowerPC processor... decoder creates an intermediate set of micro-operations, μops  μops translate variable length and complex instructions into a 3-operand fixed length format Chapter 12 12-14 IA-64 Itanium Architecture. .. registers and control register Chapter 12 12-6 General Purpose Registers Chapter 12 12-7 Instruction Set and Format Data transfer Integer arithmetic Branch Bit manipulation, rotate and shift