;****************************************************************************** ; MSP430G2x21/G2x31 Demo - I2C Master Receiver, single byte ; ; Description: I2C Master communicates with I2C Slave using ; the USI Slave data should increment from 0x00 with each transmitted byte ; which is verified by the Master ; LED off for address or data Ack; LED on for address or data NAck ; ACLK = n/a, MCLK = SMCLK = Calibrated 1MHz ; ; ***THIS IS THE MASTER CODE*** ; ; Slave Master ; (msp430g2x21_usi_09.asm) ; MSP430G2x21/G2x31 MSP430G2x21/G2x31 ; ; /|\| XIN|/|\| XIN|; | | | | | | ; |RST XOUT| |RST XOUT|; | | | | ; LED LED ; | SDA/P1.7| ->|P1.7/SDA | ; | SCL/P1.6|< -|P1.6/SCL | ; ; Note: internal pull-ups are used in this example for SDA & SCL ; ; D Dang ; Texas Instruments Inc ; October 2010 ; Built with Code Composer Essentials Version: 4.2.0 ;****************************************************************************** I2CState equ R4 slav_data equ R5 slav_add equ R6 cdecls C,LIST, "msp430g2221.h" ; -.text ; Program Start ; -RESET mov.w #0280h,SP ; Initialize stackpointer StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop watchdog timer CheckCal cmp.b #0FFh,&CALBC1_1MHZ ; Calibration constants erased? jeq Trap cmp.b #0FFh,&CALDCO_1MHZ jne Load Trap jmp $ ; Trap CPU!! Load mov.b &CALBC1_1MHZ,&BCSCTL1 ; Set DCO to 1MHz mov.b &CALDCO_1MHZ,&DCOCTL SetupP1 mov.b #0xC0,&P1OUT ; P1.6&P1.7 Pullups bis.b #0xC0,&P1REN ; P1.6&P1.7 Pullups mov.b #0xFF,&P1DIR ; unused pins as output SetupP2 clr.b &P2OUT mov.b #0xFF,&P2DIR SetupUSI mov.b #USIPE6+USIPE7+USIMST+USISWRST,&USICTL0; Port, I2C master mov.b #USIIE+USII2C,&USICTL1 ; Enable I2C mov.b #USIDIV_3+USISSEL_2+USICKPL,&USICKCTL ; SMCLK/8 bis.b #USIIFGCC,&USICNT ; Disable automatic clear control bic.b #USISWRST,&USICTL0 ; Enable USI bic.b #USIIFG,&USICTL1 ; Clear pending flag clr.w I2CState clr.b slav_data mov.b #0x91,slav_add Mainloop bis.b #USIIFG,&USICTL1 bis.w #LPM0+GIE,SR ; Enter LPM0, enable interrupts call #Delay jmp Mainloop ; -USI_ISR ; ; -add.w I2CState,PC ; I2C State Machine jmp STATE0 jmp STATE2 jmp STATE4 jmp STATE6 jmp STATE8 jmp STATE10 STATE0 bis.b #0x01,&P1OUT ; LED on: sequence start clr.b &USISRL ; Generate start condition bis.b #USIGE+USIOE,&USICTL0 ; bic.b #USIGE,&USICTL0 ; & send address to slave mov.b slav_add,&USISRL ; and transmit address R/W =1 mov.b &USICNT,R8 ; Bit counter = 8, Tx adress and.b #0xE0,R8 add.b #0x08,R8 mov.b R8,&USICNT mov.w #2,I2CState ; Go to next state rx address (N)ACK bic.b #USIIFG,&USICTL1 ; clear pending flag reti STATE2 ; Rx address (N)Ack bit STATE4 Data_Rx STATE6 Data_NACK bic.b bis.b mov.w bic.b reti #USIOE,&USICTL0 #0x01,&USICNT #4,I2CState #USIIFG,&USICTL1 bit.b jnc bis.b clr.b bis.b mov.w bis.b bic.b reti #0x01,&USISRL Data_Rx #USIOE,&USICTL0 &USISRL #0x01,&USICNT #10,I2CState #0x01,&P1OUT #USIIFG,&USICTL1 bis.b mov.w bic.b bic.b reti #8,&USICNT #6,I2CState #0x1,&P1OUT #USIIFG,&USICTL1 bis.b cmp.b jnz clr.b inc.b bic.b jmp #USIOE,&USICTL0 slav_data,&USISRL Data_NACK &USISRL slav_data #0x01,&P1OUT STATE6_Exit mov.b bis.b #0xFF,&USISRL #0x1,&P1OUT ; SDA = input ; Bit counter = 1, rx (N)ACK ; Go to next state, chk (N)ACK ; Process Address (N)ack, data Rx ; if NACK received ; ; ; bit counter = 1, SCL high,SDA low ; go to next state, generate stop ; Turn on LED : error ; bit counter = 8, Rx data ; next state: Test data, (N)ACK ; LED off ; ; ; ; ; ; ; Send Data (N)Ack bit SDA = output if data valid data invalid , goto NACK loop send ACK Increment slave data LED off ; Send NACK ; LED on:error STATE6_Exit STATE8 STATE10 bis.b mov.w bic.b reti #0x1,&USICNT #8,I2CState #USIIFG,&USICTL1 bis.b clr.b bis.b mov.w bic.b reti #USIOE,&USICTL0 &USISRL #0x01,&USICNT #10,I2CState #USIIFG,&USICTL1 mov.b bis.b bic.b clr.w bic.w bic.b reti #0xFF,&USISRL #USIGE,&USICTL0 #USIGE+USIOE,&USICTL0 I2CState #LPM0,0(SP) #USIIFG,&USICTL1 ; Bit counter = 1, send NACK bit ; go to next state, prep stop ; Pre stop condition ; SDA =output ; Bit counter = 1, SCL high,SDA low ; go to next state, generate stop ; ; ; ; ; USISRL=1 to release SDA Transparent latch enabled Latch/SDA output disabled Reset state machine for next Tx Exit active for next transfer ; -Delay ; -mov.w #0xFFFF,R7 ; Delay betn communication cycles DL1 dec.w R7 jnz DL1 ret ; ; Interrupt Vectors ; .sect ".reset" ; MSP430 RESET Vector short RESET ; sect ".int04" ; USI Vector short USI_ISR ; end