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Explanation of component process Stepper and Scanner, Device Isolation, Dry Etching, Plasma ashing, Ion Implantation, Annealing, Ohmic contact, Barrier metal, and CMP 9.. Basic Steps of

Contents of Wafer Process

Contents of Wafer Process -continued

8 Explanation of component process

(Stepper and Scanner), Device Isolation, Dry Etching, Plasma ashing, Ion Implantation, Annealing, Ohmic contact, Barrier metal,

and CMP)

9 Modern CMOS Process

10 Reference

What is a Semiconductor? Semiconductor

A semiconductor is a material that behaves in

between a conductor and an insulator

At room temperature, it conducts electricity moreEasily than an insulator, but less readily than

a conductor

At very low temperatures, pure or intrinsic

semiconductors behave like insulators At highertemperatures though or under light, intrinsic

semiconductors can become conductive

The addition of impurities to a pure semiconductorcan also increase its conductivity

What is a Semiconductor? Semiconductor

Why Silicon is a most popular Semiconductor?

Silicon exists everywhere

High quality Oxide can be made on Silicon

Raw material Æ Metal Silicon Æ Poly Crystal siliconÆSingle Crystal Silicon(Eleven Nine:99.999999999%)Crystal pulling method : Czochralski (CZ) method,

Crystal structure of Silicon

Silicon belongs to the cubic crystal system and has a

This is characterized by having each atom symmetrically

surrounded by four equally spaced

neighbors

Crystal planes

Periodic Table

5 B

6 C

7 N 13

Al

14 Si

15 P 31

Ga

32 Ge

33 As

-

-N type and P type Silicon

Silicon crystal is rarely used in the pure state

Usually, some impurity called a dopant is added in

small controlled amount

If a boron atom is substituted for a silicon atom in thesilicon lattice, the boron atom with only three of

available electrons would be able to form bonds to

only three of the four adjacent silicon atom and

a hole would be formed

N type and P type Silicon - Continued

-Si 14+

-

-

-Si 14+

-

-

-B 5+

-

-Si 14+

-

-

-Si 14+

-

- -

-It is very easy for an electron from a nearby silicon

to silicon bond to fall into

this hole and effectively move the hole away from the boron atom

Since the boron atom will accept an electron, boron and the other elements of

Silicon with acceptor is called as P type silicon,

since “Positive” holes are

generated and contribute a current flow

If a Group V atom, such as phosphorus, is introducedinto the silicon lattice, it will have an extra electronwhich may easily break away, becoming a conductionelectron.

an electron to the conduction band Other donors are

As and Sb

Silicon with donor is called as N type silicon, since

“Negative” electrons are generated and contribute

the current flow

-Si 14+

-

-

-

-Properties of Silicon and Silicon Oxide

Why Silicon wafer is round?

Crystal Growth Technology

FZ

method

Polycrystal rod

Heat Coil Seed crystal

Melting

Seeding

Single-crystal silicon

What is MOS?

M(Metal)-O(Oxide)-S(Semiconductor)

MetalOxideSemiconductorMOS Structure

Basic structure of MOS Transistor

Electrode: Highly doped Poly-Silicon

Source and Drain: Highly doped N+ Diffusion

Gate Oxide: Silicon Oxide

Electrode

p-Type SubstrateGate Oxide

Gate

DrainSource

N+

N channel

MOS Transistor

Circuit symbolN+

Basic Steps of LSI wafer process

A) Thin Film formation:

Oxidation: Thermal OxidationCVD(Chemical Vapor Deposition): Deposition of Poly-Silicon, Silicon Nitride, Silicon Oxide

Evaporation, Sputtering: Aluminum, Metal, Silicide (Alloy of Silicon and other metal)Plating: Cu

Basic Steps of LSI wafer process - ContinuedC) Introduction of impurity

Diffusion:Diffusion of Solid or vapor phase

Ion Implantation:Ionized impurity bombardment using electric field

D) Cleaning: Wafer cleaning using acid or ultra pure water

These four steps are repeated during wafer process

Used to form the thick oxide

Since the diffusion coefficient of

shorter time

considered to be a distinct phase of matter in

contrast to solids, liquids, and gases because of its unique properties

“Ionized" means that at least one electron has been dissociated from a proportion of the atoms or

molecules

The free electron charges make the plasma

electrically conductive so that it responds strongly

to electromagnetic fields

Typical PECVD (Plasma Enhanced CVD)

Electrode

Silicon waferHeater

Principle of CVD

The material gas is transferred to wafer surface

where the reaction occurs and the reaction productdeposits on wafer

Energy(heat, plasma, light, etc)

Material gas Silicon wafer thin film and

Sputtering is a physical process whereby atoms

in a solid target material are ejected into the gas phase due to bombardment of the material by

energetic ions It is commonly used for thin-film deposition

Silicon wafer

TargetRF

Generator

What is Lithography Technology?

This is a technology where semiconductor circuit

patterns formed on photo-mask(mask) are repeatedly built on a wafer with high accuracy

Film Forming

Resist coating

Expose Develop

Etching or ion implantation Resist removal Next process

Wafer process flow chart

Si wafer

Film forming process Resist Coating Expose mask pattern

Resist pattern formation

Etching Resist removal (Developing)

Photo-mask

CMP (Planarization)

Film

There are two types of photoresist, one is

“positive (posi)” resist and the other is “negative (nega)” resist

When posi resist is exposed and developed,

the resist of exposed portion is dissolved and

when nega resist is exposed and developed,

the exposed portion remains

We use posi resist for fine patterning

a short wave length.

So a light of longer wave length is used in the clean room

Photolithography Machine Formation

For example refer to Cannon KrF sstepper FPA-3000EX6 illumination system

<Parameter related to exposure>

Light source : Exposure wavelength Illumination : σ, Variable illumination

Mask : Phase shift mask,

magnification Reduction projection lens: NA, aberration Wafer stage: X,Y, Z position, Positioning

Laser overdraw

Types of Photolithography Machines

- Stepper and Scanner

Stepper The target area for exposure (shot) is illuminated thoroughly and

exposed entirely.

Mask

Wafer

The area exposed to light

Scanner The target area for exposure (shot) is illuminated partially in the form of a slit, and exposed by synchronously scanning the reticule and the wafer stage.

Schematic diagram of an RF-powered

plasma etch system

Silicon wafer

Dry Etching

Table 1 Main processed film

Film to be etched Photoresist

Deposition

Photo-lithography

Removal of photoresist

Etching

Insulation film SiO2, Si3N4, Low-k material

Wiring material AlCu, W, WSi2, CoSi, TiN, Poly-Si, Pt, Ru

High dielectric material Ta2O5, BST

Antireflection film Organic ARC, Inorganic ARC (p-SiON, etc.) ARC:Anti-Reflection Coating

BST:(Ba,Sr)TiO

BST:(Ba,Sr)TiO 3

Dry Etching - Continued

P.R Poly-Si

CD shift: LResist - LEtch

Poly-Si Poly-Si Poly-Si

Reaction during Dry Etching

Generation of etching seeds

Detachment

of adsorbent carbon

Plasma

Formation of reaction products

Detachment of reaction products

Plasma ashing

the process of removing the photo-resist from

The reactive species combines with the photo-resist

to form ash which is removed with a vacuum pump.Typically, monatomic (single atom) oxygen plasma

is created by exposing

oxygen gas (O2) to ionizing radiation

At the same time, many free radicals

are formed which could damage the wafer

Plasma ashing - Continued

Newer, smaller circuitry is increasingly susceptible

to these particles

Originally, plasma was generated in the process

chamber, but as the need to get rid of free radicals has increased, many machines now use

a downstream Plasma configuration, where plasma

is formed remotely and channeled to the wafer

This allows electrically charged particles time to recombine before they reach the wafer surface,

and prevents damage to the wafer surface

Ion Implantation

Ion implantation is used to alter the surface

properties of semiconductor materials

By doping the desired elements on the semiconductor substrate, or in the thin film on the substrate, PN

junction is formed or surface properties are controlled

by thermal treatment, recovery of dislocated crystal or implanted impurity atoms are substituted at the lattice point and activated electrically (referred to as Anneal).(Usage)

etc

(Requirement from device)

Features of Ion Implantation

implantation depth

a selective implantation (Room temperature process)

Conventional impurity doping technology

such as thermal diffusion has replaced the

thermal diffusion with ion implantation

Implantation for Vth control

If the acceptor ion is implanted to NMOS, then Vth

Purpose of Annealing

Annealing is done for the purpose of

1 Damage relaxation from the bombardment of impurity

2 Activation of doped impurity

3 Diffusion of doped impurity

Alignment model of Si atom Process flow

Before implantation

After implantation

After annealing

In this case, implanted ions are not bonded to Si atoms, but

is in between Si atoms

(Interstitial atom)

In this condition, a current does not flow even though dopant ion exists (Inactive condition)

By annealing, the alignment

of Si atoms is recovered, and ions also get bond to Si Therefore a current can flow (Ion activation)

Ohmic contact and barrier metal

Ohmic Contact

An ohmic contact refers to the contact between

a metal and a semiconductor to allow carriers to

flow in and out of the semiconductor

An ideal ohmic contact must have no effect on

device performance, i.e., it must be capable of

delivering the required current with no voltage drop between the semiconductor and the metal

In real life, therefore, an ohmic contact must have

a contact resistance that is as small as possible, to make it negligible in comparison to the bulk or

spreading resistance of the semiconductor

Materials which form ohmic contact to Silicon

Sem iconductor

Contact Material T echnique(s)

Barrier Metal

A barrier metal is a material used in integrated

circuits to chemically isolate semiconductors

from soft metal interconnects, while maintaining

an electrical connection between them

For instance, a layer of barrier metal must surround every copper interconnection in modern copper-

based chips, to prevent diffusion of copper into

surrounding materials

As the name implies, a barrier metal must have

high electrical conductivity in order to maintain

a good electronic contact, while maintaining a low enough copper diffusivity to chemically isolate

the copper conductor from the silicon below

CMP - Chemical-Mechanical Polishing

Slurry

Polishing Table

Polishing PadWafer (facing down)

Wafer carrier

Silicon

Oxide Polishing pad Slurry

Close-up of wafer/pad interface

Modern CMOS Technology

Followings are the typical CMOS wafer process

Device Isolation - Comparison of LOCOS and STI

Comparison of below figures illustrates both similarities and

the differences in LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation) Both process produce thick SiO2 regions laterally

isolating adjacent device structure

However, STI produces more compact structures because there is very little lateral encroachment of the isolation structure into adjacent active regions STI is used below 0.35um process.

LOCOS

STI

Thermally oxidized SiO2

CVD deposited SiO2

Active Region Formation

Active Region means the region where

active devices such as NMOS and PMOS

transistors are formed.

Following slides show the wafer process

using LOCOS device isolation.

STI process is explained as an option process.

Following initial cleaning, an SiO2 layer is thermally grown on the silicon substrate

A Si3N4 layer then deposited by LPCVD

Photoresist is spun on the wafer to prepare for the first masking operation.

Photoresist

Si, (100), P Type, 5~50 ohm-cm

Si3N4 (80nm) SiO2 (40nm)

LPCVD: Low Pressure CVD

Mask 1 patterns the photoresist.

Photo-mask(Reticule)

Photoresist (Posi Posi type)

Si, (100), P Type, 5~50 ohm-cm

Si3N4 (80nm) SiO2 (40nm)

The Si3N4 layer is removed where it is not protected by the photoresist by dry etching.

After photoresist stripping, the field oxide is grown in an oxidizing ambient (1000 C 90

The oxidation extends under the nitride edge

sideways.

Field region: Isolation regions between Active regions.

Process option for Device Isolation

Shallow Trench Isolation

-After Mask 1 defines the photoresist, the Si3N4, SiO2 and Si trenches are

successively plasma etched to create the shallow trenches for isolation.

A thin “liner” oxide is thermally grown in the trenches The nitride prevents any additional oxidation on the top surface of the wafer.

SiO2 is deposited to completely fill

the trenches This would typically requires

on the trench depth and geometry.

The deposited SiO2 layer is polished back using CMP to produce a planar structure.

N and P WELL Formation

Photoresist is used to mask the regions

where PMOS devices will be built using

for the P wells for the NMOS devices.

Boron

P Type Implant

Photoresist is used to mask the regions

where NMOS devices will be built using

doping for the N wells for the PMOS devices.

Phosphorus

P Type Implant

N Type Implant

A high temperature drive-in (1000~1100 C

and 4 to 6 hours) completes the formation of the N and P wells Well depth will be 2 to 3

um after the wafer process finishes.

Gate Formation

Before forming Gate oxide, channel implant

( Vth controlled implant) is done

implant dose

This equation assumes that the entire implant dose

is located in the near surface region,

inside the MOS channel depletion region

After spinning photoresist on the wafer, Mask 4 is used to define the NMOS

transistors A boron implant adjusts the N-channel Vth.

Boron

P

After spinning photoresist on the wafer, Mask 5 is used to define the PMOS

transistors A arsenic implant adjusts the P-channel Vth.

Arsenic

P N

After etching back the thin oxide to bare

silicon, the gate oxide (~10nm) is grown for the MOS transistors.

P N

A layer of polysilicon (0.3~0.5um) is

deposited

Ion implantation of phosphorus follows

the deposition to heavily dope the poly

This can produce low-sheet-resistance poly layers.

P N

Photoresist is applied and Mask 6 is used to define the regions where MOS gates are

located The polysilicon layer is then etched using plasma etching.

P N

LDD (Lightly Doped Drain)

Formation

Decreasing the channel length in the device

to 0.5um without reducing the supply voltage increases the average field to about 10 Vcm Vcm .

This high field is large enough to cause

a problems in semiconductor devices.

Such problems are often called “hot electron” problems.

Carriers at high energies can cause impact

ionization which creates additional

hole-electron pairs.

LDD structure is applied to relax the field.

Mask 7 is used to cover the PMOS devices

A phosphorus implant is used to form the

LDD (extension) region in the NMOS devices.

P N

Phosphorus

N- - Implant

Mask 8 is used to cover the NMOS devices

A boron implant is used to form the LDD

(extension) region in the PMOS devices.

P N

Boron

N- - Implant P- - Implant

A conformal layer of SiO2 is deposited on the wafer in preparation for side-wall spacer

formation.

P N

N- - Implant P- - Implant