Introduction to output compare

OUTPUT COMPARE MODULE The output compare module has the task of comparing the value of the time base counter with the value of one or two compare registers depending on the Operation mode selected It is able to generate a single output pulse or a sequence of output pulses when the compared values match; also, it has the ability to generate interrupts on compare match events Ex: The dsPIC30F4013 controller has output compare modules whereas controller dsPIC6014A has Each output compare channel can select which of the time base counters, TMR2 or TMR3, will be compared with the compare registers The counter is selected by using control bit OCTSEL (OCxCON) The output compare module has several modes of operation selectable by using control bits OCM (OCXCON): • Single compare match mode • Dual compare match mode generating either one output pulse or a sequence of output pulses, • Pulse Width Modulation (PWM) mode Fig Functional diagram of output compare module SINGLE COMPARE MATCH MODE When control bits OCM are set to 001, 010, or 011, the ouput compare module is set to the Single compare match mode Now, the value loaded in the compare register OCxR is compared with time base counter TMR2 or TMR3 On a compare match event, depending on the value of OCM, at the OCx output pin one of the following situations is possible: • OCx pin is high, initial state is low, and interrupt is generated, • OCx pin is low, initial state is high, and interrupt is generated, • State of OCx pin toggles and interrupt is generated • SINGLE COMPARE MATCH, PIN OCX DRIVEN HIGH In order to configure the output compare module for this mode, control bits OCM are set to 001 Also, the time base counter (TMR2 or TMR3) should be selected Initially, output pin OCx is set low and will stay low until a match event occurs between the TMRy and OCxR registers One instruction clock after the compare match event, OCx pin is driven high and will remain high until a change of the mode or the module is disabled TMRy goes on counting Twop instruction clocks after OCx pin is driven high, the interrupt, OCxIF flag, is generated Timing diagram of the single compare mode, set OCx high on compare match event is shown in Fig Fig Timing diagram of the single compare mode, set OCx high on compare match event • Single compare match, pin OCx driven low In order to configure the output compare module for this mode, control bits OCM are set to 010 Also, the time base counter (TMR2 or TMR3) should be enabled Initially, output pin OCx is set high and it stays high until a match event occurs between the TMRy and OCxR registers One instruction clock after the compare match event OCx pin is driven low and will remain low until a change of the mode or the module is disabled TMRy goes on counting Two instruction clocks after OCx pin is driven low, the interrupt flag, OCxIF, is generated Timing diagram of the single compare mode, set OCx low on compare match event is shown in Fig Fig Timing diagram of the single compare mode,set OCx low on compare match event • SINGLE COMPARE MATCH, PIN OCX TOGGLES In order to configure the output compare module for this mode, control bits OCM areset to 011 Also, the time base counter (TMR2 or TMR3) should be enabled Initially, output pin OCx is set low and then toggles on each subsequent match event between the TMRy and OCxR registers registers isters OCX pin is toggled one instruction clock the compare match event TMRy goes on counting Two instruction clocksafter the OCX pin is toggled, the interrupt flag, OCxF, is generated Figs and show the timing diagrams of the single compare mode, toggle output on compare match event when timer register PRy (PR2 or PR3)>OCxR (Fig 4) or timer register PRy (PR2 or PR3)=OCxR (Fig 5) Fig Timing diagrams of the single compare mode, toggle output on compare match event when timer register PRy>OCxR Fig Timing diagrams of the single compare mode, toggle output on compare match event when timer register PRy=OCxR In the interrupt routine the request for the flag Output compare interrupt module is reset At setting time base 2, preset register PR2 is set to the maximum value in orde to enable the freerunning mode over the whole range, 0-65335 The value of OC1R defines the time of the change of state of pin OC1, i.e of the duty cycle The output compare module is configured to change the state of pin OC1 on single compare match with the value of OC1R DUAL COMPARE MATCH MODE When control bits OCM are set to 100 or 101, the output compare module is configured for the dual compare match mode In this mode the module uses two registers, OCxR and OCxRS, for the compare match events The values of both registers are compared with the time base counter TMR2 or TMR3 On a compare match event of the OCxR register and register TMR2 or TMR3 (selectable by control bit OCTSEL), the leading edge of the pulse is generated at the OCx pin; the register OCxRS is then compared with the same time base register and on a compare match event, the trailing edge at the OCx pin is generated Depending on the value of control bit OCM at the output pin OCx is generated: - Single pulse and an interrupt request, - A sequence of pulses and an interrupt request • DUAL COMPARE MATCH MODE, SINGLE OUTPUT PULSE AT PIN OCX When control bits OCM are set to 100, the output compare module is configured for the dual compare match (OCxR and OCxRS registers), single output pulse mode By setting the control bits OCTSEL the time base counter for comparison is selected v Two instruction clocks after pin OCx is driven low, an interrupt request OCxIF for the output compare module is generated Pin OCx will remain low until a mode change has been made or the module is disabled If the contents of time base register PRy