512Mb: x4, x8, x16 SDRAM Features Synchronous DRAM MT48LC128M4A2 – 32 Meg x x banks MT48LC64M8A2 – 16 Meg x x banks MT48LC32M16A2 – Meg x 16 x banks For the latest data sheet, refer to Micron’s Web site Features Options • PC100- and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto precharge, includes concurrent auto precharge, and auto refresh modes • Self refresh mode • 64ms, 8,192-cycle refresh • LVTTL-compatible inputs and outputs • Single +3.3V ±0.3V power supply Table 1: Address Table Parameter 32 Meg x 32 Meg x 32 Meg x 16 32 Meg x 16 Meg x x banks x banks 8K 8K Refresh count 8K (A0–A12) 8K (A0–A12) Row addressing (BA0, BA1) (BA0, BA1) Bank addressing 4K (A0–A9, 2K (A0–A9, Column A11, A12) A11) addressing Configuration Table 2: Speed Grade -7E -75 -7E -75 • Configurations – 128 Meg x (32 Meg x x banks) – 64 Meg x (16 Meg x x banks) – 32 Meg x 16 (8 Meg x 16 x banks) • WRITE recovery (tWR) – tWR = “2 CLK”1 • Plastic package – OCPL2 – 54-pin TSOP II (400 mil) – 54-pin TSOP II (400 mil) Pb-free • Timing (cycle time) – 7.5ns @ CL = (PC133) – 7.5ns@ CL = (PC133) • Self refresh – Standard – Low power • Operating temperature range – Commercial (0oC to +70oC) – Industrial (–40oC +85oC) • Revision Meg x 16 x banks 8K 8K (A0–A12) (BA0, BA1) Notes: 1K (A0–A9) Key Timing Parameters Access Time Clock Frequency CL = CL = 143 MHz 133 MHz 133 MHz 100 MHz – – 5.4ns 6ns Setup Time Hold Time 1.5ns 1.5ns 1.5ns 1.5ns 0.8ns 0.8ns 0.8ns 0.8ns 5.4ns 5.4ns – – Marking 128M4 64M8 32M16 A2 TG P -7E4 -75 None L3 None IT :C Refer to Micron technical note: TN-48-05 Off-center parting line Contact factory for availability Available on x4 and x8 only Part Number Example: MT48LC32M16A2P-75:C PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAMfront.fm - Rev L 10/07 EN Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved Products and specifications discussed herein are subject to change by Micron without notice 512Mb: x4, x8, x16 SDRAM Table of Contents Table of Contents Features Options General Description Functional Description 11 Initialization 11 Register Definition 13 Mode Register 13 Burst Length (BL) 13 Burst Type 13 CAS Latency (CL) 15 Operating Mode 16 WRITE Burst Mode .16 Commands 17 COMMAND INHIBIT .17 NO OPERATION (NOP) .17 LOAD MODE REGISTER 18 ACTIVE 18 READ 18 WRITE 18 PRECHARGE 18 Auto Precharge 19 BURST TERMINATE 19 AUTO REFRESH 19 SELF REFRESH 19 Operations 20 Bank/Row Activation .20 READs 21 WRITEs 28 PRECHARGE 32 Power-Down 33 Clock Suspend .33 Burst READ/Single WRITE 34 Concurrent Auto Precharge 35 Electrical Specifications .42 Temperature and Thermal Impedance 42 Notes 47 Timing Diagrams .49 Package Dimensions 68 PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAMTOC.fm - Rev L 10/07 EN Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: 128 Meg x SDRAM Functional Block Diagram 64 Meg x SDRAM Functional Block Diagram 32 Meg x 16 SDRAM Functional Block Diagram Pin Assignment (Top View) 54-Pin TSOP Mode Register Definition 14 CAS Latency 16 Activating a Specific Row In a Specific Bank .20 Example Meeting tRCD (MIN) when < tRCD (MIN)/tCK ≤ 21 READ Command .21 CAS Latency 22 Consecutive READ Bursts 23 Random READ Accesses 24 READ-to-WRITE 25 READ-to-WRITE with Extra Clock Cycle 25 READ-to-PRECHARGE 26 Terminating a READ Burst 27 WRITE Command .28 WRITE Burst .29 WRITE-to-WRITE 29 Random WRITE Cycles 30 WRITE-to-READ 30 WRITE-to-PRECHARGE 31 Terminating a WRITE Burst 32 PRECHARGE Command 32 Power-Down 33 CLOCK SUSPEND During WRITE Burst 34 CLOCK SUSPEND During READ Burst 34 READ with Auto Precharge Interrupted by a READ 35 READ with Auto Precharge Interrupted by a WRITE 36 WRITE with Auto Precharge Interrupted by a READ 36 WRITE with Auto Precharge Interrupted by a WRITE 37 Example Temperature Test Point Location, 54-Pin TSOP: Top View 43 Initialize and Load Mode Register 49 Power-Down Mode 50 Clock Suspend Mode 51 Auto-Refresh Mode 52 Self Refresh Mode 53 READ – Without Auto Precharge 54 READ – With Auto Precharge 55 Single READ – With Auto Precharge 57 Alternating Bank Read Accesses 58 READ – Full-Page Burst 59 READ DQM Operation .60 WRITE – Without Auto Precharge 61 WRITE – With Auto Precharge 62 Single WRITE – Without Auto Precharge 63 Single WRITE with Auto Precharge 64 Alternating Bank WRITE Accesses 65 WRITE – Full-Page Burst 66 WRITE – DQM Operation 67 54-Pin Plastic TSOP (400 mil) .68 PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAMLOF.fm - Rev L 10/07 EN Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Address Table Key Timing Parameters Pin Descriptions 10 Burst Definition .15 CAS Latency 16 Truth Table – Commands and DQM Operation 17 Truth Table – CKE 37 Truth Table – Current State Bank n, Command to Bank n 38 Truth Table – Current State Bank n, Command to Bank m 40 Absolute Maximum Ratings 42 Temperature Limits 43 Summary of Thermal Impedance 43 DC Electrical Characteristics And Operating Conditions 44 IDD Specifications and Conditions 44 Capacitance 44 Electrical Characteristics and Recommended AC Operating Conditions 45 PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAMLOT.fm - Rev L 10/07 EN Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM General Description General Description The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK) Each of the x4’s 134,217,728-bit banks is organized as 8,192 rows by 4,096 columns by bits Each of the x8’s 134,217,728-bit banks is organized as 8,192 rows by 2,048 columns by bits Each of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns by 16 bits Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0–A12 select the row) The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access The SDRAM provides for programmable READ or WRITE burst lengths (BL) of 1, 2, 4, or locations, or the full page, with a burst terminate option An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation The 512Mb SDRAM is designed to operate at 3.3V An auto refresh mode is provided, along with a power-saving, power-down mode All inputs and outputs are LVTTLcompatible SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM General Description Figure 1: 128 Meg x SDRAM Functional Block Diagram CKE CLK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTER REFRESH 13 COUNTER 12 ROWADDRESS MUX 13 13 BANK0 ROWADDRESS LATCH & DECODER 8192 BANK0 MEMORY ARRAY (8,192 x 4,096 x 4) DQM SENSE AMPLIFIERS 16384 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS A0–A12, BA0, BA1 15 ADDRESS REGISTER BANK CONTROL LOGIC DATA OUTPUT REGISTER 4 4096 (x4) DQ0– DQ3 DATA INPUT REGISTER COLUMN DECODER 12 PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN COLUMNADDRESS COUNTER/ LATCH 12 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM General Description Figure 2: 64 Meg x SDRAM Functional Block Diagram CKE CLK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTER REFRESH 13 COUNTER 12 ROWADDRESS MUX 13 13 BANK0 ROWADDRESS LATCH & DECODER 8192 BANK0 MEMORY ARRAY (8,192 x 2,048 x 8) DQM SENSE AMPLIFIERS 16384 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS A0–A12, BA0, BA1 15 ADDRESS REGISTER BANK CONTROL LOGIC DATA OUTPUT REGISTER 8 2048 (x8) DQ0– DQ7 DATA INPUT REGISTER COLUMN DECODER 11 PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN COLUMNADDRESS COUNTER/ LATCH 11 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM General Description Figure 3: 32 Meg x 16 SDRAM Functional Block Diagram CKE CLK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTER REFRESH 13 COUNTER 12 ROWADDRESS MUX 13 13 BANK0 ROWADDRESS LATCH & DECODER 8192 BANK0 MEMORY ARRAY (8,192 x 1,024 x 16) DQML, DQMH SENSE AMPLIFIERS 16 16384 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS A0–A12, BA0, BA1 15 ADDRESS REGISTER BANK CONTROL LOGIC DATA OUTPUT REGISTER 16 16 1024 (x16) DQ0– DQ15 DATA INPUT REGISTER COLUMN DECODER 10 PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN COLUMNADDRESS COUNTER/ LATCH 10 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM General Description Figure 4: Pin Assignment (Top View) 54-Pin TSOP x4 x8 x16 - - NC DQ0 - - NC NC DQ0 DQ1 - - NC NC NC DQ2 - - NC NC DQ1 DQ3 Note: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN - - NC NC - - NC NC - - VDD DQ0 VDDQ DQ1 DQ2 VssQ DQ3 DQ4 VDDQ DQ5 DQ6 VssQ DQ7 VDD DQML WE# CAS# RAS# CS# BA0 BA1 A10 A0 A1 A2 A3 VDD x16 x8 x4 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Vss DQ15 DQ7 VssQ DQ14 NC DQ13 DQ6 VDDQ DQ12 NC DQ11 DQ5 VssQ DQ10 NC DQ9 DQ4 VDDQ DQ8 NC Vss NC DQMH DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss - NC NC DQ3 NC NC NC DQ2 NC DQM - The # symbol indicates signal is active LOW A dash (-) indicates x8 and x4 pin function is same as x16 pin function Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM General Description Table 3: Pin Descriptions Pin Numbers Symbols Type Description 38 CLK Input 37 CKE Input 19 CS# Input 18, 17, 16 RAS#, CAS#, WE# x4, x8: DQM x16: DQML, DQMH Input Clock: CLK is driven by the system clock All SDRAM input signals are sampled on the positive edge of CLK CLK also increments the internal burst counter and controls the output registers Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal Deactivating the clock provides PRECHARGE power-down and SELF REFRESH operation (all banks idle), ACTIVE power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in progress) CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power CKE may be tied HIGH Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder All commands are masked when CS# is registered HIGH CS# provides for external bank selection on systems with multiple banks CS# is considered part of the command code Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered Input/output mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses Input data is masked when DQM is sampled HIGH during a WRITE cycle The output buffers are placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle On the x4 and x8, DQML (Pin 15) is a NC and DQMH is DQM On the x16, DQML corresponds to DQ0–DQ7, and DQMH corresponds to DQ8–DQ15 DQML and DQMH are considered same state when referenced as DQM Bank address inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied Address inputs: A0–A12 are sampled during the ACTIVE command (row-address A0–A12) and READ/WRITE command (column-address A0–A9, A11, A12 [x4]; A0– A9, A11 [x8]; A0–A9 [x16]; with A10 defining auto precharge) to select one location out of the memory array in the respective bank A10 is sampled during a PRECHARGE command to determine whether all banks are to be precharged (A10 [HIGH]) or bank selected by (A10 [LOW]) The address inputs also provide the opcode during a LOAD MODE REGISTER command Data input/output: Data bus for x16 (4, 7, 10, 13, 15, 42, 45, 48, and 51 are NCs for x8; 2, 4, 7, 8, 10, 13, 15, 42, 45, 47, 48, 51, and 53 are NCs for x4) 39 15, 39 Input 20, 21 BA0, BA1 Input 23–26, 29– 34, 22, 35, 36 A0–A12 Input 2, 4, 5, 7, 8, DQ0–DQ15 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 2, 5, 8, 11, DQ0–DQ7 44, 47, 50, 53 DQ0–DQ3 5, 11, 44, 50 40 NC 3, 9, 43, 49 VDDQ 6, 12, 46, VSSQ 52 1, 14, 27 VDD 28, 41, 54 VSS PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN x16: I/O x8: I/O Data input/output: Data bus for x8 (2, 8, 47, and 53 are NCs for x4) x4: I/O Data input/output: Data bus for x4 – Supply Supply No connect: This pin should be left unconnected DQ power: Isolated DQ power to the die for improved noise immunity DQ ground: Isolated DQ ground to the die for improved noise immunity Supply Supply Power supply: +3.3V ±0.3V Ground 10 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 38: READ – Without Auto Precharge T0 T1 tCK CLK T2 T3 T4 T5 NOP NOP T6 T7 T8 NOP ACTIVE tCL tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP READ tCMS NOP PRECHARGE tCMH DQM/ DQML, DQMU tAS A0–A9, A11, A12 tAS COLUMN m ROW tAH ALL BANKS ROW A10 tAS BA0, BA1 tAH ROW ROW SINGLE BANK DISABLE AUTO PRECHARGE tAH BANK BANK BANK tAC tOH tAC DQ DOUT m tAC tOH DOUT m + BANK tAC tOH tOH DOUT m + DOUT m + tLZ tRCD tHZ tRP CAS Latency tRAS tRC Don’t Care Undefined Notes: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” 54 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 39: READ – With Auto Precharge T0 T1 tCK CLK tCKS T2 T3 T4 T5 NOP NOP T6 T7 T8 NOP ACTIVE tCL tCH tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ tCMS NOP NOP tCMH DQM/ DQML, DQMU tAS A0–A9, A11, A12 tAS A10 COLUMN m tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW ROW tAH BANK BANK BANK tAC tOH tAC DOUT m DQ t tAC tOH DOUT m + tAC tOH DOUT m + tLZ tRCD tOH DOUT m + tHZ tRP CAS Latency tRAS tRC Don’t Care Undefined Notes: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN For this example, BL = 4, and CL = 2 x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” 55 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 40: Single READ – Without Auto Precharge T0 T1 tCK CLK T2 T3 T4 T5 NOP NOP T6 T7 T8 tCL tCH tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ PRECHARGE NOP ACTIVE NOP tCMS tCMH DQM/ DQML, DQMH tAS A0–A9, A11, A12 tAS COLUMN m2 ROW tAH ALL BANKS ROW A10 tAS BA0, BA1 tAH ROW ROW DISABLE AUTO PRECHARGE tAH BANK SINGLE BANKS BANK BANK(S) BANK tOH tAC DOUT m DQ tLZ tRCD tHZ tRP CAS Latency tRAS tRC Don’t Care Undefined Notes: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN For this example, BL = 1, CL = 2, and the READ burst is followed by a “manual” PRECHARGE x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” 56 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 41: Single READ – With Auto Precharge T0 T1 tCK CLK tCKS T2 T3 T4 T5 T6 T7 T8 tCL tCH tCKH CKE tCMS tCMH COMMAND ACTIVE NOP NOP3 NOP3 READ tCMS NOP NOP ACTIVE NOP tCMH DQM/ DQML, DQMH tAS A0–A9, A12 tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m2 ROW tAS A10 tAH ROW tAH BANK BANK BANK tAC t OH DOUT m DQ tRCD CAS Latency tHZ tRP tRAS tRC Don’t Care Undefined Notes: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN For this example, BL = 1, and CL = 2 x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” READ command is not allowed else tRAS would be violated 57 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 42: Alternating Bank Read Accesses T0 T1 tCK CLK T2 T3 T4 T5 NOP ACTIVE T6 T7 T8 READ NOP ACTIVE tCL tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP READ tCMS NOP tCMH DQM/ DQML, DQMU tAS A0–A9, A11, A12 tAS A10 COLUMN m tAH COLUMN b ROW ENABLE AUTO PRECHARGE ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW ROW ROW tAH BANK BANK BANK BANK tAC tOH tAC DOUT m DQ tAC tOH DOUT m + BANK tAC tOH DOUT m + tAC tOH DOUT m + tAC tOH DOUT b tLZ tRCD - BANK tRP - BANK CAS Latency - BANK tRCD - BANK tRAS - BANK tRC - BANK tRCD - BANK tRRD CAS Latency - BANK Don’t Care Undefined Notes: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN For this example, BL = 4, and CL = 2 x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” 58 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 43: READ – Full-Page Burst T0 T1 T2 tCL CLK T3 T4 T5 T6 (( )) (( )) tCK tCH tCKS tCMH ACTIVE NOP READ tCMS NOP NOP NOP NOP tCMH tAS tAH tAH NOP BURST TERM NOP NOP (( )) (( )) ROW tAS (( )) (( )) (( )) (( )) COLUMN m ROW tAS BA0, BA1 Tn + (( )) (( )) DQM/ DQML, DQMH A10 Tn + (( )) (( )) tCMS A0–A9, A11, A12 Tn + tCKH CKE COMMAND Tn + tAH BANK (( )) (( )) BANK tAC tAC tOH DOUT m DQ tLZ tRCD CAS Latency tAC tAC ( ( tOH ) ) tOH DOUT m+1 DOUT (( )) m+2 (( )) tAC tAC tOH tOH tOH DOUT m-1 Dout m DOUT m+1 1,024 (x16) locations within same row 2,048 (x8) locations within same row 4,096 (x4) locations within same row tHZ Full page completed Full-page burst does not self-terminate Can use BURST TERMINATE command Notes: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN Don’t Care Undefined For this example, CL = 2 x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” Page left open; no tRP 59 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 44: READ DQM Operation T0 T1 tCK CLK tCKS tCKH tCMS tCMH T2 T3 T4 T5 NOP NOP T6 T7 T8 NOP NOP tCL tCH CKE COMMAND ACTIVE NOP READ tCMS NOP NOP tCMH DQM/ DQML, DQMU tAS A0–A9, A11, A12 tAH ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m ROW tAS A10 tAH DISABLE AUTO PRECHARGE tAH BANK BANK tAC tOH DQ tAC DOUT m tLZ tRCD tHZ tAC tOH DOUT m + tLZ tOH DOUT m + tHZ CAS Latency Don’t Care Undefined Notes: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN For this example, BL = 4, and CL = 2 x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” 60 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 45: WRITE – Without Auto Precharge T0 tCK CLK T1 T2 tCL T3 T4 T5 T6 NOP NOP NOP NOP T7 T8 T9 tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE PRECHARGE NOP ACTIVE tCMS tCMH DQM/ DQML, DQMU tAS A0–A9, A11, A12 ROW tAH ALL BANKs ROW tAS BA0, BA1 COLUMN m ROW tAS A10 tAH ROW tAH DISABLE AUTO PRECHARGE SINGLE BANK BANK BANK BANK tDS tDH DIN m DQ tDS tDH DIN m + tDS tDH DIN m + tDS tDH DIN m + t WR tRCD tRAS BANK tRP tRC Don’t Care Notes: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE 14ns to 15ns is required between and the PRECHARGE command, regardless of frequency x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” 61 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 46: WRITE – With Auto Precharge T0 tCK CLK tCKS tCKH tCMS tCMH T1 T2 tCL T3 T4 T5 T6 T7 T8 T9 NOP NOP NOP NOP NOP NOP ACTIVE tCH CKE COMMAND ACTIVE NOP WRITE tCMS tCMH DQM/ DQML, DQMH tAS A0–A9, A11, A12 tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m ROW tAS A10 tAH ROW tAH BANK BANK tDS tDH DIN m DQ BANK tDS tDH DIN m + tDS tDH DIN m + tRCD tRAS tDS tDH DIN m + tWR tRP tRC Don’t Care Notes: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN For this example, BL = x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” 62 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 47: Single WRITE – Without Auto Precharge T0 tCK CLK T1 T2 tCL T3 T4 T5 T6 NOP NOP NOP NOP T7 T8 T9 tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE PRECHARGE NOP ACTIVE tCMS tCMH DQM/ DQML, DQMU tAS A0–A9, A11, A12 ROW tAH ALL BANKs ROW tAS BA0, BA1 COLUMN m ROW tAS A10 tAH ROW tAH DISABLE AUTO PRECHARGE SINGLE BANK BANK BANK BANK tDS tDH DIN m DQ tDS tDH DIN m + tDS tDH DIN m + tDS tDH DIN m + t WR tRCD tRAS BANK tRP tRC Don’t Care Notes: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE 14ns to 15ns is required between and the PRECHARGE command, regardless of frequency x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” PRECHARGE command not allowed else tRAS would be violated 63 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 48: Single WRITE with Auto Precharge T0 tCK CLK tCKS tCKH tCMS tCMH T1 tCL T2 T3 T4 T5 T6 T7 NOP4 WRITE NOP NOP NOP T8 T9 tCH CKE COMMAND NOP4 ACTIVE NOP4 tCMS ACTIVE NOP tCMH DQM/ DQML, DQMH tAS A0–A9, A11, A12 tAH ROW ENABLE AUTO PRECHARGE ROW ROW tAS BA0, BA1 COLUMN m3 ROW tAS A10 tAH tAH BANK BANK tDS BANK tDH DIN m DQ tRCD3 tRAS tWR2 tRP tRC Don’t Care Undefined Notes: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE 14ns to 15ns is required between and the PRECHARGE command, regardless of frequency x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” WRITE command not allowed else tRAS would be violated 64 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 49: Alternating Bank WRITE Accesses T0 tCK CLK T1 T2 tCL T3 T4 T5 T6 T7 T8 T9 NOP NOP ACTIVE tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE tCMS NOP ACTIVE NOP WRITE tCMH DQM/ DQML, DQMU tAS A0–A9, A11, A12 tAS A10 COLUMN m tAH COLUMN b ROW ENABLE AUTO PRECHARGE ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW ROW ROW tAH BANK BANK tDS tDH DIN m DQ BANK tDS tDH DIN m + tDS tDH DIN m + BANK tDS tDH DIN m + tDS tDH DIN b tWR - BANK tRCD - BANK BANK tDS tDH DIN b + tDS tDH DIN b + tDS tDH DIN b + tRP - BANK tRCD - BANK tRAS - BANK tRC - BANK tRCD - BANK tRRD tWR - BANK Don’t Care Notes: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN For this example, BL = Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” 65 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 50: WRITE – Full-Page Burst T0 T1 T2 tCL CLK T3 T4 T5 (( )) (( )) tCK tCH tCKS tCKH COMMAND tCMH ACTIVE NOP WRITE NOP NOP (( )) (( )) NOP tCMS tCMH tAS A10 NOP BURST TERM NOP (( )) (( )) COLUMN m1 tAH (( )) (( )) ROW tAS BA0, BA1 tAH ROW tAS Tn + (( )) (( )) DQM/ DQML, DQMH A0–A9, A11, A12 Tn + (( )) (( )) CKE tCMS Tn + tAH BANK (( )) (( )) BANK tDS tDH DIN m DQ tDS tDH DIN m + tRCD tDS tDH DIN m + tDS tDH DIN m + (( )) 3( ( )) tDS tDH DIN m - 1,024 (x16) locations within same row 2,048 (x8) locations within same row 4,096 (x4) locations within same row Full-page burst does not self-terminate Can use BURST TERMINATE command to stop.2, Full page completed Don’t Care Notes: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” must be satisfied prior to PRECHARGE command Page left open; no tRP tWR 66 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 51: WRITE – DQM Operation T0 T1 tCK CLK T2 T3 T4 T5 NOP NOP NOP T6 T7 NOP NOP tCL tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE tCMS tCMH DQM/ DQML, DQMU tAS A0–A9, A11, A12 tAH ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m ROW tAS A10 tAH tAH DISABLE AUTO PRECHARGE BANK BANK tDS tDH tDS DIN m DQ tDH DIN m + tDS tDH DIN m + tRCD DON’T CARE Notes: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN For this example, BL = x16: A11 and A12 = “Don’t Care;” x8: A12 = “Don’t Care.” 67 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Package Dimensions Package Dimensions Figure 52: 54-Pin Plastic TSOP (400 mil) 22.22 ±0.08 SEE DETAIL A 0.71 0.80 TYP 0.375 ±0.075 11.76 ±0.20 10.16 ±0.08 0.15 +0.03 –0.02 PIN #1 ID GAGE PLANE 0.25 0.10 0.10 +0.10 –0.05 1.2 MAX LEAD FINISH: TIN/LEAD PLATE PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC PACKAGE WIDTH AND LENGTH DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0.25 PER SIDE Notes: 0.50 ±0.10 0.80 TYP DETAIL A All dimensions in millimeters Package width and length not include mold protrusion; allowable mold protrusion is 0.25mm per side ® 8000 S Federal Way, P.O Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc All other trademarks are the property of their respective owners This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range set forth herein Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN 68 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved [...]... 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN 34 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Operations Concurrent Auto Precharge An access command to (READ or WRITE) another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM. .. 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN If desired, more than two AUTO REFRESH commands can be issued in the sequence After steps 9 and 10 are complete, repeat them until the desired number of AUTO REFRESH + tRFC loops is achieved 12 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM. .. starting column address, as shown in Table 4 on page 15 PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Register Definition Figure 5: Mode Register Definition A12 A11 A10 12 11 A9 9 10 Reserved1 A8 8... are met, if a READ command is registered at T0 and the PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Register Definition latency is programmed to two clocks, the DQs will start driving after T1 and... write accesses are single-location (nonburst) accesses PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Commands Commands Table 6 provides a quick reference of available commands This is followed by... states Operations already in progress are not affected PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Commands LOAD MODE REGISTER The mode register is loaded via inputs A0–A11 (A12 should be driven... to any READ or WRITE commands being issued to that bank PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Commands Auto Precharge Auto precharge is a feature that performs the same individual-bank PRECHARGE... WE# A0–A12 BA0, BA1 ROW ADDRESS BANK ADDRESS Don’t Care PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Operations Figure 8: Example Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK ≤ 3 T0 T1 T2 NOP NOP T4... DISABLE AUTO PRECHARGE BA0, BA1 BANK ADDRESS Don't Care PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Operations Figure 10: CAS Latency T0 T1 T2 T3 READ NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL =... each subsequent READ may be performed to a different bank PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev L 10/07 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice ©2000 Micron Technology, Inc All rights reserved 512Mb: x4, x8, x16 SDRAM Operations Figure 11: Consecutive READ Bursts T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK,