Carbon nanotube field effect transistor based decimal decoder and multiplexer circuits

RESEARCH ARTICLE Quantum Matter Copyright © 2015 American Scientific Publishers All rights reserved Printed in the United States of America Vol 4, 565–569, 2015 Carbon Nanotube Field Effect Transistor-Based Decimal Decoder and Multiplexer Circuits Fazel Sharifi, Mohammad Hossein Moaiyeri, Keivan Navi∗ , and Mohammad Amin Taherkhani Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, 1983963113, Iran; Nanotechnology and Quantum Computing Lab, Shahid Beheshti University, G.C., Tehran, 1983963113, Iran Decoders and multiplexers are known as the fundamental components of the arithmetic circuits Design of MVL based decoders and multiplexers presents many advantages related to the reduction of interconnections in addition to a significant improvement of data density This study focuses on the design of decimal decoders and multiplexers based on the unique advantages of the carbon nanotube field effect transistor (CNFET), such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobility for the N-type and P -type devices Synopsys HSPICE with the Stanford 32 nm CNFET model has been utilized to evaluate the proposed circuits The results authenticate the functionality of circuits with reasonable delay and power consumption Keywords: Nanoelectronics, Carbon Nanotube Field Effect Transistor (CNFET), Decimal Logic, Combinational Circuit INTRODUCTION Nowadays, many applications such as signal processing, pattern recognition and business intelligence have faced the challenge of massive data processing within a reasonable time and power Based on these requirements, high-efficiency hardware platforms and circuits need to be designed and fabricated In this situation, meeting the constraints of power, performance and area becomes as an important necessity for chip designers Many techniques such as MVL circuits have been employed to improve the data intensity and reduce the power, delay and area of digital circuits Multiple-valued logic (MVL) circuits have become interesting for researchers in recent years, because of some of their critical features related to the reduction of the number of interconnections, and their increased information content per unit area Most of the previous MVL circuits have been designed based on ternary logic (three-level logic) or quaternary logic (fourlevel logic).1–5 Decoder and multiplexer circuits are among the most important components in the arithmetic circuits and are used widely in logic designs, especially in the MVL circuits Several researches have already introduced MVL decoders and multiplexers Decimal logic is one of the subsections of MVL paradigm that a lot of researches have been accomplished on it during the recent decades However, due to the hardware complexity of decimal circuits, these researches have been done based on ∗ Author to whom correspondence should be addressed Quantum Matter Vol 4, No 6, 2015 binary codded decimal (BCD) The other reason for designing of conventional decimal circuits is directly related to characteristics underlying the fabrication technologies However, designs based conventional decimal logic caused non-optimal circuits in terms of the criteria such as transistor count, power and delay parameters For many years, MOSFET has been used as the basic element in designing analog and digital circuit As the miniaturization of silicon based circuits reaches its physical limitations, some beyond-MOSFET nanoelectronic and optoelectronic devices, such as quantum-dot cellular automata (QCA), single electron technology (SET), Carbon nanotube field effect transistor (CNFET), optic interconnections and nanowires are being considered as hopeful alternatives to the existing silicon technologies.6–13 Especially, characteristics of Carbon nanotube (CNT) such as high mobility of carries, high Ion /Ioff ratio and its unique one dimensional band structure and near ballistic transportation has made it as a very potential successor to the silicon MOSFET Since the I–V characteristics of the Carbon nanotube field effect transistor (CNFET) are qualitatively similar to the silicon MOSFET, most of MOS circuits can be translated to a CNFET based design without any significant modification As one of the hopeful new devices, CNFET avoids most of the basic limitations for conventional silicon devices.14 15 It is noticeable that efficient doping of nanotubes to fabricate and integrate P -type and N -type devices on the same substrate and effective nanofabrication methods are important areas of the future research in order to fabricate complementary VLSI-compatible circuits for quantum and nano electronics.16–18 However, even 2164-7615/2015/4/565/005 doi:10.1166/qm.2015.1232 565 RESEARCH ARTICLE Quantum Matter 4, 565–569, 2015 the explanation of modern quantum theory still appears to be an open question, as is presented in Ref [19] In this paper two new decimal decoders and a decimal multiplexer are proposed based on the CNFET technology and multiple threshold design style The rest of the paper is organized as follows: in Section 2, CNFET is described briefly In Section the proposed designs are described The simulation results are brought in Section and finally the paper is concluded in Section CARBON NANOTUBE FIELD EFFECT TRANSISTOR (CNFET) The Carbon nanotube is a sheet of graphite which is rolled up → → and joined together along a wrapping vector Ch = n1 − a1 + n2 − a2 and could be made of single or multiple sheets One or more semiconducting SWCNT (Single-Wall Carbon Nano Tube) are used as a channel for the CNFETs Single-walled CNTs are classified into three groups, depends on the chiral number (n1 , n2 : (1) armchair (n1 = n2 , (2) zigzag (n1 = or n2 = 0), and (3) chiral (all other indices).20 The operation principle of CNFET is comparable with that of conventional silicon devices This three (or four) terminal device consists of a semiconducting nanotube as the channel under a metallic gate, bridging the source and drain contacts Therefore, the device can be turned on or off electrostatically through the gate The quasi-1D device structure provides better gate electrostatic control above the channel region than 3D and 2D device structures In terms of the device operation mechanism, CNFET can be categorized as either Schottky Barrier (SB) controlled FET (SB-CNFET), MOSFET-like FET and band-to-band tunneling CNFET (T-CNFET),22 shown in Figure SB-CNFET is constructed with a semiconducting nanotube and two metallic contacts with a specific work function, acting as source and drain The work function of the metallic source and drain determines the type of the channel (N or P ) and consequently this type of CNFET shows ambipolar characteristics The Schottky Barriers formed in the channel to source/drain contacts degrade the device performance in ON state and increase the leakage current in OFF state However, in the MOSFET-like CNFET the channel to source/drain junctions have no Schottky Barrier is formed and instead the low-resistance ohmic contacts between the highly doped CNT source/drain regions and the metallic contacts result in a significantly higher ION /IOFF ratio Moreover, this type of CNFET has unipolar characteristics Therefore, the MOSFET-like CNFET is very suitable for ultrahigh-performance digital applications In addition, T-CNFET has low ON current and low subthreshold swing but very low ON current and its application is limited to ultra-low-power subthreshold circuits As a result, in this paper, MOSFET-like CNFETs are utilized for designing the proposed circuits The schematic of a MOSFET-like CNFET is shown in Figure Fig Schematic of a MOSFET-like CNFET The distance between the centers of two neighboring nanotubes under the gate of a CNFET is called pitch This parameter dominantly determines the width of the gate and the contacts of the transistor The width of the gate of a CNFET can be almost calculated based on the following equation:23 Wgate (1) Where, N is the number of nanotubes under the gate and Wmin is the minimum width of the gate The threshold voltage of a CNFET is proportional to the inverse of the diameter of its nanotubes This useful property will ease circuit designing and increase circuit performance The threshold voltage of a CNFET is calculated based on Eqs (2) and (3).23 436 DCNT nm √ √ 3a0 n2 + m2 + nm Vth = DCNT = (2) (3) Where, a0 (≈0.144 nm) is the carbon to carbon bond length in a CNT, V (≈3.033 eV) is the carbon – bond energy in the tight bonding model and DCNT is the diameter of the nanotubes The possibility of determining the desired threshold voltage based on the diameter of nanotubes makes the CNFET device very suitable for designing multiple threshold circuits PROPOSED DESIGNS 3.1 Decimal Decoder The decimal decoder is a one-input, ten-output combinational circuit Decimal decoder operates based on following equation: ⎧ ⎨VDD if x = k Xk = (4) ⎩ if x = k Fig Different types of CNFET device (a) SB-CNFET (b) MOSFET-like CNFET (c) T-CNFET 566 Max Wmin N Pitch RESEARCH ARTICLE Quantum Matter 4, 565–569, 2015 S0 Dec0 0.5 IN0 Dec1 1.5 Dec2 2.5 Dec3 S0 S1 IN1 3.5 Dec4 4.5 Dec5 5.5 Dec6 6.5 Dec7 Decimal Decoder S S0 S1 S1 Out S9 IN S9 IN9 S9 Fig 7.5 Dec9 8.5 Fig The proposed decimal decoder Where, x is a given input and k can take values of to The proposed decimal decoder circuit consisting of 10 inverters and XOR gates is shown in Figure The utilized inverters have different thresholds in order to detect the corresponding input values Based on Eq (1), the threshold voltage of a CNFET Dec0 Dec1 2.5 3.5 is inversely proportional to the diameter of its CNTs Therefore by adjusting the diameter the desired threshold voltages can be obtained The logical threshold values of the first inverter to the ninth one are 0.5, 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, and 8.5, respectively As the input logic value can be to 9, when the input is 9, the outputs of all inverters are For turning on the 9th decoder output, we just need an inverter to turn the output of the last inverter to VDD When the input is all inverters outputs are Table I Characteristics of the used MOSFEET-like CNTFET model Parameter 0.5 1.5 The proposed decimal multiplexer Dec8 Dec2 Dec3 Dec4 Lch Lss Ldd Lgeff Pitch IN 4.5 Dec5 Leff Sub_pitch 5.5 6.5 Dec6 Dec7 Kox T _ox Ksub 7.5 Dec8 8.5 Dec9 Csub Efi phi_M phi_S Fig Brief description Value Physical channel length The length of doped CNT source-side extension region The length of doped CNT drain-side extension region The Scattering mean free path in the intrinsic CNT channel and S/D regions The distance between the centers of two neighboring CNTs within the same device The mean free path in p + /n+ doped CNT Sub-lithographic (e.g., CNT gate width) pitch The dielectric constant of high-k top gate dielectric material (HfO2 ) The thickness of high-k top gate dielectric material The dielectric constant of substrate (SiO2 The coupling capacitance between the channel region and the substrate (SiO2 ) The Fermi level of the doped S/D tube The work function of Source/Drain metal contact CNT work function ≥10 nm ≥10 nm ≥10 nm 100 nm 20 nm 15 nm ≥4 nm 16 nm 40 aF/ m eV 4.6 eV 4.5 eV The proposed modified decimal decoder 567 RESEARCH ARTICLE Table II Quantum Matter 4, 565–569, 2015 Simulation results (@0.9 V and 500 MHz) Proposed design Decoder Modified decoder MUX Delay (×10−11 s) Power (×10−6 W) Power delay product (PDP) (×10−15 J) 3.829 2.236 2.646 088 228 10 08 15 65 221 26 69 The rest of the decoder outputs will become VDD with the same method 3.2 The Modified Decimal Decoder The decimal decoder which is proposed in the previous section used XOR gates in its structure Using the XOR gate leads to more complexity compared to the other gates such as NOR and NAND The drawbacks of using the XOR are higher power consumption and using more transistors compare to the other basic gates Therefore, in this section a modified decimal decoder is proposed, which eliminates the XOR gates and instead it utilizes inverter and NOR gates The schematic of this circuit is shown in Figure 3.3 Decimal Multiplexer In this section, a decimal multiplexer is proposed Decimal multiplexer has one selector which can take a value from to and based on this value one of ten inputs will be selected and connected to the output The proposed decimal multiplexer, shown in Figure 5, is designed based on a decimal decoder and transmission gates The outputs of decimal decoder are given to the transmission gates Since at the same time just one of the decoder outputs is VDD , consequently just one of the transmission gates will be turned on and transmits its input to the output of the decimal multiplexer SIMULATION RESULTS Fig Transient respond of the decimal decoder but the last one because of its threshold Using of XOR gate turns the 8th decoder output to VDD When the input value is 0, all inverters outputs are VDD As a result, the first decoder output is VDD and others are because the XOR gates make them In this part of the paper, the performance of proposed designs is evaluated in various test conditions The circuits are simulated using Synopsys HSPICE simulator with the Stanford SPICE model for 32 nm CNFETs (Lg = 32 nm) including all non-idealities and parasitics.24 25 This model considers a realistic, circuit-compatible CNTFET structure and contains practical device nonidealities, parasitics, Schottky barrier effects, inter-CNT charge screening effects, doped source-drain extension regions, scattering (nonideal near-ballistic transport), back-gate (substrate bias) effect and Source/Drain, and Gate resistances and capacitances The model also contains a full transcapacitance network for more accurate transient and dynamic performance simulations The parameters of the CNTFET model and their values, with brief descriptions, are listed in Table I Fig Delay, power and PDP variations of proposed designs against frequency variations 568 RESEARCH ARTICLE Quantum Matter 4, 565–569, 2015 Fig Delay, power and PDP variations of proposed designs against temperature variations Simulations are conducted at 0.9 V power supply, 2.1 fF output load capacitor, at different temperatures and operating frequencies The propagation delay of each circuit is calculated from the time that the input signal reaches the half of its upcoming voltage level to the time that the output signal reaches the half of its upcoming voltage level The simulation results are briefly described in Table II As shown in Table II, the delay of the modified decoder is improved about 41% comparing with its previous version Also the power consumption is decreased about 21% and consequently the power delay product (PDP) is improved 53% The transient response of the proposed decoder is demonstrated in Figure To evaluate the performance of the circuits at different frequencies, they are tested at 100 MHz up to GHz at 0.9 V supply voltage with a 2.1 fF output load capacitor Another important characteristic of the circuits which should be taken into consideration is their insusceptibility to the ambient temperature variations On account of that, the proposed circuits are simulated in a various range of temperatures, from up to 80 C, to measure their sensitivity to the temperature variations Figures and show the low sensitivity of the proposed designs at different frequencies and temperatures respectively CONCLUSION In this paper decoders and multiplexers have been proposed The CNFET technology has been introduced to overcome the limitations of the MOSFET technology All of the proposed circuits have been designed based on the unique properties of the CNFET nanodevice The simulation results verify the operation of the proposed designs with high-performance The performance of designs has been evaluated using Synopsis HSPICE simulator and the Stanford CNFET model at 32 nm technology node References and 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