Vi điều khiển và ứng dụng Interrupt

Chuyên đề II Vi điều khiển ứng dụng Interrupt and A/D Bảng Vector ngắt Chi tiết Bảng chi tiết INT and AINT Interrupt Vector Table starting at location 0x000004 up to 54 sources of interrupt Interrupt Service Routine (ISR) Alternate Vector Table Access to the AIVT is provided by the ALTIVT control bit (INTCON2) If the ALTIVT bit is set, all interrupt will use the alternate vectors instead of the default vectors Ví dụ Ưu tiên ngắt  user assigned priority levels  Natural priority resolves conflicts  User-assigned priority can override natural priority  CPU Status Register, known as SRL, has status bits for priority Ngắt ngắt  An ISR may be interrupted by a higher priority interrupt  Nesting can be disabled by setting NSTDIS bit in INTCON1 register  Temporarily raising CPU interrupt priority to in ISR can also disable nesting Traps  Oscillator Failure Trap (level 14 - hard trap) Address Error Trap (level 13 - hard trap)  Instruction fetch from illegal program space Data fetch from unimplemented data space Unaligned word access from data space  Stack Error Trap (level 12 - soft trap) Stack overflow or underflow   Math Error Trap (level 11 - soft trap) Divide by Zero  Unsaturated Accumulator Overflow (A or B) l Catastrophic Accumulator Overflow (either) l Accumulator Shift Overflow  Trap 10 Interrupt Disable “DISI” Instruction  DISI disables level - interrupts for “N+1” instruction cycles  Supports a maximum of 16384 cycles  DISI #5 ; disable for cycles  DISI expires when DISICNT decrements to DISICNT can be written to modify DISI time  DISICNT can be cleared to cancel instruction 11 Interrupt Control and Status Registers  INTCON1, INTCON2 Registers  IFSx: Interrupt Flag Status Registers  IECx: Interrupt Enable Control Registers  IPCx: Interrupt Priority Control Registers  SR: CPU Status Register 12 Ví dụ 13 Interrupt Config 14 Các bước khởi tạo ngắt  Set the priority bits in the appropriate IPC register  Clear the interrupt flag in the appropriate IFS register  Set the interrupt enable bit in the appropriate IEC register  Configure the peripheral interrupt source Enable the peripheral interrupt source   15 Ví dụ  void attribute (( interrupt)) _T1Interrupt ( void) { // interrupt service routine code here } // _InterruptVector void _ISR _T1Interrupt (void) { // remember to clear the interrupt flag before exit _T1IF = 0; } // _InterruptVector 16 Chi tiết INTCON1, INTCON2 17 Interrupt flag status register IFS0 18 IFS1 19 Interrupt enable control register - IEC0 20 Interrupt priorities 21 [...]... peripheral interrupt source   15 Vi dụ  void attribute (( interrupt) ) _T 1Interrupt ( void) { // interrupt service routine code here } // _InterruptVector void _ISR _T 1Interrupt (void) { // remember to clear the interrupt flag before exit _T1IF = 0; } // _InterruptVector 16 Chi tiết INTCON1, INTCON2 17 Interrupt flag status register IFS0 18 IFS1 19 Interrupt enable control register 0 - IEC0 20 Interrupt. .. Registers  IECx: Interrupt Enable Control Registers  IPCx: Interrupt Priority Control Registers  SR: CPU Status Register 12 Vi dụ 13 Interrupt Config 14 Các bước khởi tạo ngắt  Set the priority bits in the appropriate IPC register  Clear the interrupt flag in the appropriate IFS register  Set the interrupt enable bit in the appropriate IEC register  Configure the peripheral interrupt source.. .Interrupt Disable “DISI” Instruction  DISI disables level 1 - 6 interrupts for “N+1” instruction cycles  Supports a maximum of 16384 cycles  DISI #5 ; disable for 6 cycles  DISI expires when DISICNT decrements to 0 DISICNT can be written to modify DISI time  DISICNT can be cleared to cancel instruction 11 Interrupt Control and Status Registers  INTCON1, INTCON2 Registers  IFSx: Interrupt ... peripheral interrupt source Enable the peripheral interrupt source   15 Ví dụ  void attribute (( interrupt) ) _T 1Interrupt ( void) { // interrupt service routine code here } // _InterruptVector... _ISR _T 1Interrupt (void) { // remember to clear the interrupt flag before exit _T1IF = 0; } // _InterruptVector 16 Chi tiết INTCON1, INTCON2 17 Interrupt flag status register IFS0 18 IFS1 19 Interrupt. .. cancel instruction 11 Interrupt Control and Status Registers  INTCON1, INTCON2 Registers  IFSx: Interrupt Flag Status Registers  IECx: Interrupt Enable Control Registers  IPCx: Interrupt Priority