Thông tin tài liệu
DESIGN OF A WIDE INPUT SUPPLY RANGE
BUCK-
(B.Eng (Hons), NUS)
&
2009
ACKNOWLEDGEMENTS
The author would like to express his gratitude to project supervisor, A/Prof Xu Yong Ping
for his invaluable advice and guidance during the course of the author’s work.
i
TABLE OF CONTENTS
i
SUMMARY
1
1.1
Future Trend
1.2
Alternate Sustainable Energy Sources
1.3
Linear Low-Dropout Regulator versus Switch-Mode Power Supplies
1.3.1
Linear Low-Dropout Regulator
1.3.2
Switch-Mode DC-DC Power Supplies
Ch ap t er 2
B u c k -B o o s t Co n v er t er To p o l o g i es
1
2
3
3
6
9
2.1
Conventional Inverting Buck-Boost Converter
2.1.1
Continuous Conduction Mode
2.1.2
Discontinuous Conduction Mode
2.2
4-Switches Non-Inverting Buck-Boost Converter
2.2.1
Continuous Conduction Mode
2.2.2
Discontinuous Conduction Mode
2.3
Modified 4-Switches Non-Inverting Buck-Boost Converter
2.3.1
Buck Mode Operation
2.3.1.1
Buck Configuration - Continuous Conduction Mode
2.3.1.2
Buck Configuration - Discontinuous Conduction Mode
2.3.2
Boost Mode Operation
2.3.2.1
Boost Configuration - Continuous Conduction Mode
2.3.2.2
Boost Configuration -Discontinuous Conduction Mode
2.3.3
Buck-Boost Mode Operation
2.4
Inverting Cuk Buck-Boost Converter
2.4.1
Cuk Buck-Boost Converter Operations
2.5
Recent Publications and Developments
2.6
Overall Architecture of Proposed Buck-Boost Converter
9
10
13
16
17
20
22
23
24
25
27
28
28
30
31
32
34
36
3.1
Traditional Bandgap Reference
3.1.1
Negative Temperature Coefficient
3.1.2
Positive Temperature Coefficient
3.2
Bandgap Reference Design Specifications
3.3
Bandgap Reference Design implementation
42
42
43
46
47
3.3.1
Bandgap Reference Operational Amplifier Design
3.3.2
Bandgap Reference Top
3.4
Bandgap Reference Simulation Results
3.4.1
Bandgap 250mV Variation with Temperature
3.4.2
Bandgap 660mV Variation with Temperature
3.4.3
Bandgap 250mV Variation with Temperature & Process Corner/ Mismatch
3.4.4
Bandgap 660mV Variation with Temperature & Process Corner/ Mismatch
3.4.5
Bandgap Reference Frequency Response
3.4.6
Bandgap 660mV Variation with Substrate Voltage
3.4.7
Bandgap Profile during Supply Startup
3.4.8
Bandgap Reference Line Transient Response
3.5
Bandgap Reference Simulated Performance (Summarized)
49
51
53
53
55
56
59
62
64
65
67
68
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Startup Control Circuitries Design Considerations
Proposed Design for Startup Control System
Adaptive Start-Up On-Time Generator Design
Current-Starved Start-Up Ring Oscillator Design
Startup Adaptive On-Time Generator Simulation Results
Startup Current-Starved Ring Oscillator Simulation Results
Startup Ring Oscillator Simulated Performance (Summarized)
69
70
72
76
79
84
87
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.8
Internal Power Management System
Internal Regulator 1 Design Considerations
Internal Regulator 1 Intermediate Buffer Design
Internal Regulator 1 Error Amplifier Design
Internal LDO Regulator 1 Stability Analysis
Internal Regulator 1 Reference Generator Design
Internal Regulator 1 Simulation Results
Internal Regulator 1 Output VSS_V33_EXT Variation with Substrate Input
Internal LDO Regulator 1 Frequency Response
Internal Regulator 1 Line Transient Response
Internal Regulator 1 Power Supply Rejection Ratio (PSRR)
Internal Regulator 1 Transient Response
Internal LDO Regulator 1 Simulated Performance (Summarized)
88
93
97
99
100
103
106
106
107
110
112
112
114
6.1
6.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
Internal Regulator 2 Design Considerations
Internal Low-Dropout Regulator 2 Input Reference
Internal Low-Dropout Regulator 2 Design
Internal Low-Dropout Regulator 2 Simulation Results
Internal Low-Dropout Regulator 2 Frequency Response
Internal Low-Dropout Regulator 2 Output Variation with VPSUB
Internal Low-Dropout Regulator 2 Line Transient Response
Internal Regulator 2 and Power NMOS Driver Transient Response
115
116
117
121
121
123
123
125
6.5
Internal LDO Regulator 2 Simulated Performance (Summarized)
126
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.5
External LDO Regulator Design Considerations
External LDO Regulator Intermediate Buffer Design
External LDO Regulator Stability Analysis
External LDO Regulator Simulation Results
External Regulator Frequency Response
External LDO Regulator Output Variation with V33
External LDO Regulator Line Transient Response
External LDO Regulator Load Transient Response
External LDO Regulator Simulated Performance (Summarized)
127
128
131
134
134
139
140
143
145
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Regulatory Control Scheme Design Considerations
Regulatory Control System Design
Regulatory Comparator Design Considerations
Regulatory Current-Starved Ring Oscillator Design
Regulatory Regenerative Comparator Design
Regulatory Current-Starved Ring Oscillator Simulation Results
Regulatory Regenerative Latch Comparator Simulation Results
Regulatory Control System Simulation Results
Regulatory System Sub-blocks Simulated Performance (Summarized)
147
148
150
151
154
157
160
161
163
9.1
9.2
9.3
9.4
9.5
9.6
Buck-Boost Converter Synchronous Operations
Anti-Backflow Current Control System Design Considerations
Anti-Backflow Current Control System Design
Anti-Backflow Current Control Comparator Design
Anti-Backflow Current Control On-Time Generator Design
Anti-Backflow Current Control Comparator Simulation Results
164
166
168
170
172
176
10.1
10.2
10.3
10.4
10.5
10.6
Austria Microsystems 0.35µm High-Voltage Process
Pin Allocation
Chip Top Layout
Buck-Boost Converter Startup Transient Response
Buck-Boost Converter Steady-State Response
Summary
181
184
184
186
188
189
11.1
11.2
Buck-Boost Converter Performance Comparison
Novel Buck-Boost Converter Design
190
193
A.1
A.2
A.3
A.4
A.5
A.6
A.6.1
A.6.2
A.7
Adaptive NMOS Power Transistor On-Time
Simple Adaptive On-Time Generator
Proposed Adaptive On-Time Generator Design
Proposed Adaptive On-Time Generator Amplifier Design
Proposed Adaptive On-Time Generator Comparator Design
Adaptive On-Time Generator Simulation Results
Voltage-to-Current (V-I) Converter AC Loop Response
Adaptive On-Time Generator Transient Response
Adaptive On-Time Generator Simulated Performance (Summarized)
B.1
Current Reference Design
B.2
Current Reference Simulation Results
B.2.1
Current Bias Generator Loop Frequency Response
B.2.2
Bias Current Supply Dependence
200
200
203
205
207
208
208
212
217
218
220
220
222
VSS_V33_EXT
V33 to VSS_V33_EXT Level Shifter Design
C.1
C.2
Level Shifter Simulation Results
224
226
D.1
D.2
D.3
D.3.1
D.3.2
D.3.3
D.4
Test Setup
Test Method
Test Results
Buck-Boost Converter Startup
Buck-Boost Converter Regulation
Buck-Boost Converter Line Transient Response
Discussions & Suggestions
229
230
231
232
233
235
238
SUMMARY
Buck-boost converters allow the flexibility of stepping-up and stepping-down the input
supply to generate a regulated output, thus making it very attractive for applications with
wide input supply range. Currently, off-the-shelf buck-boost converters require a
minimum operating voltage of 1.8V. As a result, the operating conditions in which these
applications are functional are severely limited. Recently, boost converters which can
operate with a minimum supply voltage of 0.3V are introduced and they are designed for
applications utilizing solar cells as an energy source. However, boost converters are only
capable of stepping-up the input supply. In this project, the concepts implemented for
these boost converters are modified and extended for use in buck-boost converter
implemented using the conventional inverting topology. The converter is designed for
low-power applications and it caters to a maximum load of 25mA. Special startup
circuitries are designed to ensure that the startup inductor current peak is controlled,
without damaging the device and to allow startup operations with minimal input voltage.
In addition, a novel internal power management system is implemented and it allows for
continual steady-state operations even as input drops to 0.3V. The converter operates in
Pulse Frequency Modulation (PFM) mode during steady-state. Synchronous rectification
operations are supported for the buck-boost converter through the implementation of a
novel anti-backflow current system which greatly reduces the quiescent current
consumption. The converter is designed in AMS High-Voltage 0.35 m process. The
dimension of the layout implementation is 2.519mm by 2.371mm. Simulation results
have shown that the converter consumes only 10.77 A and is able to startup with input
supply of 0.75V typically. In addition, the converter is able to remain in steady-state
operations even as input drops to 0.30V. With an input of 5.0V and an external load of
25mA, the designed converter possesses a conversion efficiency of 88.3%.
ii
LIST OF TABLES
Table 1-1: DC-DC converters summarized performance
8
Table 2-1: Buck-boost converter topologies summarized characteristics
35
Table 2-2: Buck-boost converter circuit blocks roles & functionalities (Summarized)
41
Table 3-1: Bandgap reference summarized simulated performance
68
Table 4-1: Startup current-starved ring oscillator summarized simulated performance
87
Table 5-1: Internal LDO regulator 1 summarized simulated performance
114
Table 6-1: Internal LDO regulator 2 summarized simulated performance
126
Table 7-1: External LDO regulator summarized simulated performance
146
Table 8-1: Regulatory control system sub-blocks summarized simulated performance
163
Table 10-1: Power management IC pin allocation and definitions
185
Table A-1: Adaptive on-time generator summarized simulated performance
217
iii
LIST OF FIGURES
Figure 1-1: Linear low-dropout regulator block diagram
3
Figure 1-2: Energy harvested from piezoelectric shoes on storage capacitor [2]
5
Figure 1-3: DC voltage generated by piezoelectric harvester with different wind speed [3]
5
Figure 2-1: Conventional Inverting Buck-Boost Converter [9]
9
Figure 2-2: Ideal CCM operation of inverting buck-boost converter (VS=5.0V, Vout=2.5V)
12
Figure 2-3: Ideal CCM operation of inverting buck-boost converter (VS=1.0V, Vout=2.5V)
13
Figure 2-4: Ideal DCM operation of inverting buck-boost converter (VS=5.0V, Vout=2.5V)
15
Figure 2-5: Ideal DCM operation of inverting buck-boost converter (VS=1.0V, Vout=2.5V)
15
Figure 2-6: 4-Switches Non-Inverting Buck-Boost Converter [9]
16
Figure 2-7: Ideal CCM operation of 4-switches converter (VS=3.3V, Vout=2.5V)
18
Figure 2-8: Ideal CCM operation of 4-switches converter (VS=2.5V, Vout=2.5V)
19
Figure 2-9: Ideal CCM operation of 4-switches converter (VS=1.0V, Vout=2.5V)
19
Figure 2-10: Ideal DCM operation of 4-switches converter (VS=3.3V, Vout=2.5V)
21
Figure 2-11: Ideal DCM operation of 4-switches converter (VS=2.5V, Vout=2.5V)
21
Figure 2-12: Ideal DCM operation of 4-switches converter (VS=1.0V, Vout=2.5V)
22
Figure 2-13: 4-switches non-inverting buck-boost converter in buck configuration [9]
23
Figure 2-14: Ideal CCM operation of modified 4-switches converter (VS=3.3V, Vout=2.5V)
25
Figure 2-15: Ideal DCM operation of modified 4-switches converter (VS=3.3V, Vout=2.5V)
26
Figure 2-16: 4-switches non-inverting buck-boost converter in boost configuration [9]
27
Figure 2-17: Ideal CCM operation of modified 4-switches converter (VS=1.0V, Vout=2.5V)
29
Figure 2-18: Ideal DCM operation of modified 4-switches converter (VS=1.0V, Vout=2.5V)
30
Figure 2-19: Inverting Cuk Buck-Boost Converter [9]
32
Figure 2-20: Proposed Inverting Buck-Boost Converter Block Diagram
37
Figure 3-1: Traditional bandgap reference circuit implementation
44
Figure 3-2: Schematic of low-supply voltage bandgap core circuit [17]
47
Figure 3-3: Schematic of operational amplifier in bandgap core circuit
50
Figure 3-4: Schematic of bandgap reference top inclusive of buffer
52
Figure 3-5: Bandgap reference variation with temperature (V33=1.5V, Typical)
53
Figure 3-6: Bandgap reference variation with temperature (V33=1.2V, Typical)
54
Figure 3-7: Bandgap reference variation with temperature (V33=2.0V, Typical)
55
Figure 3-8: Bandgap reference variation with temperature (V33=3.3V, Typical)
56
Figure 3-9: Bandgap reference variation with temperature (V33=1.2V, Corners)
57
Figure 3-10: Bandgap reference temperature coefficients before trim (V33=1.2V)
58
iv
Figure 3-11: Bandgap reference temperature coefficients after trim (V33=1.2V)
58
Figure 3-12: Bandgap reference output after trim (V33=1.2V)
59
Figure 3-13: Bandgap reference variation with temperature (V33=3.3V, Corners)
60
Figure 3-14: Bandgap reference temperature coefficients before trim (V33=3.3V)
60
Figure 3-15: Bandgap reference temperature coefficients after trim (V33=3.3V)
61
Figure 3-16: Bandgap reference output after trim (V33=3.3V)
61
Figure 3-17: Bandgap 250mV loop gain frequency response (V33=1.2V, Typical)
62
Figure 3-18: Bandgap 250mV loop gain frequency response (V33=1.5V, Typical)
63
Figure 3-19: Bandgap 660mV loop gain frequency response (V33=3.3V, Typical)
63
Figure 3-20: Bandgap reference variation with substrate (V33=2.0V, Typical)
64
Figure 3-21: Bandgap reference variation with substrate (V33=3.3V, Typical)
65
Figure 3-22: Bandgap reference 250mV startup (V33 ~ 0V to 1.2V in 1ms, Typical)
66
Figure 3-23: Bandgap reference 660mV startup (V33 ~ 0V to 3.3V in 1ms, Typical)
66
Figure 3-24: Bandgap line transient (V33 ~ 1.2V to 1.5V in 1µs, Typical)
67
Figure 3-25: Bandgap line transient (V33 ~ 3.225V to 3.375V in 30µs, Typical)
68
Figure 4-1: Startup control system block diagram
71
Figure 4-2: Simple startup adaptive on-time generator schematic
74
Figure 4-3: Startup Current-Starved Ring Oscillator Schematic
77
Figure 4-4: Startup adaptive on-time & Current limit generated (Typical, VPSUB=-1.5V)
79
Figure 4-5: Startup adaptive on-time & Current limit generated (Corners, VPSUB=-1.5V)
80
Figure 4-6: Startup adaptive on-time & Current limit generated (Typical, VPSUB=-3.0V)
81
Figure 4-7: Startup adaptive on-time & Current limit generated (Typical, VPSUB=-5.0V)
82
Figure 4-8: Startup adaptive on-time & Current limit generated (Typical, VPSUB=-10.0V)
82
Figure 4-9: Startup adaptive on-time & Current limit generated (Corners, VPSUB=-10.0V)
83
Figure 4-10: Startup adaptive current limit generated against VPSUB (Typical)
83
Figure 4-11: Startup ring oscillator output transient response (Corners, VPSUB=-1.0V)
84
Figure 4-12: Startup ring oscillator transient response (Corners, VPSUB=-1.5V)
85
Figure 4-13: Startup ring oscillator transient response (Corners, VPSUB=-3.0V)
85
Figure 4-14: Startup ring oscillator transient response (Corners, VPSUB=-5.0V)
86
Figure 4-15: Startup ring oscillator transient response (Corners, VPSUB=-10.0V)
86
Figure 5-1: Internal Power Management Scheme A
89
Figure 5-2: Internal Power Management Scheme B
91
Figure 5-3: Architecture of LDO regulator with intermediate buffer stage [31]
96
Figure 5-4: Simple source-follower implementation of the intermediate buffer [31]
97
Figure 5-5: Source-follower with shunt feedback implementation of the buffer
98
v
Figure 5-6: Folded-cascode error amplifier in architecture of LDO regulator [31]
100
Figure 5-7: Internal low-dropout regulator 1 with reference generator schematic
105
Figure 5-8: DC variation of VSS_V33_EXT and the reference generator output with VPSUB
106
Figure 5-9: Internal LDO 1 regulation loop response (V33=3.3V, VPSUB=-5.0V, Typical)
107
Figure 5-10: Internal LDO 1 regulation loop response (V33=3.3V, VPSUB=-5.0V, W.C)
108
Figure 5-11: Internal LDO 1 regulation loop response (V33=3.3V, VPSUB=-5.0V, Corner)
109
Figure 5-12: Internal LDO 1 regulation loop response (V33=3.3V, VPSUB=-0.30V, Corner) 109
Figure 5-13: Internal LDO 1 regulation loop response (V33=3.3V,VPSUB=-10.0V, Corner) 110
Figure 5-14: Internal LDO regulator 1 line transient response (V33=3.3V, Typical)
111
Figure 5-15: Internal LDO regulator 1 line transient response (V33=3.3V, Corners)
111
Figure 5-16: Internal LDO regulator 1 PSRR (V33=3.3V, VPSUB=-5.0V, Corners)
112
Figure 5-17: Internal LDO 1 output transient response (VPSUB=-5.0V, Corners)
113
Figure 5-18: Internal LDO 1 low to high output response (VPSUB=-5.0V, Corners)
113
Figure 6-1: Internal LDO reference and regulator 2 schematic
118
Figure 6-2: Structure of low-dropout regulator utilizing PCFC scheme [36]
120
Figure 6-3: Internal LDO 2 regulation loop frequency response (VPSUB=-5.0V, Typical)
122
Figure 6-4: Internal LDO 2 regulation loop frequency response (VPSUB=-5.0V, Corner)
122
Figure 6-5: Internal LDO 2 regulation loop frequency response (PreDrvN=0V, Typical)
123
Figure 6-6: Internal LDO 2 output variation with VPSUB (No Load, Corners)
124
Figure 6-7: Internal LDO 2 reference and output line transient (VPSUB=-5.0V, Typical)
124
Figure 6-8: Internal LDO 2 reference and output line transient (VPSUB=-5.0V, Corners)
125
Figure 6-9: Internal LDO 2 and power NMOS driver transient (VPSUB=-5.0V, Typical)
125
Figure 7-1: Direct implementation of NMOS source-follower with shunt feedback
130
Figure 7-2: Folded-cascode implementation of source-follower with shunt feedback
131
Figure 7-3: External low dropout regulator schematic
133
Figure 7-4: External LDO regulation loop response (V33=1.2V, ILoad=0mA, Typical)
134
Figure 7-5: External LDO regulation loop response (V33=1.2V, ILoad=2mA, Typical)
135
Figure 7-6: External LDO regulation loop response (V33=1.2V, ILoad=0mA, Corners)
136
Figure 7-7: External LDO regulation loop response (V33=1.2V, ILoad=2mA, Corners)
136
Figure 7-8: External LDO regulation loop response (V33=3.3V, ILoad=0mA, Typical)
137
Figure 7-9: External LDO regulation loop response (V33=3.3V, ILoad=2mA, Typical)
138
Figure 7-10: External LDO regulation loop response (V33=3.3V, ILoad=0mA, Corners)
138
Figure 7-11: External LDO regulation loop response (V33=3.3V, ILoad=2mA, Corners)
139
Figure 7-12: DC variation of external LDO output with V33 when converter is disabled
140
Figure 7-13: External LDO regulator line transient response (V33=1.2V to 1.5V, Typical) 141
vi
Figure 7-14: External LDO regulator line transient response (V33=1.5V to 1.2V, Typical) 141
Figure 7-15: External LDO regulator line transient response (V33=3.0V to 3.3V, Typical) 142
Figure 7-16: External LDO regulator line transient response (V33=3.3V to 3.0V, Typical) 142
Figure 7-17: External LDO load transient response (V33=1.2V, ILoad=0mA to 2mA, Typ)
143
Figure 7-18: External LDO load transient response (V33=1.2V, ILoad=2mA to 0mA, Typ)
144
Figure 7-19: External LDO load transient response (V33=3.3V, ILoad=0mA to 2mA, Typ)
144
Figure 7-20: External LDO load transient response (V33=3.3V, ILoad=2mA to 0mA, Typ)
145
Figure 8-1: Regulatory system current-starved ring oscillator schematic
152
Figure 8-2: Regulatory system regenerative latch comparator schematic
156
Figure 8-3: Regulatory ring oscillator transient response (Typical, V33=3.3V)
157
Figure 8-4: Regulatory ring oscillator transient response (Typical, V33=2.0V)
158
Figure 8-5: Regulatory ring oscillator transient response (Corners, V33=3.3V)
159
Figure 8-6: Regulatory ring oscillator transient response (Corners, V33=2.0V)
159
Figure 8-7: Regulatory comparator preamp magnitude response (Corners, V33=3.3V)
160
Figure 8-8: Regulatory comparator preamp magnitude response (Corners, V33=3.0V)
161
Figure 8-9: Regulatory control transient response (Typical, V33=3.2875V to 3.3125V)
162
Figure 8-10: Regulatory control transient response (Typical, V33=3.3125V to 3.2875V)
162
Figure 9-1: Inverting buck-boost converter voltage & current profiles during operations
164
Figure 9-2: Inverting buck-boost converter waveforms for early and late turn-off
165
Figure 9-3: Anti-backflow current control comparator with input clamps schematic
171
Figure 9-4: Anti-backflow current control on-time generator schematic
173
Figure 9-5: Anti-backflow comparator transient response (Typical, V33=2.2V)
177
Figure 9-6: Anti-backflow comparator transient response (Corners, V33=2.2V)
178
Figure 9-7: Anti-backflow comparator zoomed transient response (Corners, V33=2.2V)
178
Figure 9-8: Anti-backflow comparator transient response (Typical, V33=3.3V)
179
Figure 9-9: Anti-backflow comparator transient response (Corners, V33=3.3V)
179
Figure 9-10: Anti-backflow comp zoomed transient response (Corners, V33=3.3V)
180
Figure 10-1: Cross sectional view of standard CMOS process NMOS
181
Figure 10-2: Buck-boost converter transistor type choice for each block
183
Figure 10-3: Power management IC top level layout
186
Figure 10-4: Buck-boost converter startup transient response (VPSUB=-5.0V, Typical)
187
Figure 10-5: Buck-boost converter startup transient response (VPSUB=-0.75V, Typical)
187
Figure 10-6: Buck-boost converter steady-state response (VPSUB=-5.0V, ILoad=25mA)
188
Figure A-1: Basic waveforms observed during operations of buck-boost converter
198
Figure A-2: Simple implementation of adaptive on-time generator [12]
200
vii
Figure A-3: Proposed adaptive on-time generator block diagram
204
Figure A-4: Adaptive on-time generator (regulatory control) schematic
206
Figure A-5: V-I Converter AC Loop Response (V33=3.3V, VPSUB=-5.0V, RBIAS=4.7MΩ)
209
Figure A-6: V-I Converter AC Loop Response (V33=2.2V, VPSUB=-5.0V, RBIAS=4.7MΩ)
209
Figure A-7: V-I Converter AC Loop Response (V33=3.3V, VPSUB=-0.30V, RBIAS=15MΩ)
210
Figure A-8: V-I Converter AC Loop Response (V33=2.2V, VPSUB=-0.30V, RBIAS=15MΩ)
211
Figure A-9: V-I AC Response (V33=3.3V, VPSUB=-0.30V, RBIAS=15MΩ, Corners)
211
Figure A-10: V-I AC Response (V33=2.2V, VPSUB=-0.30V, RBIAS=15MΩ, Corners)
212
Figure A-11: Adaptive Ton transient response (VPSUB=-5.0V, RBIAS=4.7MΩ, Corners)
213
Figure A-12: Adaptive Ton transient response (VPSUB=-0.30V, RBIAS=4.7MΩ, Corners)
213
Figure A-13: Adaptive Ton transient response (VPSUB=-10.0V, RBIAS=4.7MΩ, Corners)
214
Figure A-14: Adaptive on-time variation with VPSUB (V33=3.3V, RBIAS=4.7MΩ, Typical)
215
Figure A-15: Adaptive on-time variation with VPSUB (V33=3.3V, RBIAS=4.7MΩ, Fast)
216
Figure A-16: Adaptive on-time variation with VPSUB (V33=3.3V, RBIAS=4.7MΩ, Slow)
216
Figure B-1: Current bias generator and current mirrors schematic
219
Figure B-2: Current bias generator loop frequency response (Typical, V33=1.2V)
221
Figure B-3: Current bias generator loop frequency response (Typical, V33=3.3V)
221
Figure B-4: Voltage and Current Reference Supply Dependence (Typical, VPSUB=0.0V)
222
Figure B-5: Voltage and Current Reference Supply Dependence (Typical, VPSUB=-5.0V) 223
Figure C-1: V33 to VSS_V33_EXT level shifter schematic
225
Figure C-2: V33 to VSS_V33_EXT level shifter low-to-high transient profile (Typ, V33=3.3V)
227
Figure C-3: V33 to VSS_V33_EXT level shifter high-to-low transient profile (Typ, V33=3.3V)
227
Figure C-4: V33 to VSS_V33_EXT level shifter low-to-high transient profile (Typ, V33=2.0V)
228
Figure C-5: V33 to VSS_V33_EXT level shifter high-to-low transient profile (Typ, V33=2.0V) 228
Figure D-1: Bench evaluation setup and connections schematic
230
Figure D-2: Buck-boost converter bench evaluation - startup profile (VPSUB = -0.76V)
232
Figure D-3: Buck-boost converter bench evaluation - startup profile (VPSUB = -2.0V)
233
Figure D-4: Buck-boost converter bench evaluation - regulatory profile (VPSUB = -0.76V) 234
Figure D-5: Buck-boost converter bench evaluation - regulatory profile (VPSUB = -3.50V) 235
Figure D-6: Buck-boost bench evaluation – line transient (VPSUB ~ -0.30 to -1.30V)
236
Figure D-7: Buck-boost bench evaluation – line transient (VPSUB ~ -1.30 to -0.30V)
236
Figure D-8: Buck-boost bench evaluation – line transient (VPSUB ~ -1.0 to -2.0V)
237
Figure D-9: Buck-boost bench evaluation – line transient (VPSUB ~ -2.0 to -1.0V)
237
viii
-
CChhaapptteerr 11
Introduction
In recent years, the increasing demand for ultra low power portable devices, and the
growing requirements of more sophisticated functionalities embedded into these devices
had resulted in designers having to manage the power consumption of the underlying
chips more efficiently. Efficient power management techniques are much needed so as
to lengthen the battery life, without having to introduce batteries with higher capacities
which often incur higher manufacturing cost and result in a heavier device.
The rising energy cost and also the increasing awareness of environmental issues have
resulted in product developers to examine the possible use of sustainable energy
sources in applications. In fact, consumer electronic products such as solar chargers
which are based on “green” energy sources can already be found in the market.
However, in order for the traditional batteries to be effectively replaced by these
sustainable energy sources, the power conversion efficiency of these sources has to be
improved tremendously. Besides that, due to the differences in the characteristics of
these sources as compared to batteries, power management ICs which are more
efficient and are able to extract more power from these sources have to be developed.
Chip manufacturers are looking into this growing market with much enthusiasm and are
already in the process of developing ICs for these applications. Early this year,
1
-
Freescale Semiconductor has developed an integrated mixed signal chip that can boost
the output from a single solar cell into a usable power source [1]. Previously, in order to
harness green energy from solar cells, multiple cells need to be stacked in series, due to
the low voltage output from a single cell. This implies that in order to obtain a 3V output,
which is required to power conventional electronic products, 8 solar cells have to be
stacked in series. This results in not only higher cost of the product but also reduced
portability and reliability of the end product. Freescale Semiconductor claimed that the
boost converter is able to start from 0.32V and boost the output to 4V, by making use of
the low threshold MOS from its 130 nm Smartmos-10 process. Hence, with further
advancement in the power management techniques, one can foresee that the use of
sustainable energy sources in consumer electronics will be made more attractive.
Besides solar energy sources, researchers had examined other sustainable energy
sources. Way back in 1998, researchers from the MIT Media Lab had presented a selfpowered system [2] which had been built around a pair of shoes. The shoes can be used
to generate electrical power while walking. The electrical power generated allowed the
bearer to transmit a 12-bit RFID code while walking. Wind energy has also been used to
power autonomous wind speed sensors. In [3], a piezoelectric based wind energy
harvester was designed such that electrical power is generated to power a RF
transmitter. Information such as wind speed can then be remotely transmitted back to
base using this self-powered system. Although devices powered by sustainable energy
sources seem attractive, the availability of electrical power harvested is largely
dependent on the unpredictable environmental conditions. Hence, researchers and
product designers are looking into ways to store the energy harvested effectively so that
2
-
the storage can be tapped upon during unfavorable conditions. Alternatively, systems
running on dual or multiple energy sources can be designed. However, the different
characteristics, i.e. differences in supply voltage ranges etc., of the energy sources have
to be considered in designing the power management unit.
-
-
-
1-1: Linear low-dropout regulator block diagram
Figure 1-1 shows a general block diagram of a linear regulator. It consists of a bandgap
reference generator and an error amplifier used to regulate the output voltage by
controlling the pass transistor. The design is simple and depending on the specifications
for the regulated voltage, an output filtering capacitor may or may not be required.
Hence, minimal external components are required in the implementation. A more indepth analysis of the linear regulator will be given later. However, there are two main
drawbacks in using the linear regulator. Firstly, the output regulated voltage can only be
3
-
a stepped down voltage of the input supply. Hence, limiting its application in systems
with low input supply voltage, for example solar cells applications. Furthermore, the
linear regulator suffers from low conversion efficiency. In cases when the difference in
the input and output voltage is large or when the load current is significant, the power
loss in the pass element will be significant, thereby degrading its overall efficiency to a
large extent. For instance, in the case when the input supply voltage is 12V, the output
regulated voltage at 3.3V and the load current is 10mA, the power loss in the pass
transistor is 870mW. Assuming that the error amplifier and reference voltage consumes
a negligible amount of current, the overall efficiency of the linear regulator is only 27.5%.
In conclusion, the linear regulator is best suited in low current applications with small
differences between input and output regulated voltages.
Figure 1-2 shows the voltage profile of the output storage capacitor as energy is
harvested from the piezoelectric generator mounted on the shoes, rectified and stored in
the capacitor [2]. In this case, the researchers had implemented the system such that
when the voltage on output capacitor reaches 12V, the energy will be made available to
a linear regulator which generates a 5V output voltage to power the transmitter. This
requirement limits the rate in which data can be transmitted as a person will need to take
several steps in the shoes before enough energy is harvested and stored in the storage
capacitor.
Figure 1-3 shows the DC voltage generated by the piezoelectric-based wind energy
harvester [3] with different wind speed. It can be observed that the voltage generated
has a wide range and it can reach up to 8.8V as the wind speed reaches 6.7m/s. Again,
4
-
a linear regulator is used to generate a stable output voltage to power the system, hence
resulting in a non-operational system during low wind speed conditions.
1-2: Energy harvested from piezoelectric shoes on storage capacitor [2]
1-3: DC voltage generated by piezoelectric harvester with different wind speed [3]
5
-
The piezoelectric based energy harvesters have typically very low efficiency in
harvesting energy from the environment. Hence any energy harvested is precious. In
both systems, the overall system efficiency is degraded further by the choice of a linear
regulator to generate a stable supply as a large voltage drop (hence significant power
loss) can be observed across the pass element in some operating conditions.
However in applications such as [4], where a wireless biological monitoring system is
implemented, the linear regulator will limit its operations. In [4], a free-moving mouse
inside a cage is used for prototype monitoring system design. By employing an inductive
coupling network, a prototype implant device can wirelessly receive an input RF power
from an array of external coils. The received AC voltage is further rectified by a halfwave rectifier to supply DC current. Taking into consideration, the different possible
tilting angles and positions of the mouse, the rectified DC voltage measured ranges from
1.0V to 6.9V in the experiment. In this case, if the bio-implant system requires a 3.0V
operating supply voltage, a linear regulator will not be suitable to provide the regulated
voltage. Instead, a switch-mode dc-dc power converter with both step-up and step-down
capability is required for the application.
-
-
Switch-mode DC-DC power supplies typically have higher conversion efficiency as
compared to linear regulators in most operating conditions. There are numerous types of
switch-mode dc-dc converters, namely buck, boost and buck-boost converters. The
buck-boost converter is best suited for applications involving a wide input supply range,
since it is able to both step-up and step-down the input and provide a stable output
supply. Hence, by implementing a buck-boost converter in place of the linear regulators
6
-
used in the designs, operating conditions for both systems can be further extended, i.e.
the person wearing the energy harvesting shoes will be able to transmit data back to
base more frequently.
Majority of the buck-boost dc-dc converters developed generate a non-inverting
regulated output supply and are designed with a battery input in mind. This offers great
convenience to hardware developers, as the same input supply can be used to power
other subsystems on board. However these buck-boost converters can at most operate
at a minimum supply voltage of 1.8V, i.e. the wind energy harvester can only transmit
data when wind speed is faster than approximately 5m/s. Table 1-1 summarizes a few
dc-dc converters and their performance. It can be observed from the table that only the
boost converter can operate with a low supply voltage of 0.7V and chip manufacturers
have lowered the minimum supply required for the boost converters considerably over
the past few years. These boost converters are designed for ultra-low supply
applications such as those utilizing solar cells. On the other hand, the minimum
operating voltages for buck-boost converters remain relatively high with respect to that of
the boost architecture and they required at least 1.8V to operate. Hence these buckboost converters are not optimized to operate in a system powered by sustainable
energy sources. Furthermore sustainable energy sources have typically different
characteristics as compared to the battery supplies used in all portable devices. In most
cases, the outputs from the sustainable energy sources cannot be used directly to power
the system as they need to be further regulated. Therefore a buck-boost converter which
generates an inverting output may not pose too much of inconvenience to the system
designers.
7
-
In this project, a buck-boost converter catering to sustainable energy sources,
particularly for piezoelectric wind energy harvester will be designed. This buck-boost
converter is aimed to operate with a lower supply voltage, closer to the range achieved
in boost converters recently. Also, since applications utilizing sustainable energy sources
typically consume little power, the proposed chip will be designed to cater to a maximum
load of 25mA. Different architectures of the buck-boost converters will be examined in
the next chapter and the one which is most suited for this application will be probed
further. Subsequent chapters will cover the design of the sub-blocks in the startup and
regulatory control systems required in the proposed chip. Finally, in the last chapter, the
simulated performance of the buck-boost converter will be discussed.
[5]
[6]
- [7]
[8]
Type
Buck-Boost
Buck-Boost
Buck-Boost
Boost
Inverting/
Non-inverting
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Minimum VDD
2.5V
1.8V
2.7V
0.7V
Maximum VDD
3.2V
5.5V
10.0V
5.5V
Quiescent Current
Not Specified
16µA
86µA
5µA
Max Load Current
800mA
260mA
500mA
100mA
1-1: DC-DC converters summarized performance
8
-
CChhaapptteerr 22
Buck-Boost Converter Topologies
The buck-boost converter provides a solution to applications with wide input power
supply ranges by stepping up or down the input supply to generate a regulated supply
voltage. There are many buck-boost converter topologies [9], [10], [11] which have been
developed over the years. Each of these topologies has been designed to meet the
requirements for the different applications. In this chapter, some of these topologies will
be presented and their basic operations concepts will be discussed. Based on the
discussions and evaluations on the topologies presented, the one which best suits the
requirements of the proposed chip and applications will be chosen for implementation
-
2-1: Conventional Inverting Buck-Boost Converter [9]
9
One of the simplest buck-boost topology is that of the conventional inverting buck-boost
converter which is shown in figure 2-1. The setup is simple and requires the same
number of external components as a buck or a boost converter. It involves an inductor, a
capacitor, a MOS switch and a diode, which in actual implementation is replaced by a
MOS switch, so as to reduce the conduction loss. However, a major setback of this
topology, as its name implies, is that it provides an inverted output supply voltage. It can
be observed from figure 2-1 that the input voltage source is inverted so that the output
regulated voltage is positive. This implies that no other circuitries in the system will be
able to use the input voltage directly.
The basic operations of the conventional inverting buck-boost converter can be divided
into 2 modes, i.e. Continuous Conduction Mode (CCM) and Discontinuous Conduction
Mode (DCM), which is determined by the continuity of the inductor current.
Under steady state condition, i.e. when the output regulated voltage, Vout has settled
down to its desired level for a given load, when the switching transistor is turned on for a
duration ton,
Vdiode = −VS
(2.1)
The diode is reversed biased for a given positive output regulated voltage Vout and the
inductor increases linearly from IL,1 to IL,2 in time ton such that
VS = L
I L,2 − I L,1
ton
ton =
=
L∆I L
VS
L∆I L
ton
(2.2)
(2.3)
When the switching transistor is subsequently switched off at time t = ton for a duration of
T - ton, where T is the switching period, the voltage at Vdiode reverses in polarity so as to
keep the inductor current flowing. Hence if VS is positive, Vdiode will become positive
during this period, thereby forward biasing the diode and transferring the energy stored
in the inductor coil during ton, to the load. During this period, the inductor current falls
linearly from IL,2 to IL,1, since in steady state condition
− Vout = − L
I L,2 − I L,1
T − ton
=−
L∆I L
T − ton
(2.4)
Defining turn-on period ton to be DT, where D is the controlled duty ratio. Manipulating
equations (2.2) and (2.4), the output regulated voltage can be expressed as
Vout =
D
VS
1− D
(2.5)
Hence for a given input supply voltage VS, the turn-on duration of the switching transistor
can be controlled so as to obtain the desired output voltage. For example if the input
supply voltage is at 5V, D can be controlled to be 0.3333 so as to obtain an output
voltage of 2.5V. In this case, the converter is operating in the buck-mode, stepping down
the input voltage. It should be noted that the above derivations are made using the
assumptions that the converter is operating in ideal conditions and there is no power
losses. Hence the duty cycle D obtained in practical implementations will differ from that
obtained from (2.5).
Using an inductor of 4.7µH and output capacitor of 4.7µF (Note that the inductance and
capacitance values used for the ideal simulations performed in this chapter will be the
same, unless otherwise stated), the profiles observed at the various nodes of an ideal,
open-loop inverting buck-boost converter operating in the buck mode under CCM
operations (VS = 5.0V and Vout = 2.5V) are obtained as shown in figure 2-2.
V(
)
I(
I(
V(
)
)
)
V(
)
)
2-2: Ideal CCM operation of inverting buck-boost converter (VS=5.0V, Vout=2.5V)
Similarly, using equation (2.5), an input supply voltage VS of 1.0V can be boosted up to
an output voltage Vout of 2.5V by controlling D to be 0.714. Figure 2-3 shows the
simulation results when the ideal open-loop inverting buck-boost converter operates in
boost mode under CCM operations (VS = 1.0V and Vout = 2.5V). Using equations (2.2)
and (2.4) and assuming that the converter is lossless (ideal), the peak-to-peak inductor
current IL and peak-to-peak output ripple voltage can be derived
VS DT
L
(2.6)
I load DT
Co
(2.7)
∆I L =
∆Vout =
-
V(
)
V(
)
I(
)
I(
V(
)
)
)
2-3: Ideal CCM operation of inverting buck-boost converter (VS=1.0V, Vout=2.5V)
If the current flowing through the inductor decays to zero before the next switching cycle,
the buck-boost converter is said to be operating in discontinuous conduction mode
(DCM). This condition will occur when for a fixed inductor value, the output load
decreases to a certain value, i.e. Rload increases to a critical value Rcrit. The critical
resistance Rcrit can be derived by considering the boundary operating condition, i.e.
between continuous and discontinuous conduction mode. At this boundary condition, the
average inductor current is given by
IL =
I L, peak
2
=
VS ton VS DT
=
2L
2L
(2.8)
And since the input current ISupply is equal to the inductor current during the ton duration,
and zero during toff period, i.e. when the switching transistor is switched off, the average
input current is given by
-
ISupply =
I L, peak DT
2T
VS D 2T
=
2L
(2.9)
Assuming an ideal buck-boost converter with input power equal to output power
2
VS I Supply
2
V
V D 2T
= out = S
Rcrit
2L
(2.10)
At this boundary condition, equation (2.5) still applies and using (2.5) in (2.10), the
critical resistance Rcrit can be derived
Rcrit =
2L
(1 − D )2 T
(2.11)
And from (2.10), the open loop relationship between VS and Vout under DCM condition is
Vout =
( )
R D 2T
VS
2L
(2.12)
Using equations (2.11), the critical resistance Rcrit required to force the converter into
DCM operation can be calculated. Using the same simulation circuits used to obtain
results shown in figures 2-2 and 2-3, but changing the load resistance to a value larger
than Rcrit and applying the duty ratio D obtained from (2.12) to the switching transistor,
simulation results illustrating the DCM operation of the inverting buck-boost converter (in
both buck and boost mode) are presented in figures 2-4 and 2-5. It can be observed
from the simulation results that the inductor current decays to zero before the next
switching cycle. In the actual implementation of this topology, the diode in figure 2-1 will
be replaced by a transistor. However, the transistor will experience a large voltage
across its drain and source terminals during the ton period. Hence an appropriate
transistor with suitable device rating should be used.
-
V(
)
V(
)
I(
)
I(
)
V(
)
)
2-4: Ideal DCM operation of inverting buck-boost converter (VS=5.0V, Vout=2.5V)
V(
)
V(
)
I(
I(
)
)
V(
)
)
2-5: Ideal DCM operation of inverting buck-boost converter (VS=1.0V, Vout=2.5V)
4-
-
-
2-6: 4-Switches Non-Inverting Buck-Boost Converter [9]
A conventional 4-switches non-inverting buck-boost converter is shown in figure 2-6. The
two switching transistors shown in the schematic will be turned on and off at the same
time. When the switches are off, the diodes will keep the inductor current flowing and
thereby transferring the energy stored in the coil during the on period to the load. As
compared to the conventional inverting buck-boost converter, this converter requires 4
switching transistors instead of 2 in the former case (if all the diodes are replaced with
transistors so as to allow synchronous rectification). This implies that the buck-boost
converter to be designed will need to have 4 pre-drivers for the switching transistors and
with 4 transistors to be turned on and off simultaneously, switching losses can be
substantial during low load condition. The advantage of this topology is that the output is
not inverted hence there is no need to invert the input source which is the problem of the
conventional inverting topology. Also, the maximum voltage across any of the transistors
will be only slightly higher than the input voltage VS as compared to VS + Vout in the
previous topology. The basic operations of the conventional 4-switches non-inverting
converter can also be divided into two modes CCM and DCM.
The operations of this converter are similar to the conventional inverting buck-boost
converter. Under steady state condition, when the 2 switching transistors are turned on
for a duration ton (assuming that the on resistance of the transistors is zero),
Vdiode,1 = VS
Vdiode,2 = 0
(2.13)
The 2 diodes are reversed biased for a given positive output regulated voltage Vout and
the inductor current increases linearly from IL,1 to IL,2 in time ton with a relationship
identical to that expressed in (2.2) and (2.3)
VS = L
I L,2 − I L,1 L∆I L
=
ton
ton
(2.14)
L∆I L
VS
(2.15)
t on =
When the switching transistors are subsequently switched off, the inductor current freewheels through the 2 diodes and the stored energy in the inductor is thereby transferred
to the load. In this case, assuming that the diodes are ideal, i.e. zero voltage drop,
Vdiode,1 will drop to zero while Vdiode,2 will be at same potential as Vout. During this period,
the inductor current falls linearly from IL,2 to IL,1, similar to (2.4)
− Vout = L
I L,1 − I L,2
T − t on
=−
L∆I L
T − t on
(2.16)
Defining turn-on period ton to be DT, where D is the controlled duty ratio. Manipulating
equations (2.14) and (2.16), the output regulated voltage can be expressed as
Vout =
D
VS
1− D
(2.17)
Notice that the output regulated voltage to input voltage conversion ratio is identical to
that of the conventional inverting buck-boost converter. Using (2.17), the duty ratio D
required to be applied to the switching transistors for an output voltage of 2.5V with input
supply voltage of 3.3V, 2.5V and 1.0V can be calculated. Using these figures, the ideal
open-loop transient response of this converter under steady state condition can be
simulated as shown in figures 2-7, 2-8 and 2-9. Hence this converter is able to
seamlessly regulate the output voltage for a wide range of input supply voltage, without
any extra circuitry to reconfigure the converter for each given input supply voltage VS.
V(
)
V(
)
I(
)
I(
V(
)
)
)
V(
)
2-7: Ideal CCM operation of 4-switches converter (VS=3.3V, Vout=2.5V)
-
2-8: Ideal CCM operation of 4-switches converter (VS=2.5V, Vout=2.5V)
V(
)
V(
)
I(
I(
V(
)
)
)
)
V(
)
2-9: Ideal CCM operation of 4-switches converter (VS=1.0V, Vout=2.5V)
-
During DCM operation, the voltage across the inductor is VS when the switching
transistors are turned on and –Vout when they are off which are identical to that of the
inverting buck-boost converter. Hence, the derivation of the critical load resistance Rcrit
and also the conversion ratio during DCM operation is similar to that performed earlier in
the previous section. The critical resistance Rcrit and conversion ratio is identical to that
provided in (2.11) and (2.12) and is provided below for convenience
Rcrit =
Vout =
2L
(1 − D )2 T
( )
R D 2T
VS
2L
(2.18)
(2.19)
Note that the duty ratio D term in (2.18) refers to the duty ratio D to be applied to the
switching transistors under CCM condition. To force the converter to enter DCM
operation, a load resistance larger than Rcrit must be used and to obtain an output
voltage of 2.5V, the required duty ratio D applied to the transistors for the different VS
can be calculated using (2.19). Figures 2-10, 2-11 and 2-12 show the ideal open-loop
transient response of this converter under steady state DCM condition for different input
supply voltage, VS of 3.3V, 2.5V and 1.0V respectively. It can be observed from the
simulation results that the inductor current decays to zero before the next switching cycle,
thereby depicting that the converter is operating in DCM condition. And using the duty
ratio D derived, the output of the converter is verified to be around 2.5V, hence
confirming the validity of (2.19). However, if the power losses incurred in practical
implementation of the converter are to be considered, the duty ratio D is expected to be
slightly more than that predicted in (2.19).
-
V(
)
V(
)
I(
)
I(
V(
)
)
)
V(
2-
)
: Ideal DCM operation of 4-switches converter (VS=3.3V, Vout=2.5V)
V(
)
V(
)
I(
)
I(
V(
)
)
)
V(
2-
)
: Ideal DCM operation of 4-switches converter (VS=2.5V, Vout=2.5V)
-
V(
)
V(
)
I(
)
I(
V(
)
)
)
V(
2-
)
: Ideal DCM operation of 4-switches converter (VS=1.0V, Vout=2.5V)
-
-
-
As mentioned earlier, the conventional 4-switches non-inverting buck-boost converter
involves switching 4 power transistors, i.e. two diodes are replaced by transistors to
reduce conduction losses. However, this will result in substantial power losses when the
converter is operating in low load condition since large switching losses will be incurred
through the process of charging and discharging large gate capacitances as the
transistors are turned on and off. Hence, in most recent buck-boost converter
implemented in commercial designs, extra control circuitries, sensing the input supply
voltage or error amplifier output, are included to configure the converter shown in figure
2-6 into a buck or boost configuration, thereby switching only 2 transistors instead of 4.
These configurations will only kick in when the input supply voltage is substantially lower
or higher than the regulated output voltage.
-
In the case when the input supply VS is much higher than the output voltage Vout, the
converter will be configured into the buck mode, as shown in figure 2-13. In this case,
the NMOS switching transistor is always turned off while the PMOS is switched at a duty
ratio D. Notice that the reconfigured buck-boost converter in buck mode is identical to a
standard buck converter except for an extra diode (transistor) from the inductor to the
load. If the diodes are implemented using transistors, this extra diode will always be on
thereby making the implementation in figure 2-13 similar to a buck converter. In this case,
only 2 out of the 4 transistors will be switched on and off during the operations of the
converter. Hence the switching losses will be reduced by approximately half as
compared to the previous topology.
2-
: 4-switches non-inverting buck-boost converter in buck configuration [9]
The basic operations of the modified 4-switches non-inverting converter when configured
in the implementation shown in figure 2-13 can be divided into CCM and DCM modes.
Under steady state condition, when the switching transistor is turned on for a duration ton
(assuming that the on resistance of the transistors and diodes is zero), the voltage
across the inductor L is VS – Vout, with the voltage at node Vdiode,2 at the same potential
as the output voltage Vout. Hence the inductor current increases linearly from IL,1 to IL,2 in
time ton and it can be expressed as
VS − Vout = L
t on =
I L,2 − I L,1 L∆I L
=
ton
ton
(2.20)
L∆I L
VS − Vout
(2.21)
When the switching PMOS is subsequently switched off, the stored energy in the
inductor is transferred to the load through the 2 diodes. In this case, assuming that the
diodes are ideal, i.e. zero voltage drop, Vdiode,1 will drop to zero while Vdiode,2 will be at
same potential as Vout. During this period, the inductor current falls linearly from IL,2 to IL,1
and this can be expressed in the form
− Vout = L
I L,1 − I L,2
T − t on
=−
L∆I L
T − t on
(2.22)
Defining turn-on period ton to be DT, where D is the controlled duty ratio. Manipulating
equations (2.21) and (2.22), the output regulated voltage can be expressed as:
Vout = DVS
(2.23)
Notice that the output regulated voltage to input voltage conversion ratio is identical to
that of the conventional buck converter in CCM operation. Hence to obtain an output
voltage of 2.5V from an input supply voltage of 3.3V, the ideal duty ratio to be applied
can be calculated from (2.23) and this works out to 0.7575. Using this value, the
modified 4-switches non-inverting converter in the configuration shown in figure 2-13 is
simulated. The ideal open-loop CCM transient response obtained is shown in figure 2-14.
V(
)
V(
)
I(
I(
)
)
I(
V(
)
)
)
V(
2-
)
: Ideal CCM operation of modified 4-switches converter (VS=3.3V, Vout=2.5V)
Since the converter in buck-mode configuration bears resemblance to a conventional
buck converter, the critical resistance Rcrit and the conversion ratio in either case are
similar. And they can be expressed as
-
Rcrit =
2L
(1 − D )T
(2.24)
where DT is the turn-on period for the power PMOS and L is the inductance of inductor.
Vout =
2
8LT
1+ 1+
2
RD
VS
(2.25)
Using a load resistance larger than Rcrit given in (2.24) and applying a switching signal of
duty ratio D given in (2.25) for a given input supply voltage VS and output voltage Vout,
the open-loop transient response for an ideal buck-mode configured converter operating
in DCM for VS = 3.3V and Vout = 2.5V is shown in figure 2-15.
V(
)
V(
)
I(
I(
)
)
I(
V(
)
)
)
V(
2-
)
: Ideal DCM operation of modified 4-switches converter (VS=3.3V, Vout=2.5V)
-
In the case when the input supply VS is much smaller than the output voltage Vout, the
converter will be configured into the boost mode, as shown in figure 2-16.
2-
: 4-switches non-inverting buck-boost converter in boost configuration [9]
In this case, the PMOS switching transistor is always turned on while the NMOS is
switched at a duty ratio D. Notice that the reconfigured buck-boost converter in boost
mode is identical to a standard boost converter. In this case, diode1 does not come into
operation at all and is always reversed biased while current will always flow through the
PMOS, hence the turn-on resistance of the PMOS should be small so as to reduce on
the conduction loss.
The basic operations of the conventional 4-switches non-inverting converter in the boost
configuration can be divided into two modes CCM and DCM. Since the converter in this
mode operates in the same way as an ideal boost converter and also since the voltage
conversion ratio for both modes for conventional boost converter has been welldocumented in many references, the derivation will not be provided here. Instead, the
results will be summarized below.
The voltage conversion ratio during CCM operation for the converter in boost
configuration can be expressed as
Vout =
1
VS
1− D
(2.26)
Note that although a duty ratio of 1 will theoretically give an infinite output, however,
losses within the circuit will restrict the maximum output voltage which the converter can
generate. Using (2.26), the duty ratio D to be applied for a converter with input supply VS
of 1.0V to obtain 2.5V can be derived. The open-loop steady-state transient response of
the converter in boost configuration under CCM operation is shown in figure 2-17.
The voltage conversion ratio during DCM operation for the converter in boost
configuration (voltage-mode) can be expressed as
Vout
2 D 2 RT
1 + 1 +
L
=
VS
2
where R in the above equation (2.27) much be larger than Rcrit, so as to force the
converter to operate in the discontinuous conduction mode.
(2.27)
-
V(
)
V(
)
I(
)
I(
)
I(
V(
)
)
)
V(
2-
)
: Ideal CCM operation of modified 4-switches converter (VS=1.0V, Vout=2.5V)
Using the CCM/DCM boundary conditions, the critical load resistance Rcrit can be
derived using the same methods presented earlier. Rcrit can be written as
Rcrit =
2L
D(1 − D ) T
2
(2.28)
where D is the duty ratio obtained from (2.26).
Hence using (2.27), the duty ratio D for a converter operating in DCM condition, with
input supply VS of 1.0V, output Vout of 2.5V can be derived. The open-loop steady-state
transient response of the converter in boost configuration under DCM operation is
obtained through simulation and is presented in figure 2-18.
-
V(
)
V(
)
I(
I(
)
)
I(
V(
)
)
)
V(
2-
)
: Ideal DCM operation of modified 4-switches converter (VS=1.0V, Vout=2.5V)
When the input supply voltage VS is close to the potential of the output voltage Vout, the
control circuitries should configure the converter in the buck-boost mode. There are a
number of control schemes available which aims to regulate the output voltage at a level
close to the input voltage. However, many of these are patented. One possible way or
method to regulate the output voltage when input voltage level is close to it , is to switch
the 4 transistors together as in the case of the 4-switches conventional non-inverting
converter as mentioned earlier. However in doing so, the switching losses of the
converter operating under this mode will substantially increase, resulting in a dip in
overall conversion efficiency.
Hence by introducing extra sensing and control circuitries, which sense the input voltage
VS and configure the converter accordingly, the modified 4-switches non-inverting
converter is able to regulate the output at a fixed voltage over a wide input voltage range.
The advantage of this is that it minimizes the switching loss as compared to the
conventional 4-switches converter when operating in buck or boost mode, resulting in an
improvement in the overall conversion efficiency. This can be extended to the buckboost mode operation, if a more efficient control strategy is designed.
It is important to have a low turn-on resistance for the transistors (for low conduction loss)
in this case as some of them are always on in certain configuration. Notice that the
maximum voltage across any transistor is the same as the case of the conventional 4switches buck-boost converter, i.e. slightly greater than VS and again 4 pre-drivers are
required in this case. However since it minimizes the switching loss, which makes the
converter more efficient during light load condition, many of the recent buck-boost
converters adopt this topology but use proprietary control methods to handle buck-boost
mode operations.
The last of the buck-boost topology which will be discussed in this paper is the Cuk
inverting buck-boost converter. The Cuk converter inverts the output from the input
supply similar to the conventional inverting buck-boost converter mentioned earlier but it
has been shown to be more efficient when compared to the conventional buck-boost
converter. However, the Cuk converter requires more external components, i.e. 2
inductors and 2 capacitors for its operation which is double the external components for
the other 3 topologies. Since it is important to reduce on the on-board components, so
as to be more cost and space-effective, this topology is the least preferred for the
implementation for the proposed converter. Nevertheless it will be described briefly here
so as to complete this discussion. Figure 2-19 shows a typical Cuk buck-boost converter.
2-
: Inverting Cuk Buck-Boost Converter [9]
Under steady state condition, when the switching transistor is turned on for duration of
ton (assuming that the on resistance of the transistors is zero), the current flowing
through the input inductor Li increases according to the following expression
VS = Li
I Li,2 − I Li,1 Li ∆I Li
=
ton
ton
(2.29)
Li ∆I Li
VS
(2.30)
t on =
At the same time, the capacitor Ct transfers its stored energy to the output inductor Lo as
well as the load. The diode during this period is reversed biased. Hence the current
flowing through the output inductor Lo rises linearly according to
-
Vct − Vout = Lo
t on =
I Lo,2 − I Lo,1 Lo ∆I Lo
=
ton
ton
Lo ∆I Lo
Vct − Vout
(2.31)
(2.32)
When the switching transistor is turned off at time ton, the voltage across the input
inductor reverses in polarity in order to maintain its current uninterrupted and the diode
becomes forward-biased. The energy transfer capacitor Ct is then charged by the input
source VS and the stored energy in the input inductor. In this case, the current flowing
through the input inductor Li decreases according to the following expression
VS − Vct = Li
I Li,1 − I Li,2 − Li ∆I Li
=
T − ton
T − ton
T − t on =
Li ∆I Li
Vct − VS
(2.33)
(2.34)
At the same time, the load current is supplied by the stored energy in the output inductor
and the capacitor. The current flowing through the output inductor decreases linearly
according to
− Vout = Lo
I Lo,1 − I Lo,2
L ∆I
= − o Lo
T − ton
T − ton
T − t on =
Lo ∆I Lo
Vout
(2.35)
(2.36)
The peak-to-peak input inductor current can be obtained from (2.30) and (2.34) (defining
ton to be DT, where D is the duty ratio)
-
VS DT (1 − D )T (Vct − VS )
=
Li
Li
∆I Li =
Vct =
VS
1− D
(2.37)
(2.38)
The peak-to-peak output inductor current can be obtained from (2.32) and (2.36)
(Vct − Vout )DT = (1 − D )TVout
∆I Lo =
Lo
Vct =
Lo
Vout
D
(2.39)
(2.40)
Hence from (2.38) and (2.40), the conversion ratio of the Cuk buck-boost converter in
CCM operation can be expressed as:
Vout =
D
VS
1− D
(2.41)
Therefore, the Cuk buck-boost converter has the same output to input conversion ratio
as the conventional inverting buck-boost converter as well as the conventional 4switches buck-boost converter.
Each of the four different buck-boost converter topologies discussed has its advantages
and disadvantages. The conventional inverting buck-boost converter is simple and
requires minimal external components as well as only 2 switching transistors. It also
provides through its transfer function, a seamless transition from buck to boost mode
and vice versa, without the need for additional sensing circuitries. But the output is
inverted from the input. Hence this topology is not feasible if the input supply is to be
shared with other systems in the application. On the other hand, the 4-switches
approach presented in the second and third topologies requires more switching
transistors / pre-drivers and complex control systems. But it gives a non-inverting output,
which means that other circuitries on the system can still use the input supply. The
characteristics of each of the four topologies are summarized in the table below:
-
-
4-
4-
Inverting
Non-Inverting
Non-Inverting
Inverting
1
1
1
2
1
1
1
2
2
4
4
2
2
4
4
2
1
2
2
1
N
N
Y
N
Mode of operation:
Buck ~ D
D
1− D
D
1− D
1
1− D
D
Buck-Boost ~
1− D
Boost ~
D
1− D
2-1: Buck-boost converter topologies summarized characteristics
Recent publications [12], [13] on buck-boost converters concentrate on the development
of Single Inductor Dual Buck-Boost Output (SIDBBO) converters, a variant of the
conventional 4-switches converters. These converters allow the regulation of two outputs
and in [12] it allows the charging of Li-Ion batteries under light load conditions using a
single fuel cell while the Li-Ion batteries and the fuel cell both supply the charges
required in heavy load conditions. However due to the limitation of the 4-switches
converters, these SIDBBO converters are only operational over a narrow supply range,
i.e. 2.7V - 4.2V in [12] and 2V - 5V in [13], making them unsuitable for applications with a
wider input supply range such as the inductive coupling RF power used for biological
monitoring in [4]. Recent developments in the boost converters [14] have exhibited the
capabilities of these converters to operate to voltages as low as 20mV under steadystate operations so as to cater to thermoelectric energy-harvesting needs. However the
design only allows stepping up of the input voltage and supplies very low load current. In
this project, a buck-boost converter which extends the recent concepts used in boost
converters is implemented. It is able to provide a single regulated supply over a wide
input supply range thereby meeting the needs of applications such as the inductively
powered biological system. The concept used can be further extended to SIDBBO
converters so as to extend the operating voltages of the converters in [12] and [13].
-
r
Figure 2-20 shows the block diagram of the proposed buck-boost converter. The simple,
conventional inverting buck-boost converter topology is adopted for the proposed design.
This topology requires only two power switches which greatly reduce on the silicon area
required for the buck-boost converter. And since the converter is proposed for low-power
application, its quiescent current consumption will be a concern and by eliminating the
complex control circuitries required in 4-switches topologies, the power consumption of
the proposed design can be further minimized. In addition, the minimum input supply
voltage of the 4-switches topologies will be at least a threshold voltage of a PMOS
transistor, i.e. 0.8V required to turn on and off the power PMOS transistors used. Even
then, the high on-resistance of the power PMOS will degrade the efficiency of the
converter considerably. The conventional inverting buck-boost converter does not have
such a problem but it does have a major disadvantage of generating an inverting output.
2-
: Proposed Inverting Buck-Boost Converter Block Diagram
It can be observed from figure 2-20 that the different circuit blocks within the buck-boost
converter operate under different power supplies, as indicated through different color
coding and markings in the diagram. Some of the power supplies indicated, i.e.
VSS_V33_INT and VSS_V33_EXT are internally generated using the two internal regulators.
These two regulators limit and protect the circuit blocks powering off these supply rails
from potentially high input supply voltage which will damage the low-voltage devices
used in these blocks. The proposed chip also incorporates a power management system
which is designed to operate using a single or two AA batteries supply connected at V33
when the converter is disabled. In this mode, the external LDO is designed to generate a
1.0V supply. Hence the circuits which are to be operational under this mode, such as the
low-dropout regulator and bandgap reference are to function even when their supplies
fall to 1.2V.
During power up of the chip, the startup circuitries which namely consist of internal
regulator 2, startup current-starved ring oscillator, startup adaptive on-time generator
and pre-driver 1A will kick-start the operations of the buck-boost converter. The main
and only objective of these circuit blocks at this moment is to boost the output V33
beyond its under-voltage threshold level determined by the under-voltage (UV)
comparator. Internal regulator 2 will generate an internal supply VSS_V33_INT which is
limited to below 3.6V above VPSUB from the input supply VS. This internal supply rail is
then used to power the startup circuitries as shown in figure 2-20. The ring oscillator and
adaptive on-time generator limits the inductor current peak by controlling the on-time of
the power NMOS. The on-time is limited by the duration when the oscillator output is
high if input supply is low, i.e. below 1.5V. If the input supply is higher than 1.5V, the ontime of the power NMOS is controlled by the adaptive on-time generator. Once the ontime generator output goes high or when oscillator output goes low (whichever comes
earlier), the power NMOS is switched off and the inductor current starts to decay as it
charges the output through the external schottky diode. The next charging cycle, i.e
when the power NMOS is turned on again is initiated when oscillator output goes high.
Pre-driver 1A will drive the gate of power NMOS based on the outputs of the oscillator
and on-time generator. This process continues as the output voltage V33 gets boosted
until it reaches the UV threshold as determined by the UV comparator. From this point
onwards, the regulatory circuits powered by V33, indicated in figure 2-20, takes over the
control of the converter. The startup circuitries will subsequently be disabled since they
are no longer required during the regulatory operations. This serves to reduce the overall
quiescent current consumption of the converter while regulating.
When UV comparator output goes low, the buck-boost converter enters regulatory
operation. In this case, internal regulator 1 generates an internal supply VSS_V33_EXT
(approximately 3.4V above VPSUB) from output V33. The internal regulator uses a
reference voltage derived from the bandgap reference and level-shifted with respect to
substrate, VPSUB to generate this internal supply. This is used by pre-driver 1B to drive
the gate of power NMOS. Upon detection by the regulatory comparator that the output
V33 has fallen below a threshold determined using the external resistive feedback of
V33 and the internal bandgap reference voltage, a new charging cycle will be initiated by
first turning on the power NMOS. The output of the regulatory comparator which is either
0 or V33 is translated to VPSUB or VSS_V33_EXT respectively using the level-shifter. The
translated signal is then used to control pre-driver 1B to switch on the power NMOS. The
adaptive on-time generator which includes a sense amplifier senses the input supply
VPSUB. And depending on the resistance of an external resistor, the generator determines
the on-time of the power NMOS, limiting the inductor current peak during this charging
cycle.
After the adaptive generator output goes high and turns off the power NMOS, the power
PMOS is turned on. During this time, the inductor current flows through the power PMOS
while boosting output V33 to above the threshold level. Once V33 rises above the predetermined level, the regulatory comparator output goes low. As the inductor current
continues to decay, the anti-backflow comparator senses the potential across the power
PMOS and switches off the PMOS once the inductor current decays and changes
direction, i.e charges from output V33 backflows to the inductor. The output of the antibackflow comparator is used to control pre-driver 2 which is used to drive the gate of the
synchronous power PMOS. Upon the switching off of the PMOS transistor, the current
charging cycle ends and the buck-boost converter remains in standby since V33 is
above the threshold. A new charging cycle will again commence when V33 is detected
to low by the regulatory comparator.
The preceding paragraphs describes the overall operations of the proposed buck-boost
converter from startup to regulation and how each circuit block functions in the overall
architecture in each of the different operation phases. Table 2-2 summarizes the roles
and functionalities of each of the circuit blocks shown in figure 2-20. The design
considerations and implementations for each of the sub-blocks will be discussed in detail
in the subsequent chapters.
-
Regulatory Circuitries
Startup Circuitries
2-2: Buck-boost converter circuit blocks roles & functionalities (Summarized)
Internal Regulator 2
Yes
Generates a regulated internal supply VSS_V33_INT for startup
circuitries, including adaptive startup on-time generator,
current starved ring oscillator, SR flip-flop and pre-driver 1A
Pre-Driver 1A
Yes
Drives the gate of power NMOS during startup operations
Yes
Together with the current-starved ring oscillator, limits the
inductor current peak by controlling the on-time of power
NMOS during startup. Designed to take control of power
NMOS on-time when input supply is higher than 1.5V
Current-Starved Ring
Oscillator
Yes
Controls the power NMOS on-time through the duration when
oscillator is ‘high’ and when input is lower than 1.5V. When
oscillator is ‘low’, inductor charges are transferred and boosted
the output through external schottky diode
Internal Regulator 1
No
Generates a regulated internal supply VSS_V33_EXT, about 3.4V
with respect to VPSUB from the buck-boost converter output
V33. Used by logic level shifters and pre-driver 1B.
Logic Level Shifters
No
Translates logic signals toggling between 0 & V33 to signal
controlling pre-driver 1B toggling between VPSUB & VSS_V33_EXT
Pre-Driver 1B
No
Drives the gate of power NMOS during regulatory operations
Input Sensing Amplifier &
Adaptive On-Time
Generator
No
Senses the input supply voltage level and adjusts the on-time
of power NMOS so as to maintain a relatively constant
inductor current peak over the wide input range.
Bandgap Reference
No
Generates a process, temperature independent reference.
Used by UV comparator, regulatory comparator, internal
regulator 1, external LDO and adaptive on-time generator
No
Detects if output V33 is above or below under-voltage
threshold, determined through external resistor feedback.
Comparator output used to determine if converter is in startup
or regulatory mode
Regulatory Comparator
No
Detects the converter output V33 through an external resistor
network. Triggers a new charging cycle by turning on the
power NMOS for a duration determined by adaptive on-time
generator once V33 is detected to have dropped below the
threshold set through the external resistor feedback
Anti-Backflow Control
System
No
Supports synchronous operations of the converter by
adaptively adjusting the on-time of power PMOS through
information gathered during each charging cycle
Pre-Driver 2
No
Drives the gate of power PMOS for synchronous operations
External LDO
No
Generates a regulated supply of 1.0V (configurable through
external resistors) from the buck-boost converter output
Adaptive Startup Ton
Generator
UV Comparator
-
CChhaapptteerr 33
Bandgap Reference
Reference voltage generators are essential blocks in most analog and mixed signal
devices. They generate a stable reference voltage despite any process, supply and
temperature variations which may occur. This reference is critical especially in a power
management IC as they effectively affect the performance of the chip. The bandgap
reference is the most popular reference voltage generator that can fulfill the needs. Over
the years, numerous variants of the traditional bandgap reference had been developed
and they have been able to address all requirements successfully. However, as the
supply voltage and power requirements scale down drastically in recent years, changes
have to be made on these designs so as to meet the ever changing specifications.
In order to generate a reference voltage which displays little variation with temperature,
two quantities with opposite temperature coefficients can be added with proper weighting
so that the result displays a zero temperature coefficient. In most bandgap reference
generators, the two quantities used are namely the base-emitter voltage VBE of a bipolar
device and the difference between two VBE of two BJTs with different current densities.
The collector current for a bipolar device can be written as
V BE = VT ln(I C I S )
(3.1)
-
where VT = kT q and taking into account the temperature dependence of the saturation
current IS, and assuming that the collector current has no temperature dependence, the
temperature coefficient of the base-emitter voltage VBE can be derived as shown in [15],
[16] and reproduced below for convenience.
Eg
VBE − (4 + m )VT − E g q
V
∂VBE VT I C
=
ln − (4 + m ) T − 2 VT =
T IS
T kT
∂T
T
(3.2)
It can be observed from (3.2) that the temperature coefficient of the base-emitter voltage
itself depends on the temperature and the base-emitter voltage. And for a given baseemitter voltage and temperature, the temperature coefficient can be calculated.
The positive temperature coefficient quantity required to generate the temperature
independent reference is obtained from the difference of base-emitter voltages of 2
bipolar transistors biased with different current density. For instance, if two identical
bipolar transistors are biased such that one conducts n times more collector current as
compared to the other, then the base-emitter voltage difference can be written as
∆VBE = VBE1 − VBE 2 = VT ln(n I C I S ) − VT ln(I C I S ) = VT ln(n ) = kT q ln(n )
(3.3)
Hence it can be concluded from (3.3), that the base-emitter voltage difference is directly
proportional to the absolute temperature and its temperature coefficient is given by
∂∆VBE k
= ln(n )
∂T
q
(3.4)
Hence, adding the two quantities with opposite temperature coefficients using proper
weighting, a reference voltage which possesses minimal variation with temperature can
-
be derived. One popular circuit implementation for the bandgap reference using a
normal CMOS process is shown in figure 3.1.
3-1: Traditional bandgap reference circuit implementation
In this circuit implementation, resistors R1 and R2 are chosen to be equal. Assuming that
the amplifier has infinite gain and zero offset, virtual short at the amplifier inputs will
result in nodes X and Y to settle down to approximately same voltage. Therefore the
current Io flowing through the two branches are equal. Applying KVL around the loop
involving the virtual short and assuming minimal base current, such that I E = I C
VBE1 = VBE 2 + I o R3 ⇒ VBE1 − VBE 2 = I o R3 ⇒ I o = VT ln(n ) R3
(3.5)
And using (3.5) the reference voltage at the output of the amplifier can be derived.
Vout = VBE 2 + I o (R2 + R3 ) = VBE 2 + (R2 + R3 )VT ln(n ) / R3
(3.6)
Hence it can be deduced from (3.6) that by using this circuit implementation, the two
quantities with opposite temperature coefficients are added and by choosing appropriate
-
sizing for resistors R2 and R3, a reference voltage with a zero temperature coefficient at
a particular temperature can be achieved, i.e.
∂Vout ∂VBE 2 (R2 + R3 )k ln(n )
=
+
qR3
∂T
∂T
(3.7)
And using (3.2), it can be derived that at an absolute temperature of 300K and assuming
that VBE ≈ 750mV , then
∂VBE VBE − (4 + m )VT − E g q 0.75 − (4 − 1.5)26mV − 1.12
=
≈
≈ −1.5 mV K
∂T
300
T
(3.8)
Hence in order to have a zero temperature coefficient at room temperature of 300K,
assuming that in this case, n = 8,
∂VBE 2 (R2 + R3 )k ln(n )
R
R
0.0015(300)
+
= 0 ⇒ 1+ 2 =
≈ 8.323 ⇒ 2 = 7.323
∂T
qR3
R3
R3
0.026(ln 8)
(3.9)
Substituting (3.9) into (3.6),
Vout = VBE 2 + (R2 + R3 )VT ln(n ) / R3 ≈ 0.75 + 8.323(0.026)(ln 8) ≈ 1.1999V ≈ 1.2V
(3.10)
This explains why traditional bandgap reference output has a value of approximately
1.2V. However, this implies that the reference circuit will require a supply voltage which
is higher than 1.2V in order to be functional. Examining the circuit implementation shown
in figure 3-1, it can be observed that the output stage of the amplifier requires a supply
voltage of at least 1.2V + VDSAT which is approximately 1.4V. If the input stage of the
amplifier is to be considered, the supply voltage required might be even higher. Although
the transistors in the amplifier can be biased in the subthreshold region so as to further
-
reduce the required headroom, this often results in greater mismatch and therefore
larger variation in the output reference. Hence traditional bandgap reference is not
suitable for low voltage applications.
As mentioned earlier, the proposed chip is supposed to operate in 2 different modes, i.e.
whether the buck-boost converter is enabled or disabled. In these 2 modes, the chip is to
operate under 2 different supply voltage ranges. In the case when the buck-boost
converter is disabled (BB_En = “0”), the proposed chip is to operate with a single/ double
AA battery supply voltage source which can go as low as 1.2V. The power management
system is to generate a 1.0V supply through a low dropout linear regulator and the
bandgap reference is to generate a stable reference voltage of approximately 250mV for
the LDO regulator. Under the conditions when the buck-boost converter is enabled
(BB_En = “1”), the bandgap output serves as a reference for both the LDO regulator as
well as the buck-boost converter. The bandgap reference powers off the regulated
supply rail generated by the buck-boost converter which can be between 2.2V and 3.3V.
In this case, the bandgap reference voltage will step up to approximately 660mV so as to
utilize the increased supply range available.
From the design specifications, it can be concluded that implementing a traditional
bandgap reference presented in the previous section is not feasible for the proposed
chip, since it requires a supply voltage much higher than its 1.2V reference output.
Instead, a bandgap reference which is able to cater to the low supply voltage
requirements is to be implemented in the proposed chip. Numerous designs have been
developed over the years to address the issue of high supply voltage required for the
-
traditional bandgap. In the next section, one of these designs will be discussed and
implemented.
3
As mentioned earlier, the output voltage generated by the traditional bandgap reference
circuit can be written as
Vout = VBE + nVT
(3.11)
This works out to be approximately 1.2V, making the traditional bandgap reference
implementation infeasible for low-voltage applications. In [17], it is proposed that a
fraction of the traditional bandgap voltage be obtained by scaling both terms of (3.11),
using current terms proportional to VBE and VT. Subsequently, these currents are suitably
added and converted into a voltage via a resistor. The temperature dependence of the
resistor must be taken into consideration during the implementation. Figure 3-2 shows
the schematic of a circuit [17] which implements the above-mentioned concept.
3-2: Schematic of low-supply voltage bandgap core circuit [17]
-
The operational amplifier forces the voltages at the two nodes VA and VB to be equal and
given that the sizing for transistors M1 and M2 are chosen to be equal, the current
flowing through the two diode-connected BJTs with emitter area ratio N will be equal.
Hence applying KVL around the loop involving both VA and VB, it can be derived that
VBE1 − VBE 2 = IR0 ⇒ I =
∆VBE VT ln(N )
=
R0
R0
(3.12)
Therefore the current flowing through the bipolar transistors is PTAT and since
VA = VB = VBE1
(3.13)
The current flowing through transistors M1 and M2 can be written as
I1 = I 2 =
VBE1 VT ln(N )
+
R1
R0
(3.14)
And assuming that transistor M3 has the same aspect ratio as M1 and M2, the output
reference voltage generated is given by
Vref = I1R3 =
R3
V R ln(N )
VBE1 + T 1
R1
R0
(3.15)
It can be observed from (3.15) that the term in parenthesis bears resemblance to (3.11)
and it contains terms which have opposite temperature coefficients. And by choosing
appropriate values of N and of the R1/R0 ratio, the temperature coefficients of VT and
VBE1 can be compensated. As a result, the voltage term within the parenthesis is close to
1.2V and the resistance ratio R3/R1 provides the necessary scaling so that the circuit is
able to operate with a supply voltage lower than 1.2V. This can only be achieved if the
temperature coefficients for the resistors are similar. Hence the resistors used in the
design must be of the same type and matching between the resistors and also the
-
current-mirroring transistors is critical to ensure the accuracy of the reference output
voltage. As such, the transistors M1, M2 and M3 are designed to operate in the
saturation region rather than subthreshold, so as to achieve better matching. By
inspection of the circuit, it can be observed that the minimum supply voltage required is
determined by one VBE plus saturation voltage of the current-mirroring PMOS transistor.
And depending on the temperature range for which the circuit is designed for, the
bandgap reference circuit should be able to operate at 1.2V.
The above analysis on the minimum required operating supply voltage for the bandgap
reference is made without considering the amplifier design. However, the supply voltage
used must ensure proper operation of the amplifier and this is the true limit of the circuit
as illustrated in the design by Banba et al in [18]. Examining the circuit in figure 3-2, it
can be observed that the input range for which the amplifier must be designed for
depends on the base-emitter voltage of the bipolar transistor and this can vary between
0.25V to 0.9V depending on the temperature range which the bandgap must operate.
Therefore if a PMOS input differential pair stage is implemented for the amplifier, the
supply voltage required might be close to 1.8V [18] and this is not feasible for the
proposed chip. Subsequently, to overcome this issue, the input voltage of the amplifier is
scaled down by implementing voltage dividers through resistors R1 and R2 and shifting
the inputs of the amplifier to these nodes. However this may not be sufficient to meet the
stringent supply voltage requirements of the proposed design, especially in ensuring that
enough supply headroom is available for the conventional input differential pair so as to
maintain a constant trans-conductance gain.
-
In a conventional input differential pair, the trans-conductance gain is maintained by
keeping the quiescent current in the pair constant. This is achieved by utilizing a DC
current source IBias to bias the pair. However, when the input common-mode voltage falls
below the gate-source voltage of the pair plus the saturation voltage of the current
source, the biasing transistor leaves saturation and operates in triode region resulting in
the biasing current through the pair to change. Hence this causes the trans-conductance
gain of the conventional differential pair to be affected. Figure 3-3 shows the schematic
of the operational amplifier implemented for the bandgap reference circuit.
3-3: Schematic of operational amplifier in bandgap core circuit
A modified input differential pair, i.e. “Flipped Differential Pair” proposed in [19], [20] is
implemented in the amplifier using current source I0, transistors M7 – M9, M12, M15 and
M16. This input differential pair structure requires lower supply headroom as compared
to the conventional differential pair as it can maintain a constant bias current even if the
biasing transistor M12 operates in the triode region. In order to explain its operation,
consider the case when the input common-mode voltage increases, the negative
feedback loop formed by M7-M9 causes the total current in transistors M7 and M8 to
-
remain constant, defined by the biasing current source I0. As the input common-mode
voltage increases further, such that transistors M9 and M12 enters triode mode, the
negative feedback loop in maintaining constant biasing current will pull the gate voltages
of M9 and M12 low. Given that the drain-source voltages of M9 and M12 are equal
defined by appropriate sizing of M15 and M16, M12 replicates the constant current in M9
with appropriate scaling and continues to be a constant current source for M15 and M16.
By implementing this modified differential pair, the input common-mode range for the
amplifier is extended, thereby addressing the input common-mode range issue for the
bandgap. The amplifier is implemented using transistors M10 – M26 and all the
transistors except for the input differential pair are designed to operate in saturation
mode so as to achieve better matching. And to address the supply headroom issue
which exists at the input stage of the amplifier, the diode-connected transistor is
replaced by the “flipped” structures implemented through transistors M18, M21 - M22
and M19, M25 – M26.
2
Figure 3-4 shows the top schematic for the bandgap reference circuit and it is similar to
that shown in figure 3-2. A startup circuit is incorporated in the design using transistor
M5 and M6 to ensure proper operation of the circuit during the startup phase. During
initial power-up of the circuit, the node “Vbg_Start” is low. As a result, the gates of the
current-mirroring transistors will be pulled low by the startup transistors M5 and M6
thereby preventing the bandgap circuit to remain in a non-operational condition. When
the bandgap is functional such that the node “Vbg_Start” is non-zero, the pull-down path
through transistor M6 will be disabled, isolating the startup circuit from the main circuit of
the bandgap.
-
3-4: Schematic of bandgap reference top inclusive of buffer
In order to resolve issues such as process variations and mismatches which can
possibly arise due to the non-idealities in implementation, the facilities to trim the
resistances of resistors R0 and R3 have been incorporated in the design. Two trim bits,
VBG_TC which are to be applied externally through the pins made available are
implemented to adjust the resistance of R0. These two bits serve the purpose of
adjusting the overall temperature coefficient as observed from (3.15), i.e. to adjust R1/R0
ratio. However, it should be noted that this action will affect the absolute voltage of the
reference observed at the output. After adjusting R0 such that the temperature coefficient
is minimized, the issue regarding the accuracy of the output is addressed by trimming
the resistance of R3 through two bits, i.e. VBG. Resistance of R3 is selected to
adjust the absolute value of the output since it only affects the scaling factor in (3.15)
and has no effect on the temperature coefficient. Otherwise, this step will have affected
the temperature dependency of the output which has been trimmed in the previous step.
-
When the buck-boost converter is disabled, the bandgap generates a stable reference
voltage of nominal value approximately 250mV. The reference voltage variation with
temperature range of -40 to 125 degrees Celsius is simulated at a supply voltage of 1.2V
and 1.5V. Figure 3-5 shows both schematic and post-layout simulation results (at typical
corner) of how the reference voltage at both the input and output of the buffer vary with
temperature when supply voltage is set at 1.5V. In this case, the bandgap VBG
and temperature coefficient VBG_TC trimming bits are at the default settings of
“00” and “01” respectively.
A
C
B
D
3-5: Bandgap reference variation with temperature (V33=1.5V, Typical)
(A, B: Vbg_Core, Vbg_Out, Schematic, C, D: Vbg_Core, Vbg_Out, Post-Layout)
-
It can be observed that there is not much difference between the schematic and postlayout simulation results. The schematic reference output displays a variation between
249.1556mV and 250.0962mV while the post-layout results show a range from
249.1956mV to 250.156mV over the wide temperature range of -40 to 125 degrees
Celsius. Hence the schematic and post-layout simulation results show a temperature
coefficient of 22.8ppm and 23.3ppm respectively. Figure 3-6 shows the reference
voltage variation with temperature when the supply voltage is lowered to 1.2V. The
bandgap can be deduced to be functional when the supply is 1.2V over the entire
temperature range and the temperature coefficients for the schematic and post-layout
views are derived from the results to be 23.2ppm and 23.7ppm respectively and the
schematic and post-layout results are seen to be similar.
A
C
B
D
3-6: Bandgap reference variation with temperature (V33=1.2V, Typical)
(A, B: Vbg_Core, Vbg_Out, Schematic, C, D: Vbg_Core, Vbg_Out, Post-Layout)
-
2
When the buck-boost converter is enabled, the bandgap generates a stable reference
voltage of nominal value approximately 660mV. The reference voltage variation with
temperature range of -40 to 125 degrees Celsius is simulated at a supply voltage of 2.0V
and 3.3V. Figure 3-7 shows both schematic and post-layout simulation results (at typical
corner) of how the reference voltage at both the input and output of the buffer vary with
temperature when the supply is 2.0V.
A
C
B
D
3-7: Bandgap reference variation with temperature (V33=2.0V, Typical)
(A, B: Vbg_Core, Vbg_Out, Schematic, C, D: Vbg_Core, Vbg_Out, Post-Layout)
The schematic reference output displays a variation between 657.565mV and
659.964mV while the post-layout results show a range from 657.687mV to 660.057mV
over the wide temperature range of -40 to 125 degrees Celsius and thereby display
similar temperature coefficients of 22.0ppm and 21.8ppm respectively. Figure 3-8 shows
-
the bandgap reference output variation (schematic and post-layout) with temperature
when the supply voltage is increased to 3.3V. The temperature coefficients of the
reference output are observed to be similar to that when the supply is 2.0V and are
derived to be 23.4ppm and 23.2ppm respectively for schematic and post-layout views.
From the simulation results, it can be concluded that the bandgap reference
implemented is functional for all the supply voltage and temperature ranges required for
the application.
A
C
B
D
3-8: Bandgap reference variation with temperature (V33=3.3V, Typical)
(A, B: Vbg_Core, Vbg_Out, Schematic, C, D: Vbg_Core, Vbg_Out, Post-Layout)
3
Process variations and mismatches such as mismatch between the current-mirroring
transistors and variations in the resistances implemented will result in the final reference
-
output generated to deviate from that specified. Figures 3-9 and 3-10 show the reference
output variation with temperature, generated with the different VBG and nominal
VBG_TC settings available through external pins under different process corners
and mismatch when V33 is 1.2V. From the results obtained through nominal setting of
250mV, the output can be observed to vary by approximately ±20mV from 250mV under
the different conditions. These results are obtained without undergoing the process of
trimming for the temperature coefficients but they provide an indication of the magnitude
of variation which can be expected with the different conditions.
A
B
C
D
3-9: Bandgap reference variation with temperature (V33=1.2V, Corners)
(A: Vbg_240mV, B: Vbg_250mV, C: Vbg_260mV, D: Vbg_270mV)
-
A
B
C
D
3- : Bandgap reference temperature coefficients before trim (V33=1.2V)
(A: Vbg_240mV, B: Vbg_250mV, C: Vbg_260mV, D: Vbg_270mV)
3-
: Bandgap reference temperature coefficients after trim (V33=1.2V)
-
3-
: Bandgap reference output after trim (V33=1.2V)
Figures 3-11 and 3-12 show the distribution on the temperature coefficients and voltages
obtained at the reference output for 150 samples after trimming using VBG_TC
and VBG. The temperature coefficients obtained are kept to less than 50ppm and
the outputs obtained are between 0.245V and 0.255V (except for 1 sample) for the 150
samples tested through Monte Carlo simulation, thereby resulting in ±2% accuracy with
respect to the designed value of 0.25V. If better temperature coefficients are to be
achieved, higher order temperature dependent terms should be compensated using
techniques which are well-documented in several literatures.
4
Similarly, figures 3-13 and 3-14 show the reference output variation with temperature,
generated under different process corners and mismatch (150 samples) when V33 is
3.3V without trimming through VBG and VBG_TC.
-
A
B
C
D
3- : Bandgap reference variation with temperature (V33=3.3V, Corners)
(A: Vbg_635mV, B: Vbg_660mV, C: Vbg_685mV, D: Vbg_710mV)
A
B
C
D
3- : Bandgap reference temperature coefficients before trim (V33=3.3V)
(A: Vbg_635mV, B: Vbg_660mV, C: Vbg_685mV, D: Vbg_710mV)
-
It can be observed from figure 3-13 that all 150 samples except one show a variation of
approximately ±40mV from the nominal 660mV. Figures 3-15 and 3-16 show the
distribution on the temperature coefficients and voltages obtained after trimming. The
temperature coefficients obtained are less than 51.93ppm and the outputs obtained are
between 0.648V and 0.672V for the 150 samples tested through Monte Carlo simulation.
3-
: Bandgap reference temperature coefficients after trim (V33=3.3V)
3-
Bandgap reference output after trim (V33=3.3V)
-
5
In the schematic shown in figure 3-4, the feedback signal produced by the amplifier in
the bandgap circuit returns to both its inputs. The overall stability of the feedback,
comprising of the positive and negative feedback loops can be verified by analyzing its
frequency response. To compensate the loop, shunt compensation [17] can be
implemented by adding a capacitor at the output of the amplifier, gates of currentmirroring transistors. Figure 3-17 and 3-18 show the frequency responses of the loop
gain of bandgap 250mV when V33 is 1.2V and 1.5V respectively. It can be observed that
it has a loop gain of more than 83dB and a phase margin of approximately 67 degrees,
thereby verifying the stability of the bandgap when buck-boost converter is disabled.
When buck-boost converter is enabled, the loop gain obtained shows a gain of more
than 73dB and a phase margin of more than 65 degrees as shown in figure 3-19.
A
3-
B
: Bandgap 250mV loop gain frequency response (V33=1.2V, Typical)
(A: Schematic, B: Post-Layout)
-
-
-
3-
–
–
-
: Bandgap 250mV loop gain frequency response (V33=1.5V, Typical)
-
-
3-
-
–
–
-
-
: Bandgap 660mV loop gain frequency response (V33=3.3V, Typical)
-
6
When the buck-boost converter is enabled, the input supply provides the substrate
voltage for the proposed chip. And if the input supply is implemented through renewable
energy sources, large variation on the substrate voltage can be expected depending on
external conditions. From the schematic shown in figure 3-4, it can be observed that the
collectors of the BJTs are connected to substrate and large variation in substrate voltage
will result in varying collector-emitter voltages and thereby affecting the base-emitter
voltages due to second-order effects. As the base-emitter voltages change, the drainsource voltages for the current-mirroring transistors will change and these might affect
the reference output generated. Figures 3-20 and 3-21 show the variation of reference
output with substrate voltage (schematic and post-layout) when the regulated V33 is
2.0V and 3.3V respectively. It is observed that the variation of the bandgap output is less
than 1.5mV in both cases as substrate changes over a wide range from -12.5V to -0.30V.
-
-
3-
–
–
-
-
: Bandgap reference variation with substrate (V33=2.0V, Typical)
-
-
-
3-
–
–
-
-
: Bandgap reference variation with substrate (V33=3.3V, Typical)
7
The bandgap 250mV output profiles observed as the supply ramps up from 0V to 1.2V in
1ms under typical conditions is presented in figure 3-22. The output obtained at the input
of the buffer can be observed to startup and reach approximately 250mV just before the
supply reaches 900mV. The buffer output ramps up slower and reaches 250mV when
the supply reaches approximately 1V. This is due to the large output filtering capacitor
and also limited slewing capability of the buffer. Similarly, the startup profile of bandgap
reference 660mV is simulated and presented in figure 3-23. Again, the buffer output is
observed to startup slower as compared to its input. As such, circuitries which make use
of the reference output during startup such as the under-voltage comparator are
designed to use the reference at the buffer input so as to ensure that the under-voltage
threshold detected is accurate.
-
3-
: Bandgap reference 250mV startup (V33 ~ 0V to 1.2V in 1ms, Typical)
3-
: Bandgap reference 660mV startup (V33 ~ 0V to 3.3V in 1ms, Typical)
-
8
The bandgap reference transient response to changes in supply voltage will affect the
performances of circuits such as LDO regulators and most importantly the buck-boost
converter which use this reference. Figure 3-24 shows the bandgap 250mV (both input
and output of buffer) transient response when V33 changes between 1.2V and 1.5V in
1µs. The variation of bandgap reference obtained at the output of the buffer is observed
to be much less than that observed at the input due to the larger filtering capacitor at the
output. This variation is observed to be less than ±5mV, which is approximately ±2% of
the final output. Similarly, the transient response of bandgap 660mV (both input and
output of buffer) when V33 changes between 3.225V and 3.375V in 30µs is simulated
and presented in figure 3-25. The same variation on V33 can occur when a constant
50mA load is applied on V33, with a 10µF output capacitor. The bandgap reference at
buffer output deviates by less than ±2mV, approximately ±0.3% of the final output.
3-
: Bandgap line transient (V33 ~ 1.2V to 1.5V in 1µs, Typical)
-
3-
: Bandgap line transient (V33 ~ 3.225V to 3.375V in 30µs, Typical)
)
Output Voltage (150 Samples, After Trim)
245.01mV
250.01mV
254.71mV
Temp Coefficient (150 Samples, After Trim)
16.42ppm
23.70ppm
46.54ppm
Bandgap Core Loop Gain
73.27dB
83.42dB
83.69dB
Bandgap Core Phase Margin
62.67deg
67.22deg
72.52deg
Quiescent Current
3.597µA
4.013µA
4.612µA
Output Voltage (150 Samples, After Trim)
648.32mV
660.17mV
671.96mV
Temp Coefficient (150 Samples, After Trim)
12.27ppm
23.20ppm
51.93ppm
Bandgap Core Loop Gain
70.79dB
73.09dB
76.07dB
Bandgap Core Phase Margin
60.52deg
65.35deg
71.19deg
Quiescent Current
3.829µA
4.272µA
4.877µA
3-1: Bandgap reference summarized simulated performance
-
CChhaapptteerr 44
Startup Control Circuitries
The design of the proposed buck-boost converter can be divided into 2 main parts, i.e.
startup and regulatory circuitries. While the regulatory circuitries have the benefit of
operating off the output regulated V33 supply rail, startup circuitries need to operate off
the substrate supply rail which can vary over a wide range between -0.75V and -10.0V.
The main purpose of the startup circuitries is to boost the output regulated voltage V33,
up to a voltage level at which the regulatory circuitries can take over the controls of the
converter, i.e. when under-voltage detection goes low. In this case, the under-voltage
comparator output is designed to go low when V33 reaches approximately 2.2V.
The wide range of the substrate supply rail poses a huge challenge to the design of the
startup circuitries. Besides catering to the high end of the supply range, the circuitries
should be simple such that the converter is able to startup at the lowest possible supply.
For the conventional buck-boost converter, in order to boost up the output voltage, the
switching on and off of the power NMOS transistor is a necessary action to charge the
inductor. Hence, driving circuitries for the power transistor are required to be operational
during startup. Since for AMS High-Voltage 0.35µm process [21], threshold voltage for
PMOS transistors are typically higher than that of NMOS, it can be foreseen that the
minimum supply voltage required to startup is the threshold voltage of PMOS. Even then,
depending on the type of PMOS used, the threshold voltage can vary from 0.70V to
1.80V typically. In this case, if the circuitries are operating directly off the substrate
-
supply rail, transistors with high terminal voltage tolerances are required to cater to the
upper limit of substrate supply, i.e. 10.0V. These transistors typically have thicker gate
oxide to withstand high voltage at the gate but it comes at the expense of higher
threshold voltages, inevitably pushing up the minimum startup supply.
An oscillator [22] can be incorporated within the startup system so as to facilitate the
switching on and off of the power NMOS. Duty cycle and frequency of the oscillator will
only determine the startup time required for the buck-boost converter and will not have
an effect on conversion efficiency during steady-state operations. And again, the
oscillator designed must be able to operate under low-supply voltage conditions.
Specifications such as power consumption will be of less importance since these circuits
will be switched off once the regulatory circuits take over the controls.
Besides that, unlike the case of a boost converter [22-23], or even for buck converters
with a narrow supply range, the inductor current peak attained during startup will have a
wider range in the proposed design due to the wide input supply range. Special
circuitries are required to limit the peak inductor current so as not to damage the device.
The inductor current peak obtained should ideally be independent on the input supply.
Upon giving considerations to all the requirements of the startup system for the buckboost converter, the startup system is designed, as shown in figure 4-1. It consists of an
internal startup linear regulator which will generate a regulated supply rail for startup
circuit to operate from. The introduction of a linear regulator will add complexity to the
design. Besides that, more silicon area will be required and also more current will be
-
consumed. However the regulated supply rail will allow the use of low-voltage transistors
with lower threshold voltage in the startup circuitries. Also, transistors with lower gatesource voltage tolerance, typically required to be less than 3.3V, can then be used as
power NMOS. These transistors have lower threshold voltage, i.e. less than 1.0V in
worst conditions, thereby enabling startup operations in low input supply conditions.
Moreover, the linear regulator will be shut down during regulation phase of the converter.
Hence this additional current will only be observed during startup, not affecting the
conversion efficiency. One challenge will be the generation of a reference voltage for the
regulator under the startup conditions. The design of this regulator will be discussed in
detail in the chapter 6.
4-1: Startup control system block diagram
-
Besides the internal startup regulator, the startup circuitries consist of a current-starved
oscillator and an adaptive on-time generator. The outputs of the two circuits control a SR
flip-flop which then controls the switching on and off of the NMOS power transistor
through a driver. The two blocks operate by using current generated by an internal
current reference. All the blocks will be switched off once the under-voltage comparator
output goes low so as to reduce power consumption. It should be noted that during
startup, the buck-boost converter is operating in the asynchronous mode where the
PMOS power transistor is switched off and charges stored in the inductor are transferred
to the output through the diode. This reduces the complexity of the startup system while
not compromising on overall efficiency.
As mentioned earlier, the inductor current peak as the NMOS power transistor is turned
on can be approximated by
I L , peak =
V
0 − (− VPSUB )
Ton = PSUB Ton
L
L
(4.1)
And if the duration which the NMOS power transistor is switched on is not properly
managed, the inductor current peak can reach up to a few amperes which can be
hazardous to the device and external components. Thus an adaptive on-time generator
is introduced on top of the ring oscillator so as to limit the current when the input supply
is high. The design of ring oscillator and adaptive on-time generator will be discussed in
detail in the subsequent sections.
-
-
The main objective for introducing an adaptive on-time generator in the startup system is
to ensure that the on-time for the NMOS power transistor is not too long when substrate
-
supply voltage is high. Without the adaptive on-time generator, the on-time across the
substrate supply range can be written as
Ton,osc =
D
f osc
(4.2)
where D and fosc are the duty cycle and oscillating frequency of the proposed oscillator.
Combining (4.1) and (4.2),
I L, peak =
VPSUB
DVPSUB
Ton =
L
Lf osc
(4.3)
From (4.3), it can be observed that if ring oscillator is the sole control mechanism for the
on-time, the inductor current peak obtained varies over a wide range similar to the fixed
on-time methodology. This is mainly due to the wide input range which the proposed
buck-boost converter supports.
The addition of an adaptive on-time generator limits the power NMOS on-time when
substrate supply is high such that
(
Ton = min Ton,osc ,Ton,adpt _ gen
)
(4.4)
In the event when substrate supply is high, the on-time generated by the adaptive
generator is smaller than that given in (4.2). In this case the output of the generator
resets the oscillator output, thus limiting the on-time and inductor current peak. When
VPSUB is low, the oscillator output will determine the on-time directly
Considering the fact that any circuit designed is to function at a minimum supply voltage,
the simple adaptive on-time generator as shown in figure 4-2 [24] is implemented in the
-
startup system. The core of the adaptive generator is implemented using transistors M2M8. Transistor M2 serves the purpose of a switch which will cut off the large quiescent
current path through M3 once regulatory circuits take over control. Assuming that the onresistance of M2 is negligible, the current through M3 and resistor RBIAS is
IM 3 ≈
VPSUB − VGS ,M 3
RBIAS
(4.5)
4-2: Simple startup adaptive on-time generator schematic
This current is then mirrored through transistors M4-M6 and upon activation of the
generator as the ring oscillator goes high, the current will charge capacitor C0, building
up the gate voltage of M8. Subsequently, the drain voltage of M8 will decrease and
cause the generator output to toggle and turn off the power NMOS. It should be noted
that the current mirrors are designed to operate in saturation so as to reduce effect of
current mirror mismatch. However, this implies that the circuit requires a minimum
supply of VGS,M5 + VDSAT,M4 and for the process used, this can reach up to 1.2V in the
worst temperature and process corner. Hence, in order to further reduce the minimum
-
substrate supply required for startup, the on-time of the current-starved oscillator is
introduced as a direct control of the NMOS power transistor on-time under this lowvoltage operating condition. In this case, the oscillator is designed to determine the ontime when VPSUB is lower than 1.5V. It can be observed that the generator is operating off
the internal regulated supply rail. Doing so allows the utilization of thin gate oxide
transistors, i.e. low threshold voltage in the design, reducing minimum supply required.
Although the adaptive generator circuit is simple, the on-time generated will deviate over
a wide range due to process and temperature variations, as pointed out in [24]. Since
M3 operates in saturation, i.e.
VGS ,M 3 ≈ VTH ,M 3 +
2I M 3 L
µCox W M 3
(4.6)
Combining (4.5) and (4.6), it can be observed that the current through RBIAS which will
determine the on-time is dependent on two parameters, i.e. VTH,M3 and resistance of
RBIAS which will vary significantly over process and temperature corners. The variation
due to temperature can be significantly by choosing resistors with opposite temperature
coefficient to that of the threshold voltage of M3. Moreover, the absence of a reference
voltage upon startup results in implementing a simple common source gain stage as the
comparator. As a result, the generator output which is used to reset the SR latch varies
with the gain and threshold voltage of the input transistor, leading to more uncertainties
on the generated on-time. However, as mentioned earlier, the introduction of the on-time
generator and oscillator serves the purpose of protecting the device as well as external
components from very high inductor current. The accuracy of the on-time is not crucial
so long as the inductor current is tolerable. Inaccuracies will only result in variation of the
-
startup time and have no impact on the overall conversion efficiency unlike the adaptive
on-time generator operating during regulation. For this case, the inductor current limit
during startup is designed to be approximately 330mA when VPSUB=-1.5V, under typical
process and temperature conditions. And from simulation results (to be presented later),
the inductor current can reach up to 600mA under worst case conditions.
-
-
The designed startup system also includes a current-starved ring oscillator. It serves as
the mastermind for the startup of the converter. While the adaptive on-time generator
limits the inductor current when VPSUB is high i.e. more than 1.5V, the on-time of the
oscillator determines the power NMOS on-time during low input supply conditions. Since
the converter operates in asynchronous mode during startup, once the power NMOS is
switched off, either due to reset from adaptive generator or oscillator output going low,
the charges stored in the inductor will be discharged through the external diode into the
reservoir capacitor. Hence the minimum discharge duration is determined by the off-time
of the oscillator. The next charging cycle will then be initiated when oscillator output goes
high again in the next oscillating cycle.
The on-time of the oscillator is designed to be about 2.5µs when VPSUB=-1.5V. This
worked out to a 375mA inductor current peak in the ideal case. However, in actual case,
additional voltage drop across the NMOS power transistor will result in a lower current
peak observed. In this case, the inductor current peak observed through post-layout
simulation is about 300mA.
-
The off-time of the oscillator determines the amount by which the inductor current
decays given the inductance value and the output voltage. As such the amount by which
the inductor current decays can be expressed as
∆I L =
(V 33 + Vdiode )Toff
L
(4.7)
Hence given an inductance value of 10µH and an off-time of approximately 2.5µs when
VPSUB=-1.5V, and assuming that the voltage across the external diode is 0.30V. the
inductor current of 300mA is expected to discharge completely when V33 rises to 0.9V.
4-3: Startup Current-Starved Ring Oscillator Schematic
Figure 4-3 shows the schematic of the current-starved ring oscillator implemented [25].
The frequency of the ring oscillator is basically determined by the current-starved
inverter chain formed by transistors M6 to M19 i.e. delay when charging, determined by
the on-resistance of the PMOS and the gate capacitances and delay when discharging
depending on the limited current and gate capacitances. The output from the currentstarved inverter chain is not rail-to-rail due to the current source I0. Hence the purpose
-
of the subsequent gain stages and inverters formed by transistors M20 - M28 is to boost
the output of the oscillator to be rail-to-rail. It can be observed that the ring oscillator is
powered off the internal supply rail supplied by the startup internal regulator. As a result,
low threshold transistors can be deployed in the ring oscillator so as to reduce the
minimum substrate voltage required for startup.
The delay formed by the inverter chain is dominated by the discharging phase within the
chain. This is mainly due to the fact that the discharging current is limited by current
source I0, whereas the charging current is only limited by the on-resistance of the PMOS.
The time taken to discharge gate capacitances and other parasitic capacitances at each
node can be written as
Tdis = C g
VDD − VSP
I dis
(4.8)
where Cg is the capacitances at the node, VSP is threshold of the inverter and Idis is the
discharging current available for the particular inverter. It should be noted that the
current sourced by I0 is split between inverters which are in discharging phase within the
chain. It can be concluded from (4.8) that the discharging time and thus the oscillating
frequency is dependent on the supply voltage. In general, the frequency is expected to
decrease when supply voltage to oscillator increases. Given that the off-time generated
by the oscillator increases with supply, it can be deduced from (4.7) that the V33 voltage
at which the inductor current discharges completely decreases as VPSUB increases. While
the on-time increases with supply, there should be minimal effect on the inductor current
peak observed, since the adaptive on-time generator will take over the control in high
substrate supply cases.
-
Figure 4-4 shows the transient response (both schematic and post-layout) of the
adaptive on-time generator when VPSUB=-1.5V. The entire startup system is included in
this simulation. The adaptive on-time generated for schematic and post-layout is 2.46µs
and 2.51µs respectively, while it can be observed that the inductor current peak
observed is about 310.3mA and 299.9mA for the schematic and post-layout respectively.
The on-time generated for the post-layout case is slightly longer due mainly to parasitic
capacitances introduced at the input of comparator. Besides that, the inductor current
peak observed is less than 375mA expected in ideal conditions, due to the resistance
and therefore additional voltage drop across the NMOS power transistor. Nevertheless,
the inductor current limit imposed through the implementation of the adaptive on-time
generator provides a good protection for the devices involved.
B
A
Out
-
F
-
Out
4-4: Startup adaptive on-time & Current limit generated (Typical, VPSUB=-1.5V)
(A: Schematic, B: Post-Layout)
-
-
4-5: Startup adaptive on-time & Current limit generated (Corners, VPSUB=-1.5V)
As mentioned earlier, process and temperature variations of the resistance RBIAS,
threshold voltages of M3 and input transistor of the comparator, and also capacitance
C0 will result in a large variation in the adaptive on-time generated. Figure 4-5 shows the
adaptive on-time and inductor current profile during startup for all process and
temperature conditions when VPSUB=-1.5V. It can be observed that the on-time
generated over a wide range resulting in a large variation of inductor current peak
observed i.e. approximately between 80mA to 600mA. Although the effect of process
variations can be nullified by providing trimming on RBIAS as documented in [24], it is
not implemented in the startup system design since the accuracy of the current has no
effect on overall efficiency. However, this will result in a huge difference in startup time
over the different conditions but this is not a concern for the targeted application. If a
smaller spread in the startup time is to be achieved, the procedure adopted in [24] can
be implemented.
-
The on-time generated is of greater concern when the substrate voltage is high. Figures
4-6 to 4-8 shows typical transient responses of the adaptive generator when VPSUB=-3.0V,
VPSUB=-5.0V, VPSUB=-10.0V respectively. It can be observed that in all of these cases, the
inductor current is controlled to be less than 300mA and the variation is small over the
wide input supply range.
The performance of the generator is further verified across all process and temperature
corners when the substrate supply is at its highest end i.e. VPSUB=-10.0V, as shown in
figure 4-9. Again, it can be observed that the adaptive on-time and the resulting current
peak deviate over a wide range but the inductor current is still kept below 600mA. Lastly,
figure 4-10 summaries the results as it shows the typical inductor current peak obtained
over the input supply range. It can be observed that the current obtained is fairly
constant when substrate voltage is above 1.25V and falls significantly as the generator
fails to operate when VPSUB drops further.
B
A
Out
-
Out
-
4-6: Startup adaptive on-time & Current limit generated (Typical, VPSUB=-3.0V)
(A: Schematic, B: Post-Layout)
-
B
A
Out
t
-
Out
-
I
I
4-7: Startup adaptive on-time & Current limit generated (Typical, VPSUB=-5.0V)
(A: Schematic, B: Post-Layout)
B
A
Out
-
Out
-
I
I
4-8: Startup adaptive on-time & Current limit generated (Typical, VPSUB=-10.0V)
(A: Schematic, B: Post-Layout)
-
-
4-9: Startup adaptive on-time & Current limit generated (Corners, VPSUB=-10.0V)
-
4-10: Startup adaptive current limit generated against VPSUB (Typical)
-
Figures 4-11 to 4-15 show the transient responses of the startup current-starved ring
oscillator when VPSUB=-1.0V, VPSUB=-1.5V, VPSUB=-3.0V, VPSUB=-5.0V and VPSUB=-10.0V
respectively. Each simulation result includes the typical oscillating profile as well as the
slowest and fastest oscillating profile obtained using the different temperature and
process corners. For the case when VPSUB=-1.5V, it can be observed that the oscillator
has a typical oscillating period of approximately 4.98µs and has an on-time of 2.49µs,
satisfying the specifications mentioned before. Furthermore, the oscillator is verified of
its functionalities across all conditions even when VPSUB=-1.0V. Hence ensuring the
startup operations even when VPSUB=-1.0V. Lastly, it can be observed that there is a
large variation in oscillating frequency across the different conditions. This is expected
as parameters such as switching point of the inverters within the chain and gate
capacitances are process and temperature dependent.
4-
: Startup ring oscillator output transient response (Corners, VPSUB=-1.0V)
-
4-
: Startup ring oscillator transient response (Corners, VPSUB=-1.5V)
4-
: Startup ring oscillator transient response (Corners, VPSUB=-3.0V)
-
4-
: Startup ring oscillator transient response (Corners, VPSUB=-5.0V)
4-
: Startup ring oscillator transient response (Corners, VPSUB=-10.0V)
-
Table 4-1 summarizes the simulated performance of the designed startup currentstarved ring oscillator at post-layout level.
Osc Freq (VPSUB=-1.0V, VSS_V33_INT=1.0V)
108.58KHz
192.31KHz
228.83KHz
Osc Freq (VPSUB=-1.5V, VSS_V33_INT=1.5V)
115.87KHz
200.80KHz
211.86KHz
Osc Freq (VPSUB=-2.0V, VSS_V33_INT=2.0V)
121.95KHz
186.22KHz
194.93KHz
Osc Freq (VPSUB=-3.0V, VSS_V33_INT=3.0V)
110.38KHz
139.08KHz
165.56KHz
Osc Freq (VPSUB=-5.0V, VSS_V33_INT=3.3V)
102.15KHz
129.03KHz
152.91KHz
Osc Freq (VPSUB=-10.0V, VSS_V33_INT=3.3V)
102.25KHz
129.03KHz
152.44KHz
On-Time (VPSUB=-1.0V, VSS_V33_INT=1.0V)
2.13µs
2.41µs
4.17µs
Off-Time (VPSUB=-1.0V, VSS_V33_INT=1.0V)
2.13µs
2.80µs
5.18µs
On-Time (VPSUB=-1.5V, VSS_V33_INT=1.5V)
2.44µs
2.49µs
4.35µs
Off-Time (VPSUB=-1.5V, VSS_V33_INT=1.5V)
2.17µs
2.48µs
4.89µs
On-Time (VPSUB=-2.0V, VSS_V33_INT=2.0V)
2.60µs
2.83µs
4.50µs
Off-Time (VPSUB=-2.0V, VSS_V33_INT=2.0V)
2.28µs
2.54µs
4.33µs
On-Time (VPSUB=-3.0V, VSS_V33_INT=3.0V)
3.43µs
4.10µs
5.73µs
Off-Time (VPSUB=-3.0V, VSS_V33_INT=3.0V)
2.58µs
3.09µs
4.13µs
On-Time (VPSUB=-5.0V, VSS_V33_INT=3.3V)
3.61µs
4.47µs
6.26µs
Off-Time (VPSUB=-5.0V, VSS_V33_INT=3.3V)
2.75µs
3.28µs
4.37µs
On-Time (VPSUB=10.0V, VSS_V33_INT=3.3V)
3.61µs
4.47µs
6.25µs
Off-Time (VPSUB=-10.0V, VSS_V33_INT=3.3V)
2.75µs
3.28µs
4.37µs
4-1: Startup current-starved ring oscillator summarized simulated performance
-
CChhaapptteerr 55
Internal Low-Dropout Regulator 1
As mentioned earlier, in order for the proposed buck-boost converter to operate down to
the lower end of a wide input supply range, the startup circuitries, driver for the power
NMOS and the power NMOS transistor have to be implemented using low threshold
voltage devices. However, these devices have a limited tolerance to the voltage applied
across the gate-source terminals, due to the thin oxide layer at the gates. Typically, the
maximum VGS which these devices can safely operate is about 3.6V. And since the
startup circuitries and the power NMOS transistor are using the negative supply rail
given by the negative substrate voltage of VPSUB, supply rails which are around 3.3V
above the substrate voltage have to be generated to power these circuits. As a result, it
is important to implement an internal power management system so as to generate
separate regulated supply rails to power the necessary circuits while ensuring that these
circuits are operating under safe operating conditions.
Circuits operating off the internally regulated supply rails can be categorized into two
main groups, namely startup circuits such as current-starved oscillator, startup adaptive
on-time generator, etc and regulatory circuits such as driver for power NMOS transistor
and level shifters. As mentioned earlier, startup circuits serve the purpose of boosting
the output regulated voltage V33 when V33 is lower than 2.2V and once V33 reaches
the under-voltage threshold of 2.2V, the regulatory circuits assume control of the
regulator. And in order to ensure that the regulatory functions of the buck-boost
converter are still operational even when VPSUB drops to -0.30V and that the internally
generated supply rail is still approximately 3.3V above VPSUB so that the on-resistance of
the NMOS power transistor can be kept small, the internally generated supply rail, off
which the regulatory circuits operate needs to be generated from the regulated output
supply V33. Figures 5-1 and 5-2 show two possible schemes for the internal power
management system.
5-1: Internal Power Management Scheme A
The internal power management scheme proposed in figure 5-1 involves only a single
linear regulator, generating an internal supply rail VSS_V33 used by both the startup
circuitries and the regulatory blocks such as the level shifters. The linear regulator
operates from either the supply rail VSS_VSUP which is actually the ground node of the
entire circuit or the output regulated supply V33 depending on the state of the power
switches. The power switches are controlled by the under-voltage detector output, i.e.
when V33 is below 2.2V, the under-voltage comparator output is high and the linear
regulator operates off VSS_VSUP and once V33 is boosted above 2.2V, the power switch
connecting V33 will be turned on while the other switch is turned off such that the linear
regulator generates the internal supply VSS_V33 using V33. However, there are several
foreseeable issues in the implementation of the internal power management system
presented in figure 5-1. One of these issues is the design of power switches. If the
power switches are implemented using MOS transistors and in the event when the
under-voltage comparator output is low and that the switch connected to V33 is turned
on, there exists a diode path from V33 to ground (through the body diode inherent in the
MOS switch connected to VSS_VSUP), resulting in unnecessary power loss or worse still,
failure of the device. One possible solution to this problem is the implementation of backto-back diode by connecting two MOS switches in series, but this solution results in a
larger silicon area.
Another possible problem in the implementation of the internal power management
scheme is the design of the control circuitries for the power switches. As mentioned
earlier, the power switches are controlled by the under-voltage detection circuitry output.
However, it should be noted that the under-voltage comparator is powered from the
regulated output supply V33 and when V33 is still at low voltage level, the power switch
connected to VSS_VSUP should be turned on. Hence it is a challenge to design the control
circuitries for this switch since the under-voltage detection circuitry output is still invalid
during startup. Hence, it can be concluded from the above discussions that the major
problem in implementing the internal power management scheme in figure 5-1 lies in the
design of the power switches and their control circuitries. Figure 5-2 presents an
alternative internal power management scheme.
5-2: Internal Power Management Scheme B
In this power management scheme, two linear regulators, namely internal regulator 1
and internal regulator 2 are implemented in the chip generating two internal supply rails
VSS_V33_INT and VSS_V33_EXT to power the circuits. It can be observed from figure 5-2 that
internal regulator 2 operates off VSS_VSUP and it generates VSS_V33_INT which is used to
power the startup circuitries. The other linear regulator operates off the regulated output
V33, generating VSS_V33_EXT which is used to power the regulatory circuits. No power
switches is required in this scheme, and the implementation of two separate internal
supply rail eliminates the risk of introducing circuit path from output V33 to the input
supply which happened in the previous scheme. Although this internal power
management scheme involves an additional linear regulator, the silicon area occupied
by the power management system is expected to be similar to the previous system
proposed since the present scheme does not require power switches and these low onresistance power switches occupy much silicon area.
Besides that, it can be observed from figure 5-2 that the present scheme involves an
additional pre-driver for the power NMOS transistor and since the pre-drivers take in
digital inputs, the output of the under-voltage detection circuit can be used to control and
determine the appropriate pre-driver used to drive the power NMOS. Note that the power
NMOS transistor is shared, and that both pre-drivers are actually driving the same
transistor. Additional controls are introduced in the pre-drivers so as to facilitate the
sharing of the power NMOS so as to reduce the silicon area required. In this case, the
design of the control circuitry can be implemented using simple logic gates eliminating
the hassle of introducing complex analog circuits as required in the previous scheme.
The sole purpose of the two internal regulators is to ensure that the low threshold
voltage transistors are able to operate within the safe operating condition, such that the
maximum gate-source voltage which the transistors are exposed to is not more than
3.6V. However, if the regulated voltage is much less than 3.6V, the on-resistance of the
power NMOS transistor will be higher and will degrade the conversion efficiency during
regulation. And since during regulation, the pre-driver for the power NMOS is powered
by VSS_V33_EXT, smaller temperature and process variation of VSS_V33_EXT will ensure that
the overall conversion efficiency does not degrade much with the operating conditions.
On the other hand, since VSS_V33_INT is only used during the startup process and it does
not affect the conversion efficiency during regulation, its only requirement is to be less
than 3.6V across all process and temperature corners. Also, when the input supply VPSUB
is low, for instance when VPSUB is -1.0V, the pass transistor for internal regulator 2 must
behave like a low-resistance switch, ensuring that there is minimal voltage drop so that
VSS_V33_INT is close to VPSUB voltage level. Having this requirement will improve on the
minimum startup input supply voltage required for the proposed chip. In this chapter, the
design of internal regulator 1 which generates the VSS_V33_EXT supply will be discussed in
detail while the other internal regulator will be touched upon in the next chapter.
There are two main categories of low-dropout regulators, one which requires the use of
large output capacitor that is placed outside the chip while the other category only
require a small output capacitor which can be incorporated within the chip. Using a large
output capacitor greatly reduces the regulated output variation during a load transient
event, while the advantage of the latter is that by incorporating the output capacitor
within the chip, the pin counts of the design can be reduced. However, the decision in
the type of LDO to be implemented is largely based on the application. The maximum
transient output voltage variation can be approximated by the following expression.
∆Vout,max =
I L,max
CL
∆t1 + ∆VESR
(5.1)
Where IL,max is the maximum load current, CL is the output capacitance, VESR is the
voltage variation resulting from the presence of a finite equivalent series resistance in
the capacitor chosen and t1 corresponds to the closed-loop bandwidth of the LDO
regulator.
Therefore, in order to improve on the load transient response of the LDO regulator,
reducing the output voltage variation, it is necessary for the LDO regulator to either have
a large closed-loop bandwidth or to use a large output capacitor at its output. LDO
regulators incorporating a small output capacitor typically have a dominant pole at one of
the internal node of the error amplifier, for instance through the use of Miller effect. In
order for the regulator to have a larger closed-loop bandwidth, it is critical to shift the
non-dominant pole to a higher frequency. This can be achieved by reducing the output
capacitance and resistance of the regulator. The output resistance of the LDO regulator
is dependent on the load condition and will be highest during no load condition when
current flowing through the pass transistor is actually the feedback resistor current (since
output resistance of pass transistor is inversely proportional to current). In other words,
the quiescent current of the regulator has to be increased significantly (using smaller
feedback resistors) so as to reduce the output resistance of the LDO regulator so as to
achieve a larger closed-loop bandwidth. In this particular application, the LDO regulator
is used during regulation phase of the buck-boost converter. As a result, the current
consumption of the LDO regulator will affect the quiescent current consumption of the
converter and therefore a LDO regulator with large quiescent current consumption will
reduce the overall conversion efficiency of the converter during low load condition.
Hence in order to have a good load transient response at the output of the regulator
while not consuming a large quiescent current, a LDO regulator with a large external
output capacitor will be designed.
In order to achieve a low dropout voltage while sourcing a large load current, a large
sized PMOS transistor is normally selected as the pass transistor. For a LDO regulator
with a large output capacitor, the dominant pole is usually generated by the output
capacitor. In addition to that, the introduction of the large gate capacitance of the PMOS
pass device creates another low-frequency non-dominant pole which affects the stability
of the regulation loop. Different compensation methods have been proposed to address
this issue [26-30]. One of the more popular compensation techniques is to reshape the
frequency response of the LDO regulator [27-30] by introducing additional poles and
zeros at predetermined locations. This can be implemented by making use of a feedforward capacitor in a folded topology as shown in [27] or in some cases a left-half plane
(LHP) zero is introduced by making use of the intrinsic equivalent series resistor of the
output capacitor. The LHP zero is then used to cancel the effect of the non-dominant
pole at the output of error amplifier so as to stabilize the regulation loop. However, it is
impossible to obtain a “perfect” pole-zero cancellation as the zero is introduced by ESR
which is outside the chip while the pole depends on gate capacitance of the pass
transistor and output resistance of the amplifier, both of which are process and
temperature dependent. Due to the imperfect pole-zero cancellation, a pole-zero
doublets will be created in the frequency response which will affect the settling behavior
of the LDO regulator. Besides that, the ESR of the output capacitor has to be large
enough so as to shift the LHP zero introduced nearer to the non-dominant pole location
and this results in a poorer load transient response at the output as observed from (5.1).
Alternatively, in [26], a source follower has been implemented as a voltage buffer driving
the PMOS pass transistor. By making use of the low output resistance of the source
follower, the pole at the gate of the pass device can be pushed beyond the unity-gain
frequency of the LDO regulation loop. Figure 5-3 shows a typical architecture of a LDO
regulator with an intermediate buffer stage [31].
-
VPSUB
5-3: Architecture of LDO regulator with intermediate buffer stage [31]
There are namely 3 poles in the LDO structure, located at the output of the error
amplifier (N1), output of the buffer (N2) and the output of the regulator (OUT). In this
architecture, the input capacitance and the output resistance of the intermediate buffer
are designed to be small so as to push the poles located at N1 and N2 beyond the unitygain frequency of the regulation loop. One simple method in implementing the buffer is
to introduce a simple PMOS source follower as shown in figure 5-4. The PMOS source
follower can provide near complete shutdown of the pass transistor under light load
condition, at the expense of a larger voltage headroom requirement. The output
resistance of the simple source-follower can be written as
rob =
1
g m,21
(5.2)
-
VPSUB
5-4: Simple source-follower implementation of the intermediate buffer [31]
Hence in order to reduce the output resistance of the buffer so as to shift the pole
located at N2 to higher frequency, the transconductance gm,21 of transistor M21 has to be
increased. This can be achieved either through using a larger W/L ratio of M21 or
through increasing the biasing current flowing through the buffer. However, increasing
the W/L ratio will result in a larger input capacitance for the buffer, resulting in a lower
frequency pole at node N1 and may compromise on the overall stability of the regulation
loop. On the other hand, increasing the biasing current will imply a lower current
efficiency for the LDO regulator, ultimately affecting the overall conversion efficiency of
the buck-boost converter.
In [31], a modified source-follower with negative feedback is implemented as the
intermediate buffer. A NPN transistor is connected in parallel to the output of the sourcefollower so as to reduce the output resistance by a factor of (1 + ) through shunt
feedback, where
is the current gain of the bipolar device. However, in most CMOS
process, the NPN transistor may not be available. In this design, the bipolar device is
replaced with a normal NMOS transistor and the modified buffer is shown in figure 5-5.
VPSUB
5-5: Source-follower with shunt feedback implementation of the buffer
The NMOS transistor M20 provides a shunt feedback path, in parallel to the output of the
source follower formed by M21. The shunt feedback path provides a low resistance path
at the output of the source-follower, and resistance of this buffer can be written as
rob =
1
(
)
1
g m,21 g m,20 ro,21 ro,22 g m,21
(5.3)
From (5.3), it can be observed that the output resistance of the buffer has been reduced
by a factor of gm,20(ro,21||ro,22), resulting in the pole located at the gate of the pass
transistor to be pushed to a higher frequency by the same factor. Furthermore, this low
resistance can be achieved without utilizing a large W/L ratio for M21, thereby reducing
the input capacitance of the buffer, allowing the pole at N1 to be located at a higher
frequency. Besides that, since the dominant pole frequency increases with the load
current, due to lower output resistance at the LDO regulator, the output resistance of the
buffer should decrease when the load current increases in order to maintain pole at N2
beyond the unity-gain frequency of the regulation loop under the entire load current
range. Therefore, in order to achieve this, a diode-connected PMOS transistor is
connected at the output of the buffer. It serves the purpose of mirroring a fraction of the
load current into the buffer output which the shunt device will source. As a result, the
output resistance through transistor M20 is reduced further as load current increases (as
transconductance of M20 increases due to the increase in current sourced). Hence by
implementing this modified source-follower, small input capacitance and output
resistance can be achieved without consuming a large amount of quiescent current.
The error amplifier for the LDO regulator is implemented using a single-stage foldedcascode architecture using transistors M1-M6, as shown in figure 5-6. Assuming that the
pole located at the output of the buffer is shifted to sufficiently high frequencies under
different current load conditions, the LDO regulator can be regarded as a system with
two gain stages. The first gain stage is formed by the error amplifier while the common
source gain stage realized by the pass transistor constitutes the second gain stage. The
LDO error amplifier implemented in this chip follows that shown in [31] and is stabilized
using the cascode Miller frequency compensation which served to split the two poles of
the system. The use of the cascode Miller frequency compensation scheme allows the
amplifier to achieve wider unity-gain frequency and improved stability by removing the
RHP zero.
-
VPSUB
5-6: Folded-cascode error amplifier in architecture of LDO regulator [31]
Assuming that the current source I2 in figure 5-6 is implemented using a simple current
mirror, the total voltage headroom required for the LDO regulator can be expressed as
VDD ≥ 2VGS + 2VDSAT
(5.4)
The stability of the LDO regulator designed can be evaluated using the loop-gain
transfer function of the regulation loop, by breaking the loop at feedback node. Assuming
that the load capacitance and the compensation capacitance is much greater than the
buffer input capacitance, the loop-gain transfer function as derived in [31] is
C
g m1 g mp ro1Roeq 1 + s c
g m3
R2
T (s ) = −
R1 + R2
1 + as + bs 2 + cs 3
(
a = Roeq CL + g mp ro1Cc
)
(5.5)
(5.6)
-
b = C1CL ro1Roeq
c=
(5.7)
C1CcCL ro1Roeq
g m3
(5.8)
Where Roeq is the equivalent output resistance of the LDO regulator, which together with
the transconductance of the pass device, gmp will change according to the load
conditions. It can be observed from (5.5) that there exists a LHP zero given by
z1 =
g m3
Cc
(5.9)
Also the third-order polynomial existing in the denominator of the transfer function given
by (5.5) indicates that the system has three poles and since the coefficients of the
polynomial have the load-dependent terms Roeq and gmp , it can be concluded that the
locations of the poles will shift according to load conditions. Under light load conditions
when CL >> gmpro1Cc, the regulation loop gain transfer function can be approximated to
T (s ) I L ~0
C
g m1 g mp ro1Roeq 1 + s c
g m3
R2
≈−
CC C r R
R1 + R2
1 + sCL Roeq + s 2C1CL ro1Roeq + s 3 1 c L o1 oeq
g m3
C
g m1 g mp ro1Roeq 1 + s c
g m3
R2
≈−
R1 + R2
C
1 + sCL Roeq (1 + sC1ro1 )1 + s c
g m3
(
=−
)
g m1 g mp ro1Roeq
R2
R1 + R2 1 + sCL Roeq (1 + sC1ro1 )
(
)
(5.10)
And from (5.10), it can be observed that the third pole is cancelled by the LHP zero,
resulting in a two-pole system. Also the two poles correspond to the outputs of the two
gain stages as mentioned earlier, indicating that no pole splitting occurs under this
condition. The two poles are given by
p1 =
1
CL Roeq
(5.11)
p2 =
1
C1ro1
(5.12)
In this case, the dominant pole is determined by the output node and in order to ensure
that the non-dominant pole p2 falls beyond the unity-gain frequency, it is important to
keep the input capacitance of the buffer small. It should be noted that the internal
regulator designed for the purpose of internal power management predominantly
operates under this condition since the circuits operating off this internally generated
supply rail draw minimal or no quiescent current. The LDO regulator only needs to
supply a large current for a short period of time, i.e. when the gate capacitance of the
power NMOS transistor is charged through the pre-driver. Therefore, stability of the
regulation loop is to be ensured under light load conditions.
For the completeness of this discussion, the loop transfer function when operating under
heavy load conditions will be evaluated. Although, the internal regulator designed does
not operate under this condition during steady-state, the external LDO regulator catering
to external current load which adopts similar architecture does. Hence under the
condition when CL > 0
C
g m1 g mp ro1Roeq 1 + s c
g m3
R2
≈−
CC C r R
R1 + R2
1 + sg mpCc ro1Roeq + s 2C1CL ro1Roeq + s 3 1 c L o1 oeq
g m3
C
g m1 g mp ro1Roeq 1 + s c
g m3
R2
≈−
R1 + R2
C C
C
1 + sg mpCc ro1Roeq 1 + s 1 L 1 + s c
g mpCc
g m3
g m1 g mp ro1Roeq
R2
=−
R1 + R2
CC
1 + sg mpCc ro1Roeq 1 + s 1 L
g mpCc
(
)
(
)
(5.13)
It can be observed from (5.13) that the dominant and non-dominant poles of the loop
gain transfer function under heavy load conditions can be written as
p3 =
1
g mp ro1Cc Roeq
p4 =
g mpCc
C1CL
(5.14)
(5.15)
Using the cascode Miller frequency compensation method, the poles of the LDO
regulator are split as seen from (5.14) and (5.15), allowing the regulator to remain stable
when operating under heavy load conditions.
Since the purpose of the internal regulator is to supply an internal supply rail such that
the low-threshold transistors implemented in pre-driver for the power NMOS and the
level shifters can operate within the safe operating region, i.e. VGS less than 3.6V and
since these circuits are operating on the negative supply rail of VPSUB, meaning that
VSS_V33_EXT generated must be 3.4V with respect to VPSUB. Note that the internal supply
generated is designed to be only 3.4V above VPSUB instead of the maximum tolerable
voltage of 3.6V, so as to cater to variations due to process and temperature corners.
The LDO regulator requires a reference voltage which is process and temperature
independent so as to generate a stable regulated output. And since the regulated output
generated is supposed to be with respect to VPSUB, the reference input to the regulator
should also be at a fixed voltage above VPSUB so as to improve the negative supply
rejection at the output. However, the bandgap reference circuit introduced earlier
generates a process and temperature independent reference voltage with respect to
ground. Therefore a separate reference generator circuit has to be incorporated in the
design for this LDO regulator. Incorporating a bandgap reference circuit such as the one
presented in the earlier chapter will imply a significant increase in the quiescent current
consumption.
Due to the architecture selected for the bandgap reference presented earlier, the
reference voltage with respect to substrate voltage can be generated by making use of
the reference current generated. Recall that the output current of the bandgap circuit can
be written as
I ref =
VBE ∆VBE VBE VT ln(n )
+
=
+
R1
R2
R1
R2
(5.16)
where R1 and R2 are resistances of the resistors in the bandgap core. This current flows
through a resistor R3, of the same type as R1 and R2 and the resulting voltage is the
bandgap reference output. Since VBE has a negative temperature coefficient, through a
proper selection of the resistance ratio R3/R1 and R3/R2, the resulting output reference
4
voltage can then have a small temperature coefficient. In the earlier circuit, the output
current flows through R3 which is residing on ground, hence generating a 660mV
reference output with respect to ground. If the output current is mirrored and is made to
flow through R4 which is sitting on the substrate voltage, the required reference voltage
can then be generated. In doing so, only current mirrors and resistors are required in the
implementation of the reference voltage, hence greatly reducing the quiescent current
consumption and die area required. The reference generator implemented consumed a
small amount of current, about 342.5nA, generating a voltage of about 545mV with
respect to VPSUB. The reference generator together with the LDO regulator designed is
presented in figure 5-7.
5-7: Internal low-dropout regulator 1 with reference generator schematic
-
Since the buck-boost converter designed is to cater to a wide input supply range, it is
important to ensure that the internal supply rail generated is still within the maximum
tolerable operating voltage, i.e. 3.6V for the circuits as the substrate voltage changes
from -0.30V to -10.0V. Figure 5-8 shows the DC variation of VSS_V33_EXT and the
reference generator output as the substrate voltage changes across all process and
temperature corners. It can be observed from the results that variation of VSS_V33_EXT is
less than 10mV as the substrate voltage varies over the entire range. And across all
possible process and temperature corners, VSS_V33_EXT with respect to VPSUB does not
exceed 3.6V and is more than 3.2V under all conditions.
VSS
5-8: DC variation of VSS_V33_EXT and the reference generator output with VPSUB
-
The stability of the regulation loop can be verified by evaluating the frequency response
of the loop gain function. As the circuits operating off the internally generated VSS_V33_EXT
consume an insignificant amount of current, simulations on the frequency response of
the regulation loop are performed under no load conditions using different substrate
voltages. The internal regulator is designed for an external capacitive load of 100nF and
uses a compensation capacitor of only 4pF. The feedback resistance at the output of the
regulator is about 6.6M . Therefore, from (5.11), the dominant pole is expected to be
located at 0.241Hz. Figure 5-9 and 5-10 show the typical and worst case respectively,
frequency responses of regulation loop when VPSUB=-5.0V. It can be observed that
schematic and post-layout frequency responses are similar and that the regulation loop
has a typical open-loop DC gain of about 75dB and has a phase margin of more than 80
degrees typically. And it has a worst case phase margin of about 64 degrees. Also the
3dB frequency attained is close to the value calculated earlier.
-
-
–
–
-
-
5-9: Internal LDO 1 regulation loop response (V33=3.3V, VPSUB=-5.0V, Typical)
-
-
-
5-
–
–
-
-
: Internal LDO 1 regulation loop response (V33=3.3V, VPSUB=-5.0V, W.C)
Figures 5-11, 5-12 and 5-13 show the corner simulation results of the regulation loop
frequency response when VPSUB is -5.0V, -0.30V and -10.0V respectively under no load
conditions. It can be observed that for all three cases, the regulation loop has an openloop gain of more than 50dB under different possible process and temperature operating
conditions. The gain of the regulation loop drops slightly when VPSUB=-0.30V as the
dropout voltage of the pass device decreases, resulting in a slight drop in the gain of the
output common-source stage. From the frequency responses of the regulation loop, it
can be concluded that the LDO regulator is stable under the different conditions. The
results on the phase margin of the loop will be summarized in the table at the end of the
chapter. Under the condition when VPSUB=-10.0V, it was verified that the devices used in
the design of the LDO are able to withstand the high voltages across their terminals,
thereby reaffirming the reliability of the LDO regulator design.
-
5-
5-
: Internal LDO 1 regulation loop response (V33=3.3V, VPSUB=-5.0V, Corner)
: Internal LDO 1 regulation loop response (V33=3.3V, VPSUB=-0.30V, Corner)
-
5-
: Internal LDO 1 regulation loop response (V33=3.3V,VPSUB=-10.0V, Corner)
The negative supply rail of internal regulator 1 implemented is actually the substrate
voltage which is the input supply of the proposed buck-boost converter. Therefore, it is
important to evaluate the transient response in the generated VSS_V33_EXT when there is a
change in the substrate voltage. The generated VSS_V33_EXT should not exceed the
maximum threshold of 3.6V with respect to the substrate voltage which will affect the
reliability of the low-threshold transistors used in the design. Figure 5-14 shows the line
transient response of the LDO regulator as the substrate voltage changes between -5.0V
and -5.5V in 1ns. Using an external capacitor of 100nF, the variation in the regulator
output is observed to be less than 10mV at any instant. Figure 5-15 shows the line
transient response using the same line transient conditions but with different
combinations of process and temperature corner conditions. The generated VSS_V33_EXT
does not exceed 3.6V at any point when the substrate voltage changes.
-
VPSUB
VSS_V33_EXT
VSS_V33_EXT
5-
VPSUB
VPSUB
-
: Internal LDO regulator 1 line transient response (V33=3.3V, Typical)
VSS_V33_EXT
5-
: Internal LDO regulator 1 line transient response (V33=3.3V, Corners)
-
The substrate line transient response of the regulator has a close relationship to the
PSRR of the regulated output. Figure 5-16 shows the PSRR of the regulated output for
all the process and temperature corners when VPSUB=-5.0V. The LDO regulator exhibits
a good PSRR at its output and has a PSRR of more than 60dB at DC and more than
30dB across the entire frequency spectrum. High PSRR at the regulated output is also
observed over the entire input supply range.
5-
: Internal LDO regulator 1 PSRR (V33=3.3V, VPSUB=-5.0V, Corners)
In order to evaluate the regulator’s performance in the actual system, the internal
regulator 1 output transient response when the pre-driver operating off VSS_V33_EXT
switches on and off the power NMOS is observed through simulations. The simulation
setup includes the actual pre-driver, power NMOS transistor and also the bandgap
reference which generates the current reference used by the internal regulator. Figures
5-17 and 5-18 show the internal regulator 1 and pre-driver output transient responses as
the pre-driver switches at 100KHz under all process and temperature corner conditions.
The maximum output variation is observed to be less than 30mV and although the
regulator output takes a long time to settle down to the regulated voltage, due to low
bandwidth, it is sufficient as the converter does not switch at high frequency.
VSS_V33_EXT
5-
: Internal LDO 1 output transient response (VPSUB=-5.0V, Corners)
VSS_V33_EXT
5-
: Internal LDO 1 low to high output response (VPSUB=-5.0V, Corners)
-
Table 5-1 summarizes the simulated performance of the designed internal LDO regulator
1 under different possible operating conditions.
Internal Reference w/VPSUB (VPSUB=-5.0V)
0.512V
0.545V
0.559V
DC Gain (VPSUB=-0.30V, ILoad=0µA)
55.06dB
66.48dB
72.46dB
DC Gain (VPSUB=-0.30V, ILoad=50µA)
55.94dB
64.82dB
70.45dB
DC Gain (VPSUB=-5.0V, ILoad=0µA)
62.06dB
74.96dB
80.33dB
DC Gain (VPSUB=-5.0V, ILoad=50µA)
91.11dB
102.82dB
109.19dB
DC Gain (VPSUB=-10.0V, ILoad=0µA)
62.03dB
74.95dB
80.32dB
DC Gain (VPSUB=-10.0V, ILoad=50µA)
91.70dB
103.83dB
110.44dB
Phase Margin (VPSUB=-0.30V, ILoad=0µA)
66.91 deg
82.41 deg
88.03 deg
Phase Margin (VPSUB=-0.30V, ILoad=50µA)
67.20 deg
75.71 deg
82.77 deg
Phase Margin (VPSUB=-5.0V, ILoad=0µA)
68.37 deg
82.94 deg
88.11 deg
Phase Margin (VPSUB=-5.0V, ILoad=50µA)
69.17 deg
77.25 deg
83.67 deg
Phase Margin (VPSUB=-10.0V, ILoad=0µA)
69.10 deg
83.22 deg
88.18 deg
Phase Margin (VPSUB=-10.0V, ILoad=50µA)
69.81 deg
77.76 deg
83.99 deg
Bandwidth (VPSUB=-5.0V, ILoad=0µA)
0.166Hz
0.228Hz
0.814Hz
Bandwidth (VPSUB=-5.0V, ILoad=50µA)
0.046Hz
0.110Hz
0.417Hz
Quiescent Current (ILoad=0µA)
1.11µA
1.45µA
1.95µA
5-1: Internal LDO regulator 1 summarized simulated performance
-
CChhaapptteerr 66
Internal Low-Dropout Regulator 2
The internal power management scheme presented in the previous chapter comprises of
two internal LDO regulators. Both regulators serve the purpose of generating a regulated
supply rail so as to protect the circuits from exposing to high potentials. Previously, the
design of internal regulator 1 was discussed in detail. In this chapter, the other LDO,
internal regulator 2 which serves to power the startup circuitries will be presented.
6
Unlike internal regulator 1, this LDO regulator is powered by the VSS_VSUP supply rail
which effectively is the ground node of the buck-boost converter, resulting in a different
set of design challenges. As the buck-boost converter is designed to startup typically
with a minimum substrate voltage of -0.75V which can reach up to -10.0V, the LDO while
generating a regulated supply of less than 3.6V with respect to VPSUB, must be able to
withstand and operate with this wide input supply range. Hence the devices incorporated
in the design of the regulator must be carefully selected, ensuring that the maximum
tolerable voltages at their terminals are not violated. Besides that, since the regulator is
expected to be functional even before the buck-boost converter output V33 is boosted,
the generation of a reference voltage for the LDO regulator is a challenge. Previously,
the reference with respect to the substrate voltage is generated using the bandgap
reference which operates off the V33 supply rail. But this is impossible in this case, since
the bandgap reference is not available upon startup. However, the precision of the
regulated output for this regulator, VSS_V33_INT is not as critical as VSS_V33_EXT. For the
previous case, VSS_V33_EXT is designed to be about 3.4V above VPSUB typically and it
should not exceed 3.6V across all process and temperature corners. This implies that
the tolerable spread of VSS_V33_EXT cannot exceed 200mV under all conditions. The main
reason why VSS_V33_EXT is designed to be so close to the maximum threshold of 3.6V is to
reduce the on-resistance of the NMOS power transistor so as to improve on the
conversion efficiency since VSS_V33_EXT is the supply rail utilized when the buck-boost
converter is regulating. For the present case, since VSS_V33_INT is not used during
regulation, it will not affect the efficiency of the buck-boost converter. Although the
voltage level of VSS_V33_INT will ultimately affect the startup time required for the converter,
it is not a concern for the proposed design. Therefore, VSS_V33_INT can be designed to be
regulated at some voltage far below the maximum threshold, so long that it is sufficient
for the startup circuitries to operate. This allows for a larger spread in the reference
voltage used in regulating VSS_V33_INT, reducing the challenges involved in designing the
reference generator.
As mentioned earlier, the present LDO regulator will only be functional during startup
and it does not have any effect on the overall conversion efficiency of the proposed
buck-boost regulator. Therefore, the quiescent current consumption of the LDO regulator
is not a major concern here.
6.2
-
Since this internal LDO is to start operating upon startup of the buck-boost converter, the
bandgap reference operating off V33 is not available. Therefore a simple voltage
reference generator is required for this LDO. It should be able to operate with minimal
supply. However, its accuracy is not as important as that of the bandgap reference since
the main purpose of the LDO is to protect the startup circuitries from high potentials.
To reduce on the temperature dependence of the reference voltage, the generator
should be designed using components with opposite temperature coefficients. In
conventional bandgap reference circuits, the base-emitter voltage and the difference in
base-emitter voltages of two bipolar transistors with different current densities are used
to generate the reference voltage. However these circuits require a high supply voltage
and large area, thereby making them unsuitable for this application. In this case, the
simple reference generator designed uses the gate-source voltage of a diode-connected
transistor which has a negative temperature coefficient and the voltage across a highresistive poly resistor which has a positive temperature coefficient. These two voltages
are summed to generate the reference voltage which has less temperature dependence.
6.3
-
Figure 6-1 shows the schematic of the internal regulator 2 together with the reference
generator designed for the proposed chip. The simple reference generator consists of
the diode-connected transistor M6 and the resistor chain R0. A filtering capacitor
implemented using a MOS capacitor MC0 is included at the reference voltage so as to
minimize the disturbances introduced at the node. The error amplifier for the LDO
regulator is designed using I1, I2 and transistors M7 – M15. Since the voltage between
the two supply rails can potentially reach 10.0V, it is important to ensure that the
transistors used in the design are able to withstand the high voltages across their
terminals. For instance, the drain-source voltage of transistor M4 can be expressed as
VDS ,M 4 = −VPSUB − VGS ,M 9
(6.1)
And this voltage can be as high as 9.4V. Hence the transistor used to mirror the bias
current to the amplifier must be able to tolerate this voltage across its drain-source
terminal.
The internal regulator is implemented using three-stage operational amplifier
architecture. The input differential stage consisting of I1, I2 and transistors M7 – M10
forms the first stage while the differential to single-ended conversion implemented using
transistors M11 – M12 and M14 – M15 forms the second stage. The third stage is made
up by the common source output stage formed by the pass transistor M16. A feedforward path is included through M13 and it serves to improve the transient response at
the output. The feedback at the output of the regulator to the input of the error amplifier
is realized using the diode-connected transistors MR0 – MR3. The body terminals of
each of these transistors are connected to their respective sources so as to eliminate the
body effects. These transistors are placed close to each other to improve on matching.
6-1: Internal LDO reference and regulator 2 schematic
The first stage of the amplifier is similar to the input stage introduced in [32], [33] which
are designed to operate under very low supply voltage conditions. The current flowing
through the stage is defined by current source I1 and I2. The output common-mode
voltage is feedback through the gates of M9 and M10, ensuring that the same current
flows through M9 and M10 even when the input common-mode voltage causes the drain
voltages of the two transistors to fall below the required saturation voltage, thereby
reducing the required input common-mode voltage.
Conventional compensation techniques for low-dropout regulators which use 2-stage
error amplifiers involve using the zero introduced by the ESR of the output capacitor to
cancel the non-dominant pole at the gate of the pass transistor. However, imperfect
pole-zero cancellation and unpredictability of the resistance of the ESR will result in the
creation of a pole-zero doublets in the frequency response which will affect the transient
performance of the regulator. Besides that, the dominant pole at the output of the
regulator will shift with load conditions. For instance it will shift to a higher frequency at
heavy load conditions as the output resistance of the regulator decreases and since only
one pole can be cancelled, the stability of the regulator cannot be guaranteed at different
load conditions. Pole-control frequency compensation (PCFC) which is based on nested
Miller compensation [34-35] is introduced in [36]. The stability of the regulator utilizing
the PCFC technique is almost independent of the ESR of the filtering capacitor and the
stability is significantly improved under different load and temperature conditions.
The structure of the PCFC scheme is shown in figure 6-2. Error amplifier with two gain
stages is used to provide sufficient voltage gain and the pass transistor forms the third
stage. The transconductances of the stages are notated as gm(1-3). A nested Miller
compensation technique with feed-forward transconductance stage is used in this
scheme to split the poles. A feed-forward transconductance stage gmf2 is introduced to
optimize the stability of the structure and also to improve on the transient response of
the regulator during transient load conditions.
VPSUB
6-2: Structure of low-dropout regulator utilizing PCFC scheme [36]
The transfer function of the loop gain of the structure shown in figure 6-2 is derived in
[36]. The stability of the low-dropout regulator is achieved at no load conditions and the
stability criteria are obtained by considering that the poles of the loop gain has thirdorder Butterworth frequency response in unity-feedback configuration. Defining
m=
g mf 2
gm2
(6.2)
kg =
gm2
g m 3q
(6.3)
where gm3q is defined as transconductance of the pass transistor under no load condition.
The dimension conditions of the compensation capacitors are given by
Cm1 =
R f 2 g m1
4
CL
1 + k g (m − 1) R f 1 + R f 2 g m3q
Cm 2 =
gm2
CL
2
1 + k g (m − 1) g m3q
[
4
]
(6.4)
(6.5)
Using (6.4) and (6.5), the compensation capacitors to be implemented can be
approximated. It should be noted from figure 6-1 that capacitor Cm2 is implemented using
a different type of capacitor due to the possible high potential which can exist between
its two terminals while Cm1 is designed using the normal poly capacitor.
6.4
-
6.
-
The stability of the internal LDO is verified by evaluating the frequency response of the
regulation loop. And since the LDO will predominantly operate in very light load condition,
its stability will be particularly important in this condition. Figures 6-3 and 6-4 show the
frequency responses of regulation loop under no-load condition and when VPSUB is -5.0V
for typical and corner process conditions respectively. In these simulations, the power
NMOS driver’s input is ‘high’ such that the internal regulator output is connected to the
large gate capacitance of the power NMOS. This will effectively shift the non-dominant
pole at the output to a lower frequency so that the phase margin will be degraded. It can
be observed that the regulation loop has a DC gain of about 125dB and phase margin of
more than 72 degrees under typical process condition and it has an open-loop DC gain
of more than 95dB under all process corner conditions.
-
-
-
–
-
–
-
6-3: Internal LDO 2 regulation loop frequency response (VPSUB=-5.0V, Typical)
6-4: Internal LDO 2 regulation loop frequency response (VPSUB=-5.0V, Corner)
Figures 6-5 shows the frequency response when the power NMOS driver’s input is ‘low’.
As regulator output is disconnected from the large gate capacitance, the non-dominant
pole will be shifted to higher frequency and the phase margin improves as observed
below.
-
-
-
–
-
–
-
6-5: Internal LDO 2 regulation loop frequency response (PreDrvN=0V, Typical)
6
2
-
As mentioned earlier, the voltage reference generator implemented is expected to
exhibit a large variation across all process and temperature variations. And since the
main purpose is to limit the voltage for which the startup circuitries are exposed to, it is
important to ensure that the internal supply rail generated is within 3.6V with respect to
VPSUB. Figure 6-6 shows the internal LDO output variation with VPSUB. It can be observed
that the output ranges between 2.1V and 3.4V, thereby verifying that the circuits operate
off this supply rail are protected from the high input substrate voltage.
6
3
-
Although the internal regulator is operational only during startup of the buck-boost
converter, before the output V33 reaches the under-voltage threshold, the internal LDO
transient response to substrate voltage variation during this period is still important so as
to ensure that the startup operations are not affected.
-
V
T
6-6: Internal LDO 2 output variation with VPSUB (No Load, Corners)
Figures 6-7 and 6-8 show the (typical and process corners respectively) transient
responses (schematic and post-layout) of the reference input and internal regulator’s
output generated when the VPSUB changes between -5.0V and -5.5V. It can be observed
that the post-layout view exhibits slightly worse transient response but in both cases, the
maximum variation observed is less than 100mV of the nominal value.
V
F
T
-
-
6-7: Internal LDO 2 reference and output line transient (VPSUB=-5.0V, Typical)
-
V
T
6-8: Internal LDO 2 reference and output line transient (VPSUB=-5.0V, Corners)
6
4
The power NMOS driver uses VSS_V33_INT during startup to drive the large gate
capacitance of the NMOS. Figure 6-9 shows the transient responses of the regulator
output and power NMOS driver output when VPSUB=-5.0V. Although the regulator
displays slightly worse response in post-layout view, the output is observed to settle
down before the power NMOS is switched on again for both views.
V
T
V
V
V
T
-
-
)
6-9: Internal LDO 2 and power NMOS driver transient (VPSUB=-5.0V, Typical)
6
2
Table 6-1 summarizes the simulated performance of the designed internal regulator 2
under different possible operating conditions.
VSS_V33_INT w/VPSUB (VPSUB=-5.0V)
2.127V
2.865V
3.368V
DC Gain (VPSUB=-3.8V, ILoad=0µA)
96.33dB
123.94dB
134.19dB
DC Gain (VPSUB=-5.0V, ILoad=0µA)
96.25dB
124.49dB
135.34dB
DC Gain (VPSUB=-10.0V, ILoad=0µA)
95.13dB
124.30dB
134.61dB
Phase Margin (VPSUB=-3.8V, PreDrvN=’0’)
72.64 deg
79.73 deg
83.34 deg
Phase Margin (VPSUB=-3.8V, PreDrvN=’1’)
68.16 deg
76.63 deg
81.14 deg
Phase Margin (VPSUB=-5.0V, PreDrvN=’0’)
72.82 deg
79.81 deg
83.36 deg
Phase Margin (VPSUB=-5.0V, PreDrvN=’1’)
68.44 deg
76.71 deg
81.15 deg
Phase Margin (VPSUB=-10.0V, PreDrvN=’0’)
72.22 deg
79.59 deg
83.15 deg
Phase Margin (VPSUB=-10.0V, PreDrvN=’1’)
67.87 deg
76.28 deg
80.78 deg
Bandwidth (VPSUB=-5.0V)
0.070Hz
0.356Hz
9.036Hz
Quiescent Current (ILoad=0µA)
33.03µA
67.41µA
107.20µA
6-1: Internal LDO regulator 2 summarized simulated performance
-
CChhaapptteerr 77
External Low-Dropout Regulator
In order to reduce standby power consumption so as to improve on the overall energy
efficiency of the portable devices, effective power management techniques are
becoming more important in recent years. Low-dropout regulators (LDOs) provide
regulated low-noise and precision supply voltage and are one of the most common
power management modules found in modern portable devices. In order to prevent
accidental resetting of the device and malfunction of circuits operating off the regulated
supply generated by LDOs, good load transient response with minimal output voltage
overshoots or undershoots is a critical performance indicator for LDOs. In order to
achieve a high current efficiency for LDOs powering applications with ultra-low power
consumption, the no-load quiescent current of the regulator must be kept minimal.
In the proposed chip, an isolated LDO regulator is included to provide an externally
available supply rail targeted to power ultra-low power applications such as a biomedical
front-end acquisition chip. The regulator is specified to provide a regulated 1V supply
which is externally tunable through the feedback resistors, for a load current up to 2mA.
Also, it is expected to operate in two different modes. One of which is to operate off the
buck-boost converter regulated output of 3.3V when the converter is enabled. In another
mode, when the buck-boost converter is disabled, the proposed chip caters to a single/
double AA battery supply connected to the V33 pin. In this case, the LDO regulator is
required to provide a 1.0V supply even as the AA battery voltage drops to as low as 1.2V.
Under this mode, only the current reference, bandgap reference and isolated LDO
regulator are expected to operate while the other blocks are disabled. Since the LDO
regulator is specified to deliver relatively light current load, the no-load quiescent current
of the LDO must be minimized. In doing so, the closed-loop bandwidth of the regulator
will be limited. As a result, the load transient response of the LDO, in particular the
maximum output voltage variation will be affected according to
∆Vout,max =
I L,max
CL
∆t1 + ∆VESR
(7.1)
Where IL,max is the maximum load current, CL is the output capacitance, VESR is the
voltage variation resulting from the presence of a finite equivalent series resistance in
the capacitor chosen and t1 corresponds to the closed-loop bandwidth of the LDO
regulator. From (7.1), the maximum output voltage variation during load transient can be
minimized by using an external large filter capacitor at the regulated output. However,
this poses design challenges in compensating the regulation loop. Since the isolated
LDO regulator is supposed to provide a regulated supply for some external load, no
additional resources is required to incorporate the external load capacitor.
The intermediate buffer for internal regulator 1 is implemented using a PMOS sourcefollower with shunt feedback. And since the output voltage swing of the folded-cascode
error amplifier is given by 2VDSAT, the PMOS input stage of the source-follower together
with the pass transistor results in higher voltage headroom which can be expressed as
Vin ≥ 2VGS + 2VDSAT
(7.2)
However, this may not be sufficiently low especially under corner conditions since the
external regulator is expected to operate at 1.2V. The main reason for the high voltage
headroom required for internal regulator 1 is the PMOS source-follower stage. If the
PMOS source-follower is replaced by one with a NMOS input stage, the voltage
headroom required will be reduced to
Vin ≥ VGS , P − VGS , N + 2VDSAT
(7.3)
where VGS,P refers to the gate-source voltage of the pass transistor and VGS,N is the gatesource voltage of the NMOS input of the source-follower. The source-follower included in
the architecture of the LDO regulator serves the purpose of reducing the resistance at
the gate node of the pass transistor. Hence shifting the non-dominant pole located at this
node to beyond the unity-gain frequency of the regulation loop. A simple source-follower
with a output resistance in the order of 1/gm does not shift the pole location to a
sufficiently high frequency, given the requirement to keep the quiescent current of the
LDO low. Therefore a source-follower with shunt feedback is introduced in internal
regulator 1. Since a NMOS source-follower is required in this case, the low output
resistance intermediate buffer stage will be redesigned. One direct method in deriving
the desired source-follower is to ‘flip’ the PMOS source-follower as shown in figure 7-1.
In this case, the shunt feedback is realized using transistor M2. However, although this
buffer has a good sourcing capability, and hence able to turn off the pass transistor
quickly during a load transient event, the pass device gate terminal will face slew rate
limitation when it is being pulled down. The slew rate at the buffer output is given by
dVout
I
= 1
dt
Cout
(7.4)
Where Cout is the equivalent node capacitance at the pass transistor’s gate and I1 is
determined by current source I1. Therefore, in order to ensure that the LDO regulator
displays a good load transient response, a significant amount of current must flow
through the current source.
7-1: Direct implementation of NMOS source-follower with shunt feedback
Figure 7-2 shows an alternative method in implementing the intermediate buffer for the
external regulator. The modified buffer follows the folded-cascode architecture which is
often used to reduce voltage headroom required. The shunt feedback which serves to
reduce the output resistance is implemented using I1, M3 and M2. This buffer improves
the slewing of the gate of the pass device during load transients. During the transition
from no load to full load, the decrease in the input voltage of the buffer causes the
source node of M3 to increase. Subsequently, the gate to M2 will increase, resulting in
the output node of the buffer to be pulled down, discharging the large gate capacitance
at the output node with little slew rate limitations. Similarly, when the buffer input voltage
increases, the diode-connected PMOS will provide extra transient current to charge the
gate capacitance, increasing the gate voltage with a faster slewing during full load to no
load transition.
-
7-2: Folded-cascode implementation of source-follower with shunt feedback
The output resistance of the modified buffer can be approximated and its magnitude is of
the same order as the PMOS source-follower implemented in the internal regulator. The
output resistance can be approximated as
rob ≈
1
(
g m,1 g m,2 ro,3 ro,5
)
(7.5)
By using the folded-cascode form of intermediate buffer, the voltage headroom of the
LDO regulator can be reduced and the low supply voltage specifications of the external
regulator can be satisfied. The external LDO regulator error amplifier and compensation
method follows that of the internal regulator. As such, the transfer function of the
regulation loop for the external LDO is the same as that derived earlier. Under no load
conditions, the regulation loop transfer function can be approximated to
-
T (s ) I L ~0 ≈ −
g m1 g mp ro1Roeq
R2
R1 + R2 1 + sCL Roeq (1 + sC1ro1 )
(
)
(7.6)
The two poles are given by
p1 =
1
CL Roeq
(7.7)
p2 =
1
C1ro1
(7.8)
In this case, the dominant pole is determined by the output node and no pole splitting
had occurred. In order to ensure that the non-dominant pole p2 falls beyond the unitygain frequency, it is important to keep the input capacitance of the buffer small. Unlike
the case of the internal regulator which normally operates under no load condition, the
external LDO is required to cater to a current load up to 2mA. Under this condition, the
pole locations might deviate from that approximated by (7.7) and (7.8) and they may be
better approximated using the regulation loop transfer function given by
T (s ) I L >> 0 ≈ −
R2
R1 + R2
g m1 g mp ro1Roeq
(1 + sg
mp Cc ro1Roeq
c
)1 + s gC CC
1 L
mp
(7.9)
It can be observed from (7.9) that the dominant and non-dominant poles of the loop gain
transfer function under heavy load conditions can be written as
p3 =
1
g mp ro1Cc Roeq
p4 =
(7.10)
g mpCc
C1CL
(7.11)
Using the cascode Miller frequency compensation method, the poles of the LDO
regulator are split in this case, thereby ensuring stability under heavy load conditions.
Figure 7-3 shows the schematic of the external LDO regulator implemented in the
proposed power management chip. The error amplifier is implemented using a P-input
stage folded-cascode amplifier. The input common-mode range of this amplifier fulfils
the requirement of taking in two different reference voltages of 250mV and 660mV in the
two available modes. Also it can be observed that a simple active current load is used
for the output stage of the amplifier, this effectively reduces the output resistance of the
amplifier so as to shift the non-dominant pole depicted by (7.8) to higher frequencies
under no load conditions.
7-3: External low dropout regulator schematic
-
As mentioned earlier, the external LDO regulator operates in two different modes and
therefore the stability of the regulation loop must be verified by evaluating the frequency
response of the loop gain function in each of the two modes with different current loads.
Also, the external LDO caters to a wide range of external filter capacitor values, from
470nF to 4.7µF, so depending on the specifications on maximum output voltage
variation during load transients, the appropriate capacitor can be selected. The
simulation results presented in this section only include those using an output capacitor
of 1µF, while results pertaining to the other capacitor values will be summarized at the
end of the chapter. Figures 7-4 and 7-5 show the frequency responses (schematic and
post-layout) of the regulation loop gain when the buck-boost converter is disabled and
V33=1.2V under no load and maximum current load (ILoad=2mA) conditions respectively.
It can be observed that the schematic and post-layout frequency responses are similar
and the phase margins obtained are more than 80 degrees for both cases.
-
-
–
-
–
-
7-4: External LDO regulation loop response (V33=1.2V, ILoad=0mA, Typical)
-
-
-
–
–
-
-
7-5: External LDO regulation loop response (V33=1.2V, ILoad=2mA, Typical)
Besides that, the open-loop gain of the regulation loop decreases by about 10dB from no
load to maximum load. This can be explained using (7.6) and (7.9) as the gain is
dependent on Roeq which is the output resistance (inversely proportional to output current)
of the LDO regulator. Under no load conditions, the output resistance of the LDO is
about 500K , determined by the feedback resistors and given that load capacitance is
1µF, the dominant pole is located at about 0.3Hz according to (7.7). However, the
bandwidth of the regulation loop becomes wider in the case when load current increases
to 2mA as the dominant pole shifts to a higher frequency due to lower output resistance
according to (7.7) and (7.10). This explains the need for the diode-connected PMOS
within the buffer to track the output load current so as to correspondingly lower the buffer
output resistance and shift the non-dominant pole located at the gate of the pass device
to a higher frequency as load increases. Figures 7-6 and 7-7 show the frequency
responses of the regulation loop when the buck-boost converter is disabled, i.e.
V33=1.2V under all possible process and temperature corner situations. The regulation
loop has an open-loop gain of more than 40dB and is verified to be stable under all
conditions.
7-6: External LDO regulation loop response (V33=1.2V, ILoad=0mA, Corners)
7-7: External LDO regulation loop response (V33=1.2V, ILoad=2mA, Corners)
Figures 7-8 and 7-9 show the frequency responses (schematic and post-layout) of the
regulation loop gain when the buck-boost converter is enabled and when V33=3.3V,
VPSUB=-5.0V under no load and maximum current load (ILoad=2mA) conditions
respectively. It can be observed that the frequency responses for both schematic and
post-layout views are similar and the open-loop gain of the regulation loop increases
slightly from 59dB in the previous case to 63dB. This is mainly due to the increase in
drain-source voltage across the pass device. Also, the phase margins for the two
frequency responses are determined to be more than 76.5 degrees, thereby verifying the
stability of the loop. The slight degradation in phase margin of the post-layout frequency
response under maximum current load conditions is mainly due to the increase in stray
capacitances at the input of the buffer. This shifts the non-dominant pole to a lower
frequency according to (7.11), thereby reducing phase margin by about 5 degrees.
-
-
–
-
–
-
7-8: External LDO regulation loop response (V33=3.3V, ILoad=0mA, Typical)
Next, the external LDO regulation loop frequency response when buck-boost converter
is enabled is simulated under all process and temperature corner conditions. And the
results are presented in figures 7-10 and 7-11. From the results, it is observed that the
regulation loop has an open-loop gain of more than 50dB under all conditions and the
loop is verified to be stable.
-
-
–
–
-
-
7-9: External LDO regulation loop response (V33=3.3V, ILoad=2mA, Typical)
7-
: External LDO regulation loop response (V33=3.3V, ILoad=0mA, Corners)
-
7-
: External LDO regulation loop response (V33=3.3V, ILoad=2mA, Corners)
Under the mode when the buck-boost converter is disabled, the external LDO is
supposed to operate with a single AA battery as its supply while in the case when the
converter is “on” the external LDO operates from the converter output V33. However, the
supply voltage from the battery can vary and deviate from its typical value of 1.5V. Also,
the converter output can change depending on the configuration of the resistor feedback
network. Therefore it is important to verify the performance of the regulator over a range
of supply voltages. Figure 7-12 shows the external LDO output variation as the supply
varies from 1.2V to 1.8V under no load conditions for all process and temperature corner
situations when the buck-boost converter is disabled. It can be observed that the
external LDO output exhibits very slight variation as the supply V33 changes from 1.2V
to 1.8V, thereby showing that the LDO designed has a good line regulation performance.
-
7-
: DC variation of external LDO output with V33 when converter is disabled
The supply to the external LDO may be shared with other circuits in the system and the
inherent ripple in the output of an inductive buck-boost converter implies that it is
important to evaluate the external LDO output line transient response. Figures 7-13 and
7-14 show the line transient responses (schematic and post-layout) of the external LDO
using different output capacitor values as V33 changes between 1.2V and 1.5V when
the converter is disabled. It can be observed that the magnitude of the output variation is
the largest when the smallest capacitor of 470nF is used. However, in this case, the
output settles in a shorter time. Also the output variation observed is slight larger for the
post-layout case. But for all the cases presented, the magnitude of the output variation is
less than 1.5mV and the regulated output settles to within one percent of its final values
in a very short time, showing that the external LDO exhibits good line transient response.
-
(
-
)
E
(
7-
-
: External LDO regulator line transient response (V33=1.2V to 1.5V, Typical)
5
2
5
-
(
(
7-
)
2
)
-
)
: External LDO regulator line transient response (V33=1.5V to 1.2V, Typical)
Similarly, figures 7-15 and 7-16 show the line transient responses (schematic and postlayout) of the external LDO using different output capacitor values as V33 changes
between 3.0V and 3.3V when the converter is enabled and under no current load
condition. The schematic and post-layout line transient responses observed are similar.
And from the simulation results, it can be observed that the LDO regulator has the
fastest line transient response when using the smallest output capacitor and that the
regulated output variation is less than 1.5mV in all cases.
3.0
3.3
3.0
-
(
3.3
)
(
7-
-
: External LDO regulator line transient response (V33=3.0V to 3.3V, Typical)
3.3
3.0
(
3.3
-
(
7-
)
3.0
)
-
)
: External LDO regulator line transient response (V33=3.3V to 3.0V, Typical)
-
The external LDO regulator is designed to provide a regulated supply for ultra-low power
applications such as the biomedical front-end acquisition chip. These applications
typically consume an insignificant amount of current for most of the time and will
consume the maximum current only during transient events. Hence it is important to
evaluate the load transient response of the designed LDO regulator and to verify that the
maximum output voltage variation observed during these events is within the tolerable
supply voltage range for the applications which are powered. Figures 7-17 and 7-18
show the external LDO load transient response when its load current switches between
0 and 2mA under the condition in which the converter is disabled. It can be seen that the
maximum output voltage variation observed decreases as the output capacitance
increases, as predicted by (7.1). Some ringing is observed in the regulated output
voltage profile as the load current increases from 0mA to 2mA for the case when a
470nF capacitor is used. But the output eventually settles down to a stable 1.0V.
(
(
7-
-
-
)
)
: External LDO load transient response (V33=1.2V, ILoad=0mA to 2mA, Typ)
-
-
(
(
7-
-
)
)
: External LDO load transient response (V33=1.2V, ILoad=2mA to 0mA, Typ)
Similarly, performing the same simulation on the external LDO regulator but under the
mode when the buck-boost converter is enabled, the load transient responses of the
LDO are obtained as shown in figures 7-19 and 7-20. The results observed are similar to
that of the previous mode.
(
(
7-
-
-
)
)
: External LDO load transient response (V33=3.3V, ILoad=0mA to 2mA, Typ)
-
(
(
7-
-
-
)
)
: External LDO load transient response (V33=3.3V, ILoad=2mA to 0mA, Typ)
Table 7-1 summarizes the simulated performance of the designed external LDO
regulator under different possible operating conditions.
DC Gain (ILoad=0mA, CL=1.0µF)
50.24dB
60.27dB
66.20dB
DC Gain (ILoad=2mA, CL=1.0µF)
42.09dB
49.79dB
54.91dB
Phase Margin (ILoad=0mA, CL=0.47µF)
81.93 deg
87.49 deg
89.75 deg
Phase Margin (ILoad=0mA, CL=1.0µF)
85.63 deg
88.78 deg
89.97 deg
Phase Margin (ILoad=0mA, CL=2.2µF)
87.92 deg
89.46 deg
90.08 deg
Phase Margin (ILoad=0mA, CL=4.7µF)
88.98 deg
89.77 deg
90.13 deg
Phase Margin (ILoad=2mA, CL=0.47µF)
83.41 deg
89.36 deg
90.37 deg
Phase Margin (ILoad=2mA, CL=1.0µF)
76.13 deg
86.89 deg
88.89 deg
Phase Margin (ILoad=2mA, CL=2.2µF)
66.49 deg
82.48 deg
86.03 deg
Phase Margin (ILoad=2mA, CL=4.7µF)
58.94 deg
76.88 deg
81.71 deg
-
Bandwidth (ILoad=0mA, CL=1.0µF)
0.330Hz
0.345Hz
0.359Hz
Bandwidth (ILoad=2mA, CL=1.0µF)
19.76Hz
40.10Hz
102.10Hz
Quiescent Current (ILoad=0mA)
2.78µA
3.01µA
3.35µA
DC Gain (ILoad=0mA, CL=1.0µF)
52.00dB
63.61dB
70.53dB
DC Gain (ILoad=2mA, CL=1.0µF)
55.59dB
60.85dB
64.83dB
Phase Margin (ILoad=0mA, CL=0.47µF)
82.87 deg
88.19 deg
89.73 deg
Phase Margin (ILoad=0mA, CL=1.0µF)
86.36 deg
89.15 deg
89.95 deg
Phase Margin (ILoad=0mA, CL=2.2µF)
88.29 deg
89.63 deg
90.06 deg
Phase Margin (ILoad=0mA, CL=4.7µF)
89.19 deg
89.84 deg
90.10 deg
Phase Margin (ILoad=2mA, CL=0.47µF)
85.07 deg
88.82 deg
91.14 deg
Phase Margin (ILoad=2mA, CL=1.0µF)
76.85 deg
83.24 deg
87.57 deg
Phase Margin (ILoad=2mA, CL=2.2µF)
66.58 deg
74.68 deg
80.72 deg
Phase Margin (ILoad=2mA, CL=4.7µF)
56.84 deg
66.83 deg
75.05 deg
Bandwidth (ILoad=0mA, CL=1.0µF)
0.319Hz
0.329Hz
0.337Hz
Bandwidth (ILoad=2mA, CL=1.0µF)
16.13Hz
30.28Hz
58.22Hz
Quiescent Current (ILoad=0mA)
2.82µA
3.04µA
3.39µA
7-1: External LDO regulator summarized simulated performance
-
CChhaapptteerr 88
Regulatory Control Circuitries
Once the output of the buck-boost converter reaches approximately 2.2V, the regulatory
system takes over the control of the converter. The regulatory system serves the
purpose of controlling and regulating the output so long as the converter is operating
within the designed input supply range or current load. Numerous types of control
systems have been designed for use in dc-dc converters. Each with its own set of
advantages and disadvantages. For instance, voltage-mode PWM control which is one
of the most popular control schemes is known to be less efficient in light load conditions.
Hence it is mostly implemented for converters operating in heavy current load conditions.
The proposed buck-boost converter is designed for low power applications. Hence in
order to improve on the conversion efficiency of the converter under light current load
conditions, it is important to control on the quiescent current consumption of the
converter during regulation. Therefore, the regulatory control scheme designed for the
converter must not be too complicated. Voltage-mode PWM control provides a good
quality regulated output since the output with known harmonics, i.e. due to the fixed
frequency of the internally generated PWM can be filtered out with appropriate choice of
the inductor and output capacitor. However, it involves quite a number of circuitries, such
as error amplifier, comparator and oscillator. Furthermore, in order to reduce on the size
of the external components chosen as filter, the PWM must be operating at a high
frequency, resulting in larger power consumption. As a result, most commercial dc-dc
-
converters [37] are designed with dual mode control so as to cater to a wide range of
current load. Under light load conditions, these converters operate in Pulse Frequency
Modulation (PFM) mode while in heavy load conditions, the converter will switch to
operate in PWM mode.
In PFM mode, the output is regulated by varying the frequency of the converter, i.e.
under light load conditions, the dc-dc regulator will switch at low frequency and vice
versa. Hence the power consumption of the converter will reduce with the current load,
resulting in improved conversion efficiency under this operating condition. However,
quality of the output will suffer since harmonics observed at the output will change with
different load conditions. Also as mentioned in Chapter 2, since the open-loop
relationship between the input and output is independent on the operating frequency
when the converter is operating in CCM, control schemes based on PFM will not be able
to regulate the output once the load conditions result in CCM operation.
Since the proposed converter is designed for low power applications, control schemes
based on PFM operations are more suited for implementation. If a wider range of current
load conditions is to be supported, both modes can be incorporated. As a result, the
maximum load for the designed converter is limited by both the DCM-CCM boundary
condition as well as its efficiency.
Numerous control schemes based on PFM operations have been developed over the
years. They include hysteretic voltage control, pulse skipping, etc. In this case, a simple
regulatory system is implemented. The key blocks in the regulatory system include the
-
adaptive on-time generator, anti-backflow control system, regulatory comparator and
drivers to the power transistors. Majority of the circuitries in the control system operate
using the output regulated V33. Only the level shifter and driver for the NMOS power
transistor operate with the internal VSS_V33_EXT supply rail mentioned in Chapter 5.
The regulatory process is initiated by the regulatory comparator which compares the
scaled down output voltage with the bandgap reference. When the regulated output falls
below the bandgap reference voltage, the regulatory comparator goes high and initiates
a charging cycle via the adaptive on-time generator which controls the on-time of the
power NMOS and indirectly dictating the inductor current peak. Details on the design of
the adaptive on-time generator will be discussed in Appendix A. Once the inductor
current reaches a pre-determined level, the power NMOS will be switched off and the
charges stored in the inductor will be discharged and transferred to the output capacitor
through the external diode and the power PMOS which will be turned on. The antibackflow system controls the on-time for the PMOS transistor and serves the purpose of
preventing the charges stored from flowing back to the inductor. This happens if the
PMOS power transistor is still turned on after the inductor current discharges to zero. If a
significant amount of charges backflows to the inductor, the efficiency of the converter
will be affected. Details on the design and operations of the anti-backflow system will be
discussed in the following chapter. As the output capacitor is charged, the regulated
output will be boosted, resulting in the regulatory comparator output to go low, ending
the charging cycle. Some of the key waveforms attained during this process can be
observed in figures 2-4 and 2-5 presented earlier. In this chapter, the design of the
regulatory comparator will be discussed.
-
As mentioned earlier, the regulatory comparator monitors the output voltage and triggers
a new charging cycle whenever the output voltage falls below the threshold. As a result,
the performance of the comparator affects both the accuracy and the ripple magnitude of
the regulated output. In particular, the speed of the comparator plays an important role in
determining the performance of the buck-boost converter. A high gain comparator which
has a small delay will in general result in a smaller output ripple voltage and a more
accurate output.
There are many ways to realize a comparator and using an amplifier in open-loop
configuration is one of the simplest methods. The amplifier is configured in open loop so
as to retain the high open-loop gain property of the amplifier. However, in such
configuration, the bandwidth of the amplifier is very low. And since the linear settling time
of amplifier is proportional to its bandwidth, the speed of the resultant comparator is very
slow. This problem can be solved by cascading low open-loop gain but high bandwidth
amplifiers in series to obtain the desired properties of a comparator. But as a result, the
power consumption of such a comparator is expected to be very high. Taking into
consideration, the conversion efficiency of the converter at very light load conditions and
also the fact that the comparator is always enabled as it monitors the output, this
implementation is not feasible.
Regenerative comparators present an alternative method to implement the regulatory
comparator. They comprise of a pre-amplifier, regenerative circuit and a latch at the
output. Regenerative comparators typically consume less current as compared to the
methods discussed earlier since the regenerative circuit does not consume static power
-
once its output settles to a valid logic level, i.e. only the pre-amplifier consumes static
power. However, such comparators require an internal clock signal which controls the
track and latch phase of the regenerative circuit and for the regenerative comparators to
be of high speed, this clock signal generated must be of high frequency. Traditional onchip oscillators such as the ring oscillator implemented using an inverter chain typically
consume a significant amount of current and this may negate the benefits and
advantages of using a regenerative comparator. In order to make the proposition of
using regenerative comparator to implement the regulatory comparator attractive, it is
important to keep the power consumption of the on-chip clock generator low and currentstarved ring oscillators seem to be a viable solution to generate the signal. Using a
current-starved ring oscillator and a regenerative comparator, a high-gain comparator
with considerable speed can be implemented using limited power.
Like most on-chip oscillators without using any external components, the variation of the
oscillating frequency will be large across the different operating conditions. Therefore, it
is important that the design of the comparator caters to these variations and it can be
expected that the accuracy and the ripple magnitude at the output will change with the
oscillating frequency.
As mentioned earlier, an internal clock signal is required to control the track and latch
phase of the regenerative comparator. In order to lower the power consumption, a
current-starved ring oscillator similar to the one implemented in the startup circuitries is
used to generate the required signal. Figure 8-1 shows the schematic of the currentstarved ring oscillator implemented in the regulatory system.
-
8-1: Regulatory system current-starved ring oscillator schematic
The frequency of the ring oscillator is basically determined by the current-starved
inverter chain formed by transistors M8 to M17 i.e. delay when charging, determined by
the on-resistance of the PMOS and the gate capacitances and delay when discharging
depending on the limited current source I0 and gate capacitances. The output from the
current-starved inverter chain is not rail-to-rail due to the current source I0. However, the
introduction of NMOS with thicker gate oxide within the inverter chain ensures that the
output of the chain is low enough to turn on the PMOS transistor M22 at the output. In
order to make the output of the oscillator compatible to the other logic gates, gain stages
and inverters formed by transistors M22 - M26 are introduced to boost the output of the
oscillator to be rail-to-rail. The delay formed by the inverter chain is dominated by the
discharging phase due to the fact that the discharging current is limited by current
-
source I0. The time taken to discharge gate capacitances and other parasitic
capacitances at each node can be written as
Tdis = C g
VDD − VSP
I dis
(8.1)
where Cg is the capacitances at the node, VSP is threshold of the inverter and Idis is the
discharging current available for the particular inverter. It should be noted that the
current sourced by I0 is split between inverters which are in discharging phase within the
chain. It can be concluded from (8.1) that the discharging time is process dependent as
the threshold of the inverter changes with different process corners. As a result, it can be
expected that the oscillating frequency is process dependent. Since the oscillating
frequency is dependent on the capacitances at the internal nodes of the inverter chain, it
is important to take into consideration the parasitic capacitances introduced by routings.
As such, post-layout simulations are necessary to verify the oscillating frequency.
Through appropriate sizing of the transistors of the output gain stages, the duty cycle of
the ring oscillator output can be adjusted. In this case, the on-time of the ring oscillator
output is implemented to be more than 50 percent, i.e. 65 percent so as to allow for a
longer tracking phase, thereby reducing on the bandwidth requirements of the
preamplifier in the regenerative comparator. By doing so, the quiescent current
consumption of the preamplifier can be reduced as shown in the next section. It should
be noted that the output voltage ripple is only dependent on the frequency of the ring
oscillator which affects the frequency at which the output is sampled. Increasing the ontime of the oscillator does not affect the magnitude of the ripple at the converter output.
Also two switches are added to the output of the oscillator which will allow the digital
-
control of the buck-boost converter to control the state of the oscillator’s output, either
low or high.
Figure 8-2 shows the schematic of the regenerative comparator designed for regulating
the output of the buck-boost converter. It comprises of a preamplifier, a regenerative
latch and a SR latch. The comparator compares the output (scaled down by resistive
network) with the internal bandgap reference. The preamplifier serves the purpose of
tracking the inputs to the comparator and provides a small gain on the input difference
so as to improve on the resolution of the comparator. It also reduces the kick-back noise
which will “disturb” the bandgap reference and cause problems to other circuitries using
the same reference. Also, the noise will cause problems in the sensing of the output
through the resistor network, resulting in unexpected output voltage profile. The kickback noise is introduced by the regenerative latch during switching and through using a
high-gain preamplifier which connects the input to the latch kick-back noise can be
significantly reduced. However, a high-gain amplifier typically has a low bandwidth for a
given quiescent current consumption. This results in a longer settling time for the
preamplifier which implies that the comparator speed is slower since the comparator
needs a longer tracking phase. Often, the preamplifier is designed with a smaller gain so
as to achieve wider bandwidth such that the kick-back noise is reduced by a smaller
extent but improving on the comparator speed. The preamplifier designed has an openloop gain and bandwidth approximated by
Av, preamp =
g m,n
g m, p
(8.2)
-
p−3dB, preamp =
g m, p
CL
(8.3)
Where gm,n is the transconductance of the NMOS input differential pair, gm,p is the
transconductance of the diode-connected PMOS load and CL is the load capacitance of
the preamplifier which includes gate capacitance of the regenerative latch. Hence it can
be observed that the bandwidth can be increased by increasing the aspect ratio of the
diode-connected PMOS or the bias current such that gm,p increases.
However, increasing the aspect ratio not only increases the parasitic load capacitance at
the output but it also reduces the gain. Compromises have to be made so as to achieve
the gain and bandwidth required given a limited bias current. In this case, the gain is
designed to be about 12dB and the bandwidth must be greater than 1.88MHz in order
for the preamplifier to settle to within 0.1% of its final value within the minimum track
period generated by the oscillator under all conditions, i.e. 584ns. At the end of the
tracking phase, the regenerative latch uses the magnified input difference generated by
the preamplifier to generate valid logic level outputs which are latched by the SR latch at
the output. The time required for the regenerative latch output to reach valid logic
voltage level depends on the magnitude of the input difference and it must be faster than
the latch period generated by the oscillator. Therefore, the preamplifier gain plays an
important role in ensuring that this requirement is satisfied. The SR latch stores the state
of the regenerative output such that only valid regenerative latch output is obtained at
the comparator output, without excessive switching of the output during the track phase.
-
8-2: Regulatory system regenerative latch comparator schematic
-
Figure 8-3 shows the transient response (post-layout) of the regulatory current-starved
ring oscillator when V33 is 3.3V. The oscillating frequency can be observed to be
approximately 500KHz and that the duty cycle of the oscillator designed is about 65%,
allowing more settling time for the track phase of the regenerative comparator. Also, the
average current consumed by the ring oscillator during oscillating is around 829.12nA
which is very small, making the proposition of implementing a regenerative comparator
for the regulatory comparator attractive from power consumption perspective. Recalling
the fact that the regulatory control system takes control of the converter once V33 rises
above 2.2V, it is expected that the oscillator is functional under this condition. Figure 8-4
shows the transient response of the oscillator when V33=2.0V and it can be observed
that the oscillator is still functional though the frequency increases slightly to 553.60 KHz.
-
-
8-3: Regulatory ring oscillator transient response (Typical, V33=3.3V)
-
-
-
8-4: Regulatory ring oscillator transient response (Typical, V33=2.0V)
As mentioned earlier, the oscillating frequency generated is expected to vary over a wide
range as process variation on the threshold voltages such that the trip point of the
inverters in the inverter chain changes and also temperature dependence of the bias
current and gate capacitances will affect the frequency generated. Figures 8-5 and 8-6
show the transient responses of the oscillator when V33=3.3V and V33=2.0V
respectively. Each simulation result includes the typical oscillating profile as well as the
slowest and fastest oscillating profile obtained using the different temperature and
process corners. The results observed are summarized and tabulated in the table
presented at the end of the chapter. It can be observed that there is a variation of up to
100% in the oscillating frequency and as a result the bandwidth of the pre-amplifier must
be designed accordingly to cater to the variation of the track period. For instance, the ontime of the oscillator output, i.e. track period is only 584ns when the transistors are at
“worst power” process corner with operating temperature at 125oC, hence the bandwidth
-
of the pre-amplifier must be at least 1.88MHz to ensure that the output of the preamplifier settles down to within 0.1% of the final output, before the latch phase kicks in.
8-5: Regulatory ring oscillator transient response (Corners, V33=3.3V)
S
8-6: Regulatory ring oscillator transient response (Corners, V33=2.0V)
-
In order to verify that the speed of the comparator designed meet the requirements
defined by the ring oscillator on-time which is the track period of the comparator, the
preamplifier magnitude response is simulated as shown in figures 8-7 and 8-8 under
different process and temperature corner situations when V33=3.3V and V33=3.0V
respectively. The simulations are performed with the regenerative latch at the outputs of
the preamplifier so as to include the effects of the load capacitances on the actual
bandwidth obtainable. From the simulation results, it is observed that the preamplifier
has an open-loop gain ranging between 10dB and 15dB. Also it has a minimum
bandwidth of 1.941MHz, ensuring that it meets the speed requirement set by the
minimum on-time of the ring oscillator. This implies that the preamplifier output can settle
down to within 0.1% of its final value within the track phase of the comparator.
8-7: Regulatory comparator preamp magnitude response (Corners, V33=3.3V)
-
8-8: Regulatory comparator preamp magnitude response (Corners, V33=3.0V)
The performance of the regulatory control system is evaluated by simulating both the
current-starved ring oscillator and the regenerative latch comparator with the actual
bandgap reference and resistive feedback network. The regulated output node V33 is
swept between 3.2875V and 3.3125V and the ring oscillator and comparator outputs are
observed, as shown in figures 8-9 and 8-10. It can be observed from the results that the
performances of the system in both schematic and post-layout views are similar and that
the ring oscillator output stage is able to drives all the switches in the regenerative latch
of the comparator. Also once the output V33 crosses the threshold of 3.3V during the
track phase of the comparator, the comparator output switches at the very next latch
phase, thereby verifying the performance of the regulatory system implemented.
-
-
O
(
)
-
8-9: Regulatory control transient response (Typical, V33=3.2875V to 3.3125V)
-
(
)
-
8-
: Regulatory control transient response (Typical, V33=3.3125V to 3.2875V)
-
Table 8-1 summarizes the simulated performance of the designed current-starved ring
oscillator and preamplifier of the latch comparator in the regulatory system under
different possible operating conditions.
Oscillator Frequency (V33=2.0V)
378.92KHz
553.60KHz
1090.28KHz
Oscillator Frequency (V33=3.0V)
338.07KHz
505.94KHz
1067.03KHz
Oscillator Frequency (V33=3.3V)
330.43KHz
500.77KHz
1080.56KHz
Oscillator On-Time (V33=2.0V)
0.579µs
1.040µs
1.460µs
Oscillator On-Time (V33=3.0V)
0.601µs
1.266µs
1.795µs
Oscillator On-Time (V33=3.3V)
0.584µs
1.321µs
1.874µs
Open-Loop Gain (V33=3.0V)
10.55dB
12.00dB
13.94dB
3dB Bandwidth (V33=3.0V)
1.986MHz
2.759MHz
3.109MHz
Open-Loop Gain (V33=3.3V)
10.79dB
12.25dB
14.22dB
3dB Bandwidth (V33=3.3V)
1.941MHz
2.720MHz
3.071MHz
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8-1: Regulatory control system sub-blocks summarized simulated performance
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r
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CChhaapptteerr 99
Anti-Backflow Current Control System
In order to improve on the overall conversion efficiency of the proposed buck-boost
converter, synchronous operation is supported, i.e. a power PMOS transistor will be
inserted between the inductor and output capacitor such that when the charges stored in
the inductor is transferred to the output capacitor, current will flow through this transistor
instead of the free-wheeling diode. By implementing this feature, conduction losses can
be minimized when current is transferred, since the voltage drop across the transistor is
much smaller. However, in synchronous rectification, additional control circuitries are
required to determine the switching of the power transistor. In this chapter, control
circuitries designed to implement the synchronous rectification feature will be described.
-
9-1: Inverting buck-boost converter voltage & current profiles during operations
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r
Figure 9-1 shows inductor current as well as the voltage profiles at the gates of the
power NMOS and PMOS. As mentioned earlier in Chapter 2, the inductor current is
decaying at a rate determined by the output regulated voltage and inductance of the
external inductor as this current is transferred to charge up the output capacitor. During
this period of the operations, the power PMOS transistor is supposed to be turned on
and should ideally switched off when the current decay to zero. Early or late switching off
of the PMOS power transistor will result in degradation in the overall efficiency.
9-2: Inverting buck-boost converter waveforms for early and late turn-off
Figure 9-2 shows the waveforms which can be observed when there is early or late
turning off of the PMOS power transistor. In the event when the transistor is switched off
early, i.e. before the inductor current dropped to zero, the remaining charges in the coil
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r
will be transferred to the reservoir capacitor through the diode. This will result in the
voltage profile at the power NMOS drain to increase from the output regulated voltage
level (before switching off) to a voltage which is one diode above V33. In this case, the
conduction loss involved is bound to increase. On the other hand, if the power transistor
is switched off after the inductor current has dropped to zero, charges stored in the
output capacitor will flow back to charge up the inductor, undoing some of the work done
earlier, thereby lowering the overall conversion efficiency of the regulator. Hence it will
be ideal if the power transistor is turned off at the instant when inductor current decays
to zero. However, it is impossible to build such a control circuitry as non-idealities such
as delay in switching off the power transistor, imperfect comparison of the inductor
current, etc. will result in early or late switching off.
In addition, it is important to note the voltage profile at the power NMOS drain. From
figure 9-1, it can be concluded that voltage at the node ranges from VPSUB, when the
power NMOS transistor is switched on, to V33 + Vdiode, where Vdiode is the voltage drop
across the free-wheeling diode when charges stored in inductor is transferred to the
capacitor. Hence in the context of the proposed regulator, voltage at the node can vary
between -10.0V to 4.0V. Hence it is critical to choose the appropriate devices for the
power PMOS and any control circuitries connected to this node, such that the safe
operating conditions are not violated during the buck-boost converter operations.
Control circuitries are required to manage the on-time of the power PMOS transistor so
as to ensure that the transistor is switched off when inductor current decays to zero. One
of the most commonly used parameters used to monitor the inductor current is the
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r
voltage drop across the synchronous transistor. When the inductor current is positive, i.e.
when inductor current flows to charge up the output capacitor, the voltage drop across
the PMOS will be positive and once the charges from the capacitor backflow to charge
the inductor, the voltage drop across the PMOS changes polarity. Hence one of the
simplest ways to manage the PMOS on-time is to implement a comparator with inputs at
the drain and source nodes of the power transistor. The power PMOS transistor will
switch off once the comparator output changes polarity. This method is popular due to
the simplicity of the design.
However, if the requirements of the comparator are to be examined, it can be observed
that the comparator needs to have a very high gain, resolution to detect the small
voltage drop across the power PMOS due to its low resistance. Besides that, the rate at
which the inductor current decays is dependent on the inductance and the output voltage
magnitude, and can be expressed as
dI L V 33 3.3V
=
=
= 330 mA µs
dt
L
10 µH
(9.1)
Hence from (9.1), it can be observed that the comparator must have a very high
bandwidth such that the comparator detects the change in polarity of the inductor current
with minimal delay. However, it is very difficult to implement a comparator with very high
gain and bandwidth with limited power budget. Although the regenerative latch
comparator similar to the one implemented in the regulatory control system provides a
viable solution to the problem, the frequency at which the comparator tracks and latches
must be very high so as to reduce the amount of current back-flowing. Implementing a
ring oscillator operating at such high frequency will result in high power consumption.
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r
Also, any preamplifier implemented within the regenerative latch comparator will need to
have a very high bandwidth so that its output can settle within the short tracking phase.
As a result, the overall conversion efficiency will be affected, making the implementation
of synchronous rectification less appealing.
The buck converter in [38] adaptively adjusts the on-time of the synchronous transistor
through implementation of a charge pump and the use of some simple control logic
circuitries. The direction of the inductor current during the instant when the synchronous
transistor is switched off is determined by simple logic gate outputs. And depending on
the outputs, the on-time is adaptively adjusted through increasing or decreasing the
charges held on the capacitor in the charge pump. In this case, simple logic gates are
able to detect the direction of the inductor current as ringing profile at that node is very
much subdued since the inductor used has very small inductance and is integrated
within the chip. Also, since the converter implemented operates in the buck-mode, the
node where the control circuitries use to determine the inductor current direction has a
swing limited to the input supply of the converter. However, the anti-backflow current
control system implemented in [38] will not function correctly for the case of the
proposed buck-boost converter due to a few reasons.
Firstly, due to the inductor and some parasitic capacitances at the drain of the PMOS
synchronous rectification transistor, the voltage profile at the node will ring according to
the resonance frequency. This phenomenon is commonly observed in most
commercially available dc-dc converters and if the control system in [38] is implemented
in these converters, the direction of the inductor current might not be determined
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r
correctly since the voltage profile can oscillate between positive and negative with
respect to the output. Secondly, as mentioned previously, the drain node of the power
PMOS can possibly swing between -10.0V and 4.0V due to the large input supply
voltage for which the converter is supposed to operate. As such, any circuitries which
are connected to the node to determine the inductor current direction must be able to
withstand the large voltage swing. Therefore, the use of simple logic gates is impossible
and will lead to reliability issues for the proposed converter.
In the proposed buck-boost converter, a modified anti-backflow current control system is
designed so as to overcome the problems mentioned. There is no need for a high-speed
ring oscillator in the design resulting in significant reduction in quiescent current
consumption. The design consists of an adaptive synchronous rectification transistor ontime generator, similar to the charge pump implemented in [38] and a comparator which
includes simple clamps at its inputs so as to cater to the wide voltage swing mentioned.
The on-time generator serves to predict the instant during which the inductor current
reaches zero in the current cycle. And before the synchronous transistor is switched off,
the comparator is enabled so as to determine the direction of the inductor current.
Depending on the comparator output, the on-time generated will be increased or
decreased so that the instant during which the PMOS is switched on in the next cycle is
closer to the time at which the current decays to zero.
Notice that the inductor current direction is determined before the synchronous PMOS is
switched off. This eliminates any potential problems in the detection which may occur
due to the unpredictable ringing profile at the drain of the PMOS. However, this will lead
to a slight inaccuracy between the timing in which the PMOS is switched off and the
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actual instant in which the inductor current reaches zero. The magnitude of this
inaccuracy introduced depends on the time required for the comparator to generate a
valid output. Ultimately, the on-time generator will toggle between two on-time outputs
which will result in comparator output with opposite polarities. The inductor current
magnitude at which the PMOS will switch off will be close to zero but the amount by
which it differs from the ideal value depends on the resolution of the on-time generator,
delay taken for the comparator to determine the current direction and delay of the driver
to switch off the PMOS.
Figure 9-3 shows the comparator designed for anti-backflow current control system [39].
Thick gate-oxide PMOS transistors MC0-MC3 form the simple clamp required to protect
and limit the voltages at the inputs of the comparator. The gates to the transistors are
connected to ground such that they only switch on when the drain node of the power
PMOS goes one threshold voltage above ground. When the power NMOS is switched
on, and that the node reaches the voltage level close to VPSUB, the clamps will not be on
and the pull-down transistor MSW1 will be switched on to pull the positive input terminal
of the comparator to ground so as to protect the input from the large negative substrate
voltage. Therefore, thick gate-oxide transistors are required for the implementation of the
clamp so as to withstand the large negative voltage (-10.0V) which the node can
possibly reach when the power NMOS is switched on. Also, it should be noted that the
body terminals of the thick gate-oxide transistors used for the clamp are bias in such a
way so as to eliminate any potential parasitic diode path which may damage the device.
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9-3: Anti-backflow current control comparator with input clamps schematic
The comparator operates off the V33 and the anti-backflow control system operates
once the regulated output V33 reaches above the under-voltage threshold of 2.2V.
Hence, functionalities of the comparator have to be guaranteed even when V33 is as low
as 2.2V. Also since quiescent current is the fundamental concern in achieving high
efficiency for the converter, a clocked zero-dc-current comparator realized with
transistors M0-M5 and MSW2-MSW6 is implemented. When the clock signal is low, the
comparator is in reset mode and the internal nodes are pre-charged to the supply
voltage by the switches. When the clock signal goes high such that the comparator is
enabled, the comparator goes into evaluation and regeneration mode. The input
differential pair resolves the input signal and the differential current develops a voltage
difference between the sources of transistors M2 and M3 before the cross-coupled latch
turns on. Then the latch transistors regenerate the amplified output signal back to full
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swing and hold the logic levels without consuming any static power. Very low power is
consumed by this comparator since only dynamic current flows during the evaluation
transient and once regeneration is completed, no static power is consumed by the
comparator. It should be noted that the input differential pair is implemented using
transistors with thicker gate oxide since the inputs can potentially reach 4.0V moments
before the synchronous PMOS is switched on. Also, the clock signal is generated by the
on-time generator such that it will go high for approximately 20ns after the generator
determines and predicts that the inductor current reaches zero.
After the 20ns during which the comparator is enabled, the power PMOS is switched off
and the clock signal to the comparator goes low. However, the comparator needs to
retain the state of its outputs so as to facilitate the adjustment of on-time in the generator.
The SR latch formed by transistors M6-M13 ensures that the output states are retained.
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-
The anti-backflow current control on-time generator operates off the V33 and ground
supply rails. Similar to the comparator specifications, the on-time generator needs to
operate down to 2.2V. Figure 9-4 shows the schematic of the on-time generator
designed. The generator consists of a charge pump formed by current sources I0, I1,
transistors MSWA, MSWB and capacitor C0, similar to that designed in [38], a current
reference generator formed by transistors M0 – M8, MSW1, resistor R0 and capacitor
C1, a startup circuitry formed by transistors MS1 – MS4 and capacitor CS and a
comparator similar to the adaptive power NMOS on-time generator discussed earlier.
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9-4: Anti-backflow current control on-time generator schematic
The charge pump charges or discharges the capacitor C0 with a fixed amount of current
for a fixed amount of time, depending on the comparator output. If the inductor current is
determined to be positive, such that the on-time for the power PMOS is to be increased,
the switch MSWB will be switched on for 200ns so as to discharge the charges stored on
the capacitors, resulting in a fixed voltage drop at node “NGATE”. Assuming that the
switch is ideal, the voltage drop can be approximated by
∆VNGATE =
I ref ton
C
(9.2)
Where Iref is the reference current determined by current sources I0, I1 and ton is the
duration which the switch MSW6 is turned on, while C denotes the capacitance at the
node “NGATE”. Similarly, when the inductor current is negative, the switch MSWA will
be turn on for 200ns and that the capacitors C0 will be charged, resulting in a voltage
increase at the node. The voltage increase (decrease) at the node decreases (increases)
the on-resistance of transistor M0 and will increase (decrease) the reference current
flowing in the current reference generator.
The current reference generator adopts the same architecture as the one used to supply
bias current to all sub-blocks within the chip (Appendix B). Transistors M1 and M2
operate in subthreshold region and the drain currents in M1 and M2 can be
approximated by (assuming no body effect and that the transistors are similar)
I D ,M 1 = I S ,M 1e(VG −VTH 0 ) / nVT
(9.3)
I D ,M 2 = I S ,M 2e(VG −VTH 0 ) / nVT e(−VREF ) / nVT
(9.4)
And since the drain currents through the two transistors are equal, defined by the equal
sizing of current mirror formed by M7 and M8, the above equations can be combined
and rewritten as
I
VREF = nVT ln S ,M 2
I S ,M 1
(9.5)
If transistor M2 has an aspect ratio K times that of M1 and that there is perfect matching
between the two, equation (9.5) can be written as
VREF = nVT ln(K )
(9.6)
where VREF denotes the source voltage of transistor M2. It can be observed that the
reference voltage is proportional to absolute temperature, similar to the PTAT voltage
difference formed by two bipolar transistors operating with different current densities.
The temperature dependence of the reference voltage is mitigated with the use of
resistors and transistor with appropriate temperature coefficients such that the current
generated shows little dependence on temperature. The current bias generated can be
approximated by
I BIAS =
VREF nVT ln(K )
=
R
R
(9.7)
where R depends on the resistance of the resistor chain R0 in figure 9-4 and the onresistance of transistor M0 which will vary depending on the charge pump output at node
“NGATE”. In other words, the bias current generated can be increased or decreased
depending on the inductor current polarity as determined by the comparator. A startup
circuitry implemented through transistors MS1-MS4 and capacitor CS is required for the
current generator so as to ensure that it operates in the correct operating condition.
During startup when the current flowing through the generator is zero, switch MS3 will be
turned on since the gate of MS3 is at zero potential, forcing the transistor pair M1 and
M2 to be turned on resulting in non-zero current flowing within the generator. This
current will be mirrored through M7, M8 and MS1 which will charge capacitor CS to the
supply and turns off MS3. The bias current generated is mirrored through transistors M7,
M8 and M6 and will charge the capacitor C1 once the synchronous PMOS is switched
on. Prior to that, capacitor C1 is completely discharged through the pull-down transistor
MSW1. The comparator realized with M11-M15, identical to that used in the adaptive
power NMOS on-time generator will compare the voltage on C1 with the bandgap
reference voltage of 660mV. Assuming that the comparator is ideal, the delay generated
by the on-time generator can then be approximated by
t=
C1VBG,660 mV C1RVBG,660 mV
=
I BIAS
nVT ln(K )
(9.8)
Therefore from (9.8), it can be observed that the on-time for the synchronous PMOS is
adjusted by controlling the on-resistance of M0 within the current bias generator.
From the above discussions, it can be concluded that the overall performance of the
anti-backflow current control system involves taking the output of the comparator as
some form of feedback to adjust the on-time of the power PMOS. And the amount of
inductor current overshoot/ undershoot which determines the performance of the system
can only be evaluated after a number of iterations within the control system designed.
Therefore, the performance of the system will only be evaluated in the last chapter when
top simulations of the buck-boost converter are performed.
In this section, the performance of the anti-backflow control comparator will be evaluated.
In particular, the transient response of the comparator will be observed as inductor
current starts to flow through the power PMOS. Figure 9-5 shows the typical transient
responses of the comparator as the inductor current flowing through the PMOS decays
when V33=2.2V which is the minimum operating supply voltage while figures 9-6 and 9-7
show the transient responses of the comparator under all process and temperature
corners when V33=2.2V. The simulation setup includes both the power NMOS and
PMOS and their respective drivers, together with a 10µH inductor. It can be observed
from figure 9-5 that the comparator output switches quickly after the voltage at the drain
terminal of the PMOS becomes lower than that at the source. The results are
comparable though the comparator in the post-layout view responses slightly slower.
Nevertheless, from figures 9-6 and 9-7 it can be concluded that the comparator is
functional under all conditions when V33=2.2V.
-
S
S(
(
-
-
)
)
)
9-5: Anti-backflow comparator transient response (Typical, V33=2.2V)
-
-
)
(
)
S
9-6: Anti-backflow comparator transient response (Corners, V33=2.2V)
-
(
)
)
S
9-7: Anti-backflow comparator zoomed transient response (Corners, V33=2.2V)
Figures 9-8, 9-9 and 9-10 show the comparator transient responses observed when V33
is increased to 3.3V. From figure 9-8, the comparator switches in less than 10ns after
the inductor current changes direction, and thereby has a faster response time than the
regulatory comparator while using much lesser current. This is possible due to
availability of a uniquely generated “enable” signal for the comparator.
-
-
)
S
)
S
-
-
9-8: Anti-backflow comparator transient response (Typical, V33=3.3V)
From figures 9-9 and 9-10, it can be concluded that the anti-backflow comparator
implemented is functional under all process and temperature conditions when the output
regulated voltage V33 is at 3.3V.
-
(
)
S
9-9: Anti-backflow comparator transient response (Corners, V33=3.3V)
)
-
-
C
(
)
)
S
9-
: Anti-backflow comp zoomed transient response (Corners, V33=3.3V)
-
CChhaapptteerr 1100
Complete Buck-Boost Converter
The proposed buck-boost converter is designed and implemented using the AMS
0.35µm high-voltage process. This process provides the option of placing transistors in
isolated wells and this is necessary for the implementation of the proposed design.
µ
-
In addition to the higher voltage tolerances across the terminals of the devices available
in the AMS 0.35µm HV process, the availability of more process layers allows the
foundry to provide with transistors placed in isolated wells. This helps to resolve a lot of
conflicts involving NMOS transistors used in the design.
-1: Cross sectional view of standard CMOS process NMOS
Figure 10-1 shows the cross section of a NMOS transistor in a normal low-voltage
CMOS process. The body terminal of the NMOS transistor is connected to the substrate
and as the entire chip shares the same substrate, the substrate contacts are always
connected to the lowest voltage in the design so as to prevent any PN junction from
conducting. This poses a restriction on the circuit design in the form of body effect. If the
source voltage of the NMOS is considerably higher than the substrate voltage, which
can be the case for some of the circuits used in this design, the threshold voltage of the
transistor will inevitably increase. In the extreme operating conditions of the design, the
source-body voltage can go up to 10.0V and will result in significant increase in
threshold voltage which may result in an increase in the minimum operating input supply
voltage required. And in most process, the devices are not able to withstand such a high
source-body voltage. The isolated transistors available in the AMS High-Voltage process
solve these potential problems in the design with an introduction of an additional n-well
which isolates the body of the NMOS transistor from the common substrate. This
additional n-well is connected to the highest potential V33 of the chip to prevent any
parasitic diode conduction. The process layer used for the isolated n-well allows it to
withstand the potentially high voltage across itself and the substrate. With this additional
isolation well, the source-body potential can be managed better by choosing to bias the
body terminal appropriately. For more information, please refer to the relevant process
documents [21] (classified).
The availability of the many different types of transistors and devices adds to the design
challenges and complexity. In general, to decide on the type of transistors to be used in
the circuits, one can determine the lowest potential in the particular block. For instance
for internal regulators 1 and 2 which are to generate an internal supply with respect to
substrate will have used non-isolated versions of the transistors in their designs while
the external LDO which sits on ground (not lowest potential in the chip) uses isolated
transistors in the design. In addition, it is important to note the potentially high operating
voltages across the terminals of some transistors in the design. However the
incorporation of internal regulators which generate a supply suitable for low-voltage
devices simplify and reduce the number of circuit blocks which require HV devices, i.e
exposed to high operating voltage. For these circuits, appropriate choice of high-voltage
transistors is to be made. The safe operations of the transistors in the design are then
verified using the “SOA” feature of the design kit. Figure 10-2 shows and summarizes
the type of transistors used in each of the circuit blocks introduced in the preceding
chapters.
-2: Buck-boost converter transistor type choice for each block
2
The design is implemented using the standard 40-pin dual-in-line (DIL) package. Table
10-1 shows the definition of each of the available pins on the package. The choice of a
dual-in-line package may not be well-suited for the chip implementation as majority of
the pins in the 40-pin package have lead resistances of up to 1.2 ohm and resulting in
higher conduction losses. Also, this package is not particularly suitable for power
applications due to its high parasitic inductances and this will result in excessive ringing
when the transistors switch. As a result, the overall conversion efficiency of the converter
will be lower than expected. The performance of the proposed chip can be improved by
using a better package. However since the primary objective for this current version is to
verify its functionality, the DIL package is chosen due to its simplicity.
3
The top-level layout of the chip implemented is shown in figure 10-3. The chip has a die
dimension of 2519µm by 2371.05µm. In order to achieve low on-resistances for the
power transistors, the aspect ratios are sized extremely large and these transistors
occupy almost 40% of the total area. These transistors are placed on one side of the
chip, close to the pads so as to reduce the routing resistance. In addition, multiple pads
are connected to each of the terminals of the power transistors so as to reduce the
bond-wire resistances involved.
-
-1: Power management IC pin allocation and definitions
REG_COMP_IN
1
I
Scaled down feedback input to regulatory comparator
UV_HYSTN
2
I
Defines lower limit to Under-Voltage threshold
UV_HYSTP
3
I
Defines upper limit to Under-Voltage threshold
V33_DGND
4,19
IO
Digital ground
POWER_V33
5,7,8
IO
V33 connected to power PMOS
DTEST_EN
6
I
PFET_D
9,10,14,15
IO
Drain of power MOS, connected to inductor
PWR_VPSUB
11-13
IO
Substrate connected to power NMOS
BB_EN
16
I
VPSUB
17,22,23,36
IO
Substrate
V33
18,21,32,33
IO
V33 for regulatory circuitries and LDO
VSS_V33_EXT
20
O
VSS_V33_EXT
VREF_CTAT
24
O
Connected to ext. res. defining CTAT current generated
ADPT_RES
25
O
Connected to ext.res. defining inductor current peak
VBG_TC
26
I
Bandgap temperature coefficient trim bit
VBG_TC
27
I
Bandgap temperature coefficient trim bit
VBG
28
I
Bandgap output accuracy trim bit
VBG
29
I
Bandgap output accuracy trim bit
V33_AGND
30
IO
LDO_EN
31
I
Enable external low-dropout regulator
LDO_OUT
34
O
External low-dropout regulator output
LDO_FB
35
IO
External low-dropout regulator feedback
VREF
37
IO
Connected to ext. res. defining bias current generated
NC
38-40
N.A.
Enable test
Enables buck-boost converter
Analog ground
Not connected
-
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-
-3: Power management IC top level layout
4
-
Figure 10-4 shows the typical startup profile of the buck-boost converter designed when
VPSUB=-5.0V. The converter is controlled by the startup circuitries such as the ring
oscillator and adaptive on-time generator which determine the on-time of the power
NMOS when V33 is below the under-voltage threshold of 2.2V. Once V33 rises beyond
2.2V, the regulatory control circuitries take over the control thus explaining on the
different profile observed in figure 10-4. However, it can be observed that in both
instances, the inductor current peak is controlled and limited to less than 350mA, thus
ensuring safe operations of the devices.
-
10-4: Buck-boost converter startup transient response (VPSUB=-5.0V, Typical)
-5: Buck-boost converter startup transient response (VPSUB=-0.75V, Typical)
Similarly, figure 10-5 verifies the capability of the converter in starting up with an input
substrate supply of -0.75V. It can be observed that the converter is able to boost the
output to 3.3V upon startup but it requires a longer startup time. The inductor current
peak is only 80mA as V33 remains below the under-voltage threshold, this is mainly due
to higher on-resistance of the power NMOS since the gate-source voltage is only 0.75V,
resulting in lower voltage across inductor. However once V33 rises above the threshold,
the inductor current peak increases as the on-resistance of the power NMOS decreases
since the driver to power NMOS now uses the VSS_V33_EXT supply rail.
5
-
-
Figure 10-6 shows the typical waveforms observed once the buck-boost converter
enters steady-state operations when VPSUB=-5.0V and ILoad=25mA. It can be observed
that the inductor current peak obtained is close to the designed value of 330mA and that
the output ripple voltage is about 15mV. Due to the innovative anti-backflow current
system implemented, the inductor current is observed to be close to zero as the power
PMOS is switched off. The efficiency of the converter operating under these conditions is
about 88.3% but is expected to drop further with the losses incurred in the package.
- -
-6: Buck-boost converter steady-state response (VPSUB=-5.0V, ILoad=25mA)
The buck-boost converter consumes about 10.77µA from the V33 supply rail under
these conditions and when the input supply drops to -1.0V and that the load current
remains at 25mA, the efficiency of the converter remains at about 88.1%.
6
From the simulation results, it can be observed that the proposed buck-boost converter
design is able to startup over a wide input supply range while maintaining the inductor
current peak at a safe level of approximately 300mA. The fact that it manages to startup
when input supply is as low as -0.75V which is about the threshold voltage of PMOS
transistors used in this process, verifies the design and concept introduced for the
startup circuitries. Also, the proposed converter is observed to be able to regulate at
3.3V with current load up to 25mA and therefore meets the design specification while
achieving a respectable efficiency of up to 88.3%.
-
CChhaapptteerr 1111
Conclusion
In this project, a power management IC comprising of a buck-boost converter and an
LDO is designed and implemented. Due to the high input supply range, i.e. up to -10.0V,
the design has to be implemented using the AustriaMicroSystems 0.35µm High-Voltage
process instead of the normal CMOS process.
11.1
-
Due to the complexities involved when operating with high input supply voltage and the
many difficulties and considerations involved when designing circuits using a highvoltage process, there is no existing publications which allow for direct performance
comparison. Most existing publications have designs which operate within the safe
operating conditions for standard low-voltage CMOS process, such as [5] and [22] and in
most cases, the designs involve the boost converter architecture as this topology suits
the use of a standard CMOS process. This work modifies and extends the concepts
introduced in low input supply boost converters, such as the 1-V startup control system
in [22] for a buck-boost converter which has wider input supply range covering the highvoltage domain.
The simulated performance of the buck-boost converter is compared with some of the
commercial buck-boost converters available as well as existing publications, as shown in
the comparison table 11-1.
-
-1: Comparison table for buck-boost converters
[5]
[6]
[7]
[8]
Type
Buck-Boost
Buck-Boost
Buck-Boost
Boost
Buck-Boost
Inverting/
Non-inverting
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Minimum VDD
2.5V
1.8V
2.7V
0.7V
0.3V
Maximum VDD
3.2V
5.5V
10.0V
5.5V
10.0V
Quiescent Current
Not Specified
16µA
86µA
5µA
10.8µA
Max Load Current
800mA
260mA
500mA
100mA
25mA
In [5], a non-inverting 4-switches synchronous buck-boost converter is designed and
implemented using a similar topology to that introduced in chapter 2. It operates over a
narrow input supply range of between 2.5V and 3.2V which makes the design
implementable in a standard CMOS process. It has a peak to peak output ripple voltage
of up to 275mV, due to the high current load it is designed for and has an overall
conversion efficiency of between 10% and 62% which is low, due to the high onresistance of the power transistors used for the design. This problem does not exist for
commercial buck-boost converters [6], [7]. In both chips, a non-inverting 4-switches
topology buck-boost converter is implemented and in [7], power transistors with low onresistance are to be implemented externally. The commercial chips using the proprietary
process catered for power applications are able to achieve high efficiency of up to
90~96%. These converters are designed for moderate power applications but it can be
noted that by comparing the two, a considerably higher amount of quiescent current
-
(86µA) is required in [7] as it operates over a wider input supply range as compared to
[6]. Moreover, due to the topology used for these designs, the two converters are not
able to operate when input supply is below 1.8V and this restricts the use of these
converters in renewable energy sources applications mentioned in Chapter 1.
The designs in [8] as well as [22] are one of the first designs which allow the DC/DC
converters operations under such low input supply, i.e. 0.7V. These converters are
designed for applications utilizing solar cells as input supply. However, these designs
are implemented with the boost topology of the DC/DC converters and as a result they
are not functional in conditions when input supply is higher than the regulated output
voltage. Also, since these designs deal with relatively low input supply, high voltage
protection circuitries need not be considered. Also, variation in inductor current peak will
not be significant over this narrow supply range and circuits need not be designed to
limit the inductor current. This ultimately leads to lower quiescent current consumption
when compared to the buck-boost converters.
Comparing the simulated performance of the proposed buck-boost converter with the
other designs, it can be observed that the proposed design is able to operate over a
wider input supply range, i.e. -0.3V to -10.0V as compared to the rest. And despite the
wide supply range which the design operates, its quiescent current consumption is
maintained at 10.77µA which is much lower than the commercial buck-boost converters
available. However, the proposed design generates an inverting output supply and by
taking this into consideration during the system design, this drawback can be overcome
easily.
-
11.2
-
The rising energy costs and the increase in popularity and demand for applications
running on renewable and alternate energy sources have led to the need for dc/dc
converters which operate over a wider input supply range. In order to increase and
improve on the input supply operating range of existing buck-boost converters which
typically can operate down to 1.8V, the concept which was recently introduced in boost
converters such as [8] and [22] is modified and improved on so as to allow
implementation in a conventional inverting buck-boost converter. For instance, the novel
startup control system introduced in [22] which involves an oscillator is developed further
as the wide input supply range of up to 10V will result in ridiculously high inductor current
if this system is implemented directly. An additional adaptive startup on-time generator is
introduced in the startup control so as to limit the inductor current when input supply is
high.
Also, since the converter is designed for low power applications, its quiescent current
consumption is particularly important in determining its overall conversion efficiency.
However, in most cases, where the converter is to operate over such a wide input range,
more circuits are required and this inevitably results in higher quiescent current as
observed in [7]. In order to ensure that the converter is able to safely operate over this
wide supply range of up to 10V while maintaining the quiescent current at a respectable
10.77µA, a novel internal power management system is implemented as mentioned in
Chapter 5. With this design, complicated voltage protection circuitries are no longer
required.
-
In addition, the buck-boost converter design implements a novel anti-backflow current
control system. It involves improvements and modifications made to the design in [38]
which suits designs with integrated inductor and low-voltage input supply. However for
the commonly used DC/DC converters with external inductor, the concept introduced
may not be feasible with reasons mentioned in Chapter 9. Hence a novel design which
extends the concept used in [38] is implemented. This design reduces the quiescent
current consumption of the anti-backflow current control system significantly.
With the introduction and implementations of these novel concepts and designs, which
have been clearly described in the preceding chapters, a novel wide input supply range
buck-boost converter is implemented. The buck-boost converter designed is able to
generate a 3.0V/3.3V regulated supply and caters to a load current of up to 25mA. It is
able to operate over a wide input supply range of between -0.30V to -10.0V and is able
to startup with a minimal input of -0.75V typically. From the simulations performed on the
converter, the design is observed to consume a quiescent current of 10.77µA and
achieves an efficiency of up to 88.3%.
-
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-
A
A
Appppeennddiixx A
Adaptive On-Time Generator
As mentioned in Chapter 2, the operation of the buck-boost converter can be divided into
2 stages. The first part of the operation involves building up of inductor current IL by
switching on the power NMOS while during the second stage, the power NMOS is
switched off and charges stored in the inductor will be transferred to the output reservoir
capacitor through synchronous rectification using the power PMOS. Or if synchronous
rectification is not supported, the charges will be transferred through a diode.
-1: Basic waveforms observed during operations of buck-boost converter
Figure A-1 shows the simplified waveforms during the operations of the buck-boost
converter. During the first stage of the operation, the inductor current peak, neglecting
any voltage drop across the NMOS power transistor, is given by
-
I L , peak =
V
0 − (− VPSUB )
Ton = PSUB Ton
L
L
(A.1)
where VPSUB is the magnitude of the substrate voltage, L being the inductance while Ton
is the turn on time of the NMOS power transistor. The inductor current peak needs to be
properly managed so as to prevent damage to the devices involved, i.e. chip, inductor
and diode.
The fixed on-time control is one of the popular methodologies adopted by some designs.
This control is easy to implement as it involves a minimal amount of control circuitries.
However, given the wide range of input supply, VPSUB that the proposed chip is supposed
to operate, adopting the fixed on-time control technique will result in a wide range of
inductor current peak. In this case where VPSUB can vary from -0.30V to -10.0V, using a
10µH inductor and assuming a fixed Ton of 5µs, inductor current peak can be expected to
have a range of 0.15A to 6.25A. Therefore in order to cater the high current peak of
6.25A, larger sized power transistors have to be incorporated in the chip. Also the
inductor and diode current ratings have to be higher, thus resulting in higher production
cost.
On the other hand, reducing the fixed on-time Ton so as to lower the upper range of the
inductor current peak will unnecessarily lower the inductor current peak at the lower end.
This results in a buck-boost converter that operates at a higher frequency for a particular
current load. Switching losses will then dominate over the conduction losses in the buckboost converter and will ultimately reduce the overall conversion efficiency.
It can be observed from (A.1) that the inductor current peak is proportional to the supply
voltage as well as the on-time. As a result, the inductor current peak varies over a wide
range since the converter is to operate between -0.30V to -10.0V. In order to reduce this
spread, it is important to reduce the dependence of IL,peak on the supply voltage. One
possible method is to generate an on-time which is adaptive to the supply voltage
changes. If the on-time Ton, is inversely proportional to the substrate supply voltage
VPSUB, such that
I L , peak =
VPSUB
V
k
k
Ton = PSUB
=
L
L VPSUB L
where k is the proportionality factor. And if this factor can be made independent or
weakly dependent on the supply, the variation of the inductor current peak can be
reduced to a great extent.
A
-
-2: Simple implementation of adaptive on-time generator [24]
(A.2)
Figure A-2 shows a circuit implementation for an adaptive on-time generator. This circuit
has been implemented in buck converters [24], [38]. The key advantage of this circuit is
that it is simple and thus consumes minimal quiescent current. In the buck converter, the
inductor current peak is given by
I L, peak =
VIN − VOUT
Ton
L
(A.3)
Examining the circuit in figure A-2, it is observed that the current flowing through resistor
RBIAS and transistor MN1 can be written as
I BIAS =
VIN − VGS , MN 1
RBIAS
(A.4)
The adaptive on-time generated is then given by the relationship between current
flowing through MP2 and the voltage at the capacitor at which is sufficiently high to allow
the generator output to go high. The adaptive on-time can be approximated by
Ton =
CVtrip
kI BIAS
=
CRBIAS
Vtrip
k (VIN − VGS , MN 1 )
(A.5)
Where k is the current mirror aspect ratio of MN1, MN2, MP1 and MP2 while Vtrip is the
minimum threshold voltage for output of the common source stage to be pulled down to
the trip point of the inverter at the output stage. From the above approximation, it can be
observed that the on-time generated is inversely proportional to (VIN – VGS,MN1) and in
[24], it was assumed that the VGS,MN1 approximates the regulated output voltage, i.e.
Ton =
CRBIAS
CRBIAS
CRBIAS
Vtrip ≈
Vtrip ⇒ I L, peak =
Vtrip
k (VIN − VGS , MN 1 )
k (VIN − VOUT )
kL
(A.6)
Hence it can be concluded that inductor current peak resulting from the implementation
of this circuit is independent on the input and output voltage. However, this circuit
implementation is not suitable for the case of a buck-boost converter. As mentioned
earlier, for the inductor current peak to be independent on the input voltage, the adaptive
on-time should ideally be inversely proportional to the supply voltage. But from (A.6), it is
obvious that the addition of the VGS,MN1 term in the denominator will introduce an error
and the on-time generated will vary with input supply voltage, though to a smaller extent.
Moreover, by examining equation (A.6), it can be observed that the inductor current peak
generated is process and temperature dependent. Current mirror mismatch, process and
temperature variations on transistor MN6, resistor RBIAS and capacitor are some of the
factors which can affect the result. Furthermore, the error arising from the assumption
that the gate-source voltage of MN1 approximates the regulated output voltage will also
vary as the parameters of transistor MN1 changes across process and temperature
corners. In the design, RBIAS is trimmed so as to mitigate any errors which arose from
process variations. Despite the trimming performed on RBIAS, it was reported that the
measured on-time was 50% longer than the on-time specified. The deviation from its
targeted variation affects the overall power efficiency of the converter.
Besides that, the circuit implementation in figure A-2 requires a minimum supply of
VGS,MN1 + IRBIAS. And for the high voltage 0.35µm process used, the typical threshold
voltage of a NMOS is around 0.50V. However, the buck-boost converter will be required
to operate down to -0.30V. Therefore this simple circuit cannot be used in the proposed
buck-boost converter design.
A
-
The adaptive on-time generator to be designed for the proposed buck-boost converter
must be able to generate an on-time inversely proportional to the absolute substrate
supply voltage VPSUB which can vary between -0.30V to -10.0V. Knowing that the
threshold voltage of a PMOS in the process used can reach approximately 0.90V at
process and temperature corners, it is impossible to have the generator to operate from
the substrate supply rail. Hence it is more appropriate for the adaptive on-time generator
to be powered by the output supply V33 rail.
The adaptive on-time generator is expected to be functional upon startup once the
regulated output supply reaches 2.2V when the under-voltage comparator output goes
low. At this point, the regulatory circuits are expected to take over the control of the
regulator from the startup circuitries. Therefore the proposed generator is supposed to
operate under a supply voltage range of 2.2V to 3.6V. In addition, the on-time generated,
i.e. peak inductor current is supposed to be variable, possibly through the use of an
external resistor or capacitor, so as to cater to the different input supply characteristics.
However, the on-time variation at a particular resistor choice, due to process and
temperature variations is supposed to be ±20% of the typical value, less than the 50%
variation observed in the previous design. In this case, the nominal on-time generated is
selected to be 660ns when VPSUB is -5.0V and output regulated supply V33 is 3.3V.
Figure A-3 shows the block diagram of the proposed adaptive on-time generator. It
consists of an amplifier in current-voltage feedback topology. Assuming that the amplifier
is ideal and has zero systematic offset, the virtual short at the input terminals of the
amplifier will ensure that the negative terminal of the opamp be at ground, such that the
current through transistor M1 and external resistor RBIAS can be written as
I RBIAS =
0 − (− VPSUB ) VPSUB
=
RBIAS
RBIAS
(A.7)
-3: Proposed adaptive on-time generator block diagram
This current charges the capacitor C1 through the current mirror formed by transistor M2
and M3. The voltage at the capacitor C1 is compared with reference voltage of 660mV
using the comparator. The on-time generated is given by the time taken from which the
current starts to charge the capacitor to the instant when comparator output goes high.
Assuming that the comparator is ideal, the adaptive on-time is given by
Ton =
C∆Vcap
I RBIAS
=
CRBIASVBG,660 mV
VPSUB
(A.8)
where C includes the capacitance of C1 and stray capacitances at the node, e.g. gate
capacitance of the input transistor of comparator, etc. Hence from (A.8), it can be
observed that the on-time generated fulfilled the requirement of being inversely
proportional to the VPSUB. Therefore using the adaptive on-time generated, inductor
current peak of the converter is expected to exhibit less variation with VPSUB.
A
-
The amplifier shown in figure A-3 is operating off the V33 supply rail, i.e. expected to
function across supply voltage range of 2.2V to 3.6V. The input common-mode range of
the amplifier should include ground, since the positive terminal senses the ground
potential to convert the voltage to current in RBIAS. Therefore, a PMOS differential pair is
implemented as the input stage of the amplifier. Besides that, it can be observed that the
amplifier output range should include the gate-source voltage of transistor MN1.
In this case, the PMOS input differential pair folded cascode architecture is selected for
the amplifier design, due to its simplicity. From figure A-3, it can be observed that there
is a non-dominant pole at the source of the M1, formed by the pad capacitance (since
RBIAS is external), and RBIAS. The pole at this node can be written as
p2 =
(
2π RBIAS
1
1
≈
(1 g m,MN1 ) C pad 2πRBIAS C pad
)
(A.9)
The pole location is detrimental in ensuring that the current-voltage feedback loop is
stable. Figure A-4 shows the schematic view of the folded cascode amplifier designed as
part of the V-I converter (Biasing circuitries are excluded). Shunt compensation is
implemented to ensure stability for the V-I converter. The dominant pole is formed by the
high output impedance of the amplifier together with the compensation capacitor. In this
case, the compensation capacitor is realized using a MOS capacitor MC0, in order to
reduce the silicon area. And assuming that parasitic capacitances at the output are
insignificant as compared to the compensation capacitance, the dominant pole is
p1 ≈
1
1
≈
2πRout CMC 0 2π ( g m11ro 9 ro11 g m13ro13 ( ro 7 ro15 ))CMC 0
(A.10)
By adjusting the size of the MOS capacitor MC0, the stability of the V-I converter can be
ensured in all operating conditions.
-4: Adaptive on-time generator (regulatory control) schematic
A
-
Current generated by the V-I converter is mirrored through M2 and M3. Subsequently,
this current is used to charge the capacitor C1. The voltage profile at capacitor C1 is
then used to generate the on-time using a comparator. In the simple generator circuit
shown in figure A-2, the comparator is realized using a single-stage common source
amplifier which has an inverter chain at the output to boost its gain. The main problem
with this implementation is that the trip point, i.e. voltage at C1 at which the comparator
output switches, is strongly dependent on the process parameters of the transistor
forming the common-source stage. This in turn translates to a large variation in the
adaptive on-time generated across process corners. The presence of a bandgap voltage
on-chip allows comparison with voltage on C1 without depending on process-dependent
threshold voltage as reference. Comparison can be performed using an input differential
pair as shown in figure A-4. The first-stage of the comparator is realized using transistors
M16-M20 which forms a NMOS differential pair with active current load. The logic gates
at the output boost the gain of the first stage.
The speed of the comparator is predominantly determined by the bandwidth of the first
stage and it can be improved by minimizing the load capacitance at its output and also
by increasing the bias current. However, in order to reduce quiescent current of the
comparator while not compromising on the speed, the current source of the first stage is
controlled by the signal “REG_COMP_SET” which enables the first stage when required.
Hence when the power NMOS transistor is switched off, only the V-I converter will
consume current while the comparator designed will not consume any current.
Furthermore, when the comparator is switched off, the output of the first stage is pre-
charged to V33 using the switch MSWA and once the comparator is enabled, the current
through M17 will slowly increase as the voltage profile on C1 increases, thereby
discharging the output node of the first stage, subsequently causing the comparator
output to trip.
During regulation of the buck-boost converter, the “on” signal together with the reset
signal i.e. comparator output generated by the adaptive on-time generator will serve as
inputs to an S-R flip-flop. The output of the flip-flop is then used to control the NMOS
power transistor. Therefore, the time taken for the generator to reset the flip-flop upon its
activation by the “on” signal gives the approximate on-time for the power NMOS.
A
- -
-
In order to verify on the stability of the current-voltage feedback loop involving the
voltage to current converter, it is important to examine its loop response. Figure A-5
shows the loop response of the voltage to current converter in the adaptive on-time
generator in typical conditions, i.e. V33=3.3V, VPSUB=-5.0V, RBIAS=4.7MΩ, typical corner.
In this simulation, the pad capacitance as well as routing capacitance at the source of
transistor MN1 is estimated to be 5pF. It can be observed that there is no significant
difference between the schematic and post-layout simulation results. And the V-I
converter has a loop gain of about 87.7dB and a phase margin of 88.6 degrees. Figure
A-6 shows the loop response of the V-I converter when V33 drops to 2.2V and it can be
observed that there is no significant degradation in the frequency response performance.
-
-
–
–
-
-
-
A-5: V-I Converter AC Loop Response (V33=3.3V, VPSUB=-5.0V, RBIAS=4.7MΩ)
–
-
-
–
-
-
-6: V-I Converter AC Loop Response (V33=2.2V, VPSUB=-5.0V, RBIAS=4.7MΩ)
From the two sets of simulation results, it can be seen that the V-I converter has a very
low bandwidth, primarily due to the fact that ultra low quiescent current is used to bias
the amplifier, thus lower transconductance and also because of the shunt compensation
used in this design.
The V-I converter should have its worst case phase margin when the non-dominant pole
given by (A.9) is at its lowest frequency. And from (A.9), it can be expected that the pole
location is at its lowest frequency when RBIAS is of the highest resistance and when the
current flowing through M1 is at its lowest, i.e. VPSUB=-0.30V. In this design, RBIAS is
catered up to the resistance value of 15MΩ, which is approximately 3 times more than
the nominal resistance of 4.7MΩ, i.e. translating to approximately 3 times of the nominal
inductor current peak. Using this worst case external condition but with the typical
process corner, the loop response of the V-I converter is simulated again at 2 different
supply, i.e. V33=3.3V and V33=2.2V as presented in figures A-7 and A-8 respectively. It
can be observed that no significant differences can be seen in the schematic and postlayout simulation results and that the open-loop gain of the converter remained relatively
unchanged at 86.1dB. However, the phase margin degraded as expected to
approximately 70.4 degrees, which is still acceptable.
–
-
-
–
-
-
-7: V-I Converter AC Loop Response (V33=3.3V, VPSUB=-0.30V, RBIAS=15MΩ)
-
–
-
–
-
-
-
-8: V-I Converter AC Loop Response (V33=2.2V, VPSUB=-0.30V, RBIAS=15MΩ)
In order to obtain the worst case results which include the different process corner
conditions, the loop response of the V-I converter is simulated at all possible process
corners using the worst case external conditions obtained above. The results at different
V33 supplies of 3.3V and 2.2V are as shown in figures A-9 and A-10 respectively.
V-
V-
-9: V-I AC Response (V33=3.3V, VPSUB=-0.30V, RBIAS=15MΩ, Corners)
-
V-
V-
-
: V-I AC Response (V33=2.2V, VPSUB=-0.30V, RBIAS=15MΩ, Corners)
From the simulation results, the lowest loop gain obtained is 79.2dB while lowest phase
margin observed is 65.6 degrees across all process corners.
A
-
In order to validate functionality as well as performance of the adaptive on-time
generator, the transient response of the system (V-I converter and comparator) to an
“on” signal is simulated. As mentioned earlier, the adaptive on-time generated is very
much dependent on the capacitance of C1 and parasitic capacitances at that node.
Subsequently, in order to account for parasitic capacitances, post-layout simulation of
the generator is performed at the specified conditions and capacitor C1 is adjusted so as
to meet the specifications. Figure A-11 shows the transient response of the generator at
nominal operating conditions but with all possible temperature and process corner
permutations. Figures A-12 and A-13 present transient responses when VPSUB is
adjusted to -0.30V and -10.0V respectively.
-
-
-
: Adaptive Ton transient response (VPSUB=-5.0V, RBIAS=4.7MΩ, Corners)
-
-
: Adaptive Ton transient response (VPSUB=-0.30V, RBIAS=4.7MΩ, Corners)
-
-
-
: Adaptive Ton transient response (VPSUB=-10.0V, RBIAS=4.7MΩ, Corners)
Variations in the adaptive on-time can be observed for the different process and
temperature corners. This is expected as process variations on the capacitance of C1 as
well as the impact of transistors process variations on the speed of comparator will
certainly cause the on-time generated to differ. However, these effects can be eliminated
by varying the resistance of external RBIAS. On the other hand, non-idealities associated
with the comparator will cause the adaptive on-time generated to deviate from its
inversely proportional relationship with the VPSUB. As a result, the inductor current peak
will vary slightly with VPSUB. Figure A-14 shows the adaptive on-time generated and its
corresponding inductor current peak (using (A.1)) as VPSUB varied from -0.30V to -12.5V
under typical process condition. It is important to note that the actual current peak
observed will deviate from (A.1) as non-idealities such as delay in turning on the NMOS
power transistor and finite on-resistance of the power MOS do exist in an actual system.
-
-
-
-
-
: Adaptive on-time variation with VPSUB (V33=3.3V, RBIAS=4.7MΩ, Typical)
Although the on-time generated varies with VPSUB, the variation is small and it allows
simpler management of the devices used in the design as compared to the fixed on-time
methodology. Figures A-15 and A-16 show the on-time variation with VPSUB at the two
extreme corners and temperature conditions, i.e. smallest and largest on-time generated.
It can be observed that the upper and lower worst case limit of the on-time generated is
less than ±20% of the nominal value which represents significant improvement in
performance as compared to [24] which showed deviation of 100% in some conditions.
This improvement is attributed to the modifications performed on the original circuit at
the expense of increased complexity, i.e. use of V-I converter to remove dependence on
threshold voltage. With proper allocation of resources, this circuit consumes merely
1.465µA at typical condition, mainly contributed by current flowing through RBIAS, i.e.
-
I RBIAS =
VPSUB
5.0V
=
= 1.0638µA ≈ 1.064 µA
RBIAS 4.7 MΩ
-
(A.11)
-
-
-
: Adaptive on-time variation with VPSUB (V33=3.3V, RBIAS=4.7MΩ, Fast)
-
-
-
-
: Adaptive on-time variation with VPSUB (V33=3.3V, RBIAS=4.7MΩ, Slow)
A
-
Table A-1 summarizes the simulated performance at post-layout level.
V-
- Loop Gain
79.2dB
87.7dB
-
DC Systematic Offset
-
177.7µV
369.5µV
Phase Margin
65.6 degrees
88.6 degrees
-
Gain Margin
42.4dB
44.5dB
-
Ton (VPSUB=-5.0V)
588.7ns
659.5ns
756.7ns
Ton (VPSUB=-0.30V)
9.44µs
10.37µs
11.54µs
Ton (VPSUB=-10.0V)
302.0ns
342.3ns
398.6ns
Quiescent Current
-
1.465µA
-
-
3: Adaptive on-time generator summarized simulated performance
-
A
B
Appppeennddiixx B
Current Reference
Transistor transconductances are the most important parameters in operational
amplifiers since the performances such as gain, bandwidth of the amplifiers are
dependent on transconductances of the input differential pair. Therefore it is important to
ensure that the transconductances do not vary much with supply voltage, process and
temperature variations. For the proposed chip, the input differential transistor pairs for all
the amplifiers are designed to operate in sub-threshold mode and the drain current and
transconductance of a transistor operating in sub-threshold region can be approximated
I D = I S e(VGS −VTH 0 ) / nVT
gm =
I S (VGS −VTH 0 ) / nVT
I
e
= D
nVT
nVT
(B.1)
(B.2)
It can be observed that the transconductance is inversely proportional to temperature
and hence the bias current designed to flow through the input transistors of the amplifier
must compensate for this dependence.
B
Figure B-1 shows the schematic of the current bias generator [40] implemented in the
chip so as to stabilize the transconductances of the transistors. The bias generator is
designed using transistors M0 – M7 and the current generated is mirrored to the other
-
circuits using transistors M10, M11 and other current mirrors. A startup circuit is
incorporated in the design using M8, M9 and capacitor C1 so as to ensure that the
current reference does not remain in non-operational state during power up. An external
resistor with default value of 2.2M
is connected to the Vref pin and this resistor defines
the bias current flowing to the other circuits. Shunt compensation is implemented using
capacitor C0 so as to shift the dominant pole located at the gates of M4 and M5 to
sufficiently low frequency from the non-dominant pole at Vref pin.
-1 Current bias generator and current mirrors schematic
Using (B.1), the current flowing through transistors M4 and M5 can be expressed as
I D, M 5 = I S , M 5e
I D, M 4 = 4 I D, M 5 = I S , M 4 e
(VGS ,M 5 −VTH ,M 5 )/ nVT
(VGS ,M 4 −VTH ,M 4 )/ nVT
(B.3)
=
1
(V
)/ nV
−V
I S ,M 5e GS ,M 4 TH ,M 4 T
5
(B.4)
Assuming that the threshold voltages of transistors M4 and M5 are similar,
1 (VGS ,M 4 −VGS ,M 5 )/ nVT
V / nV
e
= 4 ⇒ e ref T = 20 ⇒ Vref = nVT ln(20 )
5
(B.5)
-
Hence it can be observed that the voltage generated at Vref is proportional to the
absolute temperature and is independent on the load connected at the node. And
assuming that the resistive load connected externally has a resistance which is
independent on the temperature, the current generated will be PTAT. And comparing
(B.5) with (B.2), assuming that the process dependent term n matches, if the current
generated is used to bias the input differential transistor pair of the amplifiers, the
transconductances obtained will be independent on temperature. The actual voltage
obtained at Vref in simulations deviates from that in (B.5) and this is due to second order
effects which are not modeled in (B.1). However, the voltage at Vref can be observed to
be PTAT in simulations. Also, it should be noted that transistors M0 – M3 of the current
reference are designed to operate in saturation mode so as to improve on the matching.
The incorporation of an amplifier formed by transistors M0 – M3 and M6 – M7 reduces
the supply dependence of the bias current generated, as the drain-source voltages of
the sub-threshold transistor pair will continue to match as the supply voltage changes.
Hence the channel length modulation effect of the pair can be cancelled with different
supply, eliminating the possible second order effect and impact on the bias current
generated as the supply rail varies. This is important as the different modes which the
proposed chip is designed for will result in operations in varying supplies.
B.2
B.
The stability of the feedback loop in the current bias generator is verified by simulating
its frequency response. Since the current bias generator is operational in both modes,
when converter is enabled or disabled, the frequency response is to be evaluated when
-
V33 is 1.2V and 3.3V. Figures B-2 and B-3 show the frequency responses of the
feedback loop under typical conditions when V33 is 1.2V and 3.3V respectively. It is
observed that the loop has an open loop gain of about 62dB in both cases and the
phase margin is approximately 67.6 degrees, thereby verifying the stability of the loop.
(
(
)
-
)
-
-2 Current bias generator loop frequency response (Typical, V33=1.2V)
(
-
)
(
)
-3 Current bias generator loop frequency response (Typical, V33=3.3V)
-
B.
Since the current reference is supposed to provide the bias current to the sub-blocks in
both modes, when buck-boost converter is enabled or disabled, the bias generator is to
be functional for V33 ranges from 1.2V to 3.3V. Hence it is important that the bias
current generated remains stable as supply voltage varies such that the performances of
the other circuits are not affected. Figures B-4 and B-5 show the supply dependence of
the voltage and current reference generated (schematic and post-layout) when substrate
voltage is 0V and -5.0V respectively. It can be observed that the voltage and current
references remain stable as the supply voltage V33 varies from 1.0V to 3.6V. In
particular, the current ranges narrowly between 49.58nA to 49.75nA over the wide
supply range.
V
-
-
-4 Voltage and Current Reference Supply Dependence (Typical, VPSUB=0.0V)
-
V
-
-
-5 Voltage and Current Reference Supply Dependence (Typical, VPSUB=-5.0V)
-
A
Appppeennddiixx CC
V33 to VSSSS__VV3333__EEXXTT Level Shifter
As the buck-boost converter boosts up the supply rail V33 beyond the under-voltage
threshold upon power up, the regulatory control system takes over the control of the
converter. The regulatory control system comprising of the anti-backflow current control
system and the regulatory comparator interfaces with the digital control circuitries to
regulate the V33 supply. These circuits are designed to operate under the V33 supply so
as to ensure that the converter is still functional even when the input supply drops to
300mV. However during this regulating process, there are still some circuits such as the
driver to the power NMOS which are operating the internally regulated supply rail of
VSS_V33_EXT, which is clamped to approximately 3.4V above the negative substrate
voltage applied. As a result, there is a need to translate the control commands
generated off V33 to this internally regulated supply so as to drive the power NMOS
when required and this operation can be achieved through a level shifter.
C
Since the level shifter to be implemented is to be functional when the buck-boost
converter is in steady-state operations, its quiescent current consumption should not be
large so as not to affect the overall conversion efficiency. Also, the number of such level
shifter is to be minimized so as to reduce on the chip area and quiescent current
required. This is achieved by optimizing the design on the system level and in the
proposed chip only two of these level shifters are required to translate all necessary
-
commands to the appropriate supply voltage. One of these is used to translate the
command to drive the power NMOS while the other converts the under-voltage
comparator output to the internal VSS_V33_EXT supply rail.
The delay introduced during the process of translating the input command signal from
one supply to the other should also be minimized so that there is minimal impact on the
power NMOS on-time. Figure C-1 shows the schematic of the level shifter designed for
the purpose mentioned above. The quiescent current required for each of these level
shifters is about 62.5nA. It comprises of an input transistor pair M0 and M1 which takes
in complementary versions of the input signal to be translated and through the positive
feedback introduced by the cross-coupled transistors M6 and M7, an output signal which
is either VPSUB or close to VSS_V33_EXT is generated. This output signal is further amplified
through the inverter chain so as to generate the desired level-shifted signal.
-1 V33 to VSS_V33_EXT level shifter schematic
-
By connecting the gates of transistors M2 and M3 to VSS_V33_EXT, and forcing a small
amount of current to flow through them using I1 and I2, the sources of the two transistors
can be limited to be slightly less than VSS_V33_EXT, thereby ensuring that transistors M6,
M7 and the inverter chain are not exposed to voltages which are higher than their
maximum tolerable voltages. As high drain-source voltages can exist across M2 - M3,
and also M0 – M1, the transistor type of these transistors is to be selected appropriately.
C.2
Figure C-2 and C-3 show the simulation results on the delay (schematic and post-layout)
introduced by the level shifter when VSS_V33_EXT is 3.3V with respect to substrate voltage
and VPSUB is -0.30V. It can be observed that when VPSUB is -0.30V, the delay is about
3.1ns for the schematic view and increases slightly to 4.2ns due to the introduction of
parasitic capacitances at the nodes in the post-layout view as input signal changes from
low to high. But when the input signal changes from high to low, the delays observed are
about 7.7ns and 9.9ns for schematic and post-layout views respectively. These delays
are less than 5% of the shortest NMOS on-time designed and thus will have minimal
impact on the inductor peak current.
As mentioned earlier, the regulatory control system takes over the control of the
converter when the output voltage V33 is boosted beyond the under-voltage threshold of
2.2V, and from this instant, the level shifters are expected to translate the necessary
outputs from the control system to the circuitries operating off the VSS_V33_EXT. Hence it is
important to verify the performance of the level shifter when supply V33 is at this level.
Figures C-4 and C-5 show the delay introduced by the level shifter when V33 is 2.0V
-
and VPSUB is at -0.85V. The delay introduced ranges between 5.1ns and 13.6ns as the
input signal changes from low to high and vice versa. These delays amount to less than
5% of the shortest NMOS on-time designed.
-
(
)
-2 V33 to VSS_V33_EXT level shifter low-to-high transient profile (Typ, V33=3.3V)
(
)
(
-
)
-3 V33 to VSS_V33_EXT level shifter high-to-low transient profile (Typ, V33=3.3V)
-
-
(
)
-4 V33 to VSS_V33_EXT level shifter low-to-high transient profile (Typ, V33=2.0V)
(
)
(
-
)
-5 V33 to VSS_V33_EXT level shifter high-to-low transient profile (Typ, V33=2.0V)
-
A
D
Appppeennddiixx D
Bench Evaluation Report
The designed buck-boost converter was sent for fabrication and packaged in Dual-InLine (DIL) 40 pins package. The performance of the designed chip was evaluated using
the in-house double-layer PCB. In this section, the testing and evaluation of the chip will
be described in detail and suggestions will be provided at the end to facilitate future
works on the design.
D
Figure D-1 shows the setup of the buck-boost converter during bench testing. Nominal
resistance values (shown in schematic) are used for the reference current pins for the
bench evaluations. These values are designed and discussed in the previous chapters.
However, they can be adjusted to achieve optimum performance. Surface mounted
capacitors with low ESR are used so as to reduce the ripple voltage at both the input
and output of the buck-boost converter while the schottky diode and inductor used are all
surface-mount components. But due to poor quality of the in-house PCB used, it is
difficult to attain good connectivity between the components and the board. A single DC
power supply supplying a negative voltage to the substrate pins of the chip is required to
power the chip, as shown in figure D-1. Power supply threads, i.e. V33, ground,
substrate and PFET_D on the PCB are designed to be thick wherever possible as the
large amount of current flowing through these nodes will introduce a significant IR drop.
For instance, as the power NMOS is on, the inductor current is charged up to a peak
-
current of 330mA and this may result in a large voltage drop along the nodes of PFET_D
and substrate.
-
Bench evaluation setup and connections schematic
A DC power supplying negative voltage to the substrate pins is connected and powered
on after proper grounding is ensured. In order to reduce the voltage drop along the
-
power cables attached to the PCB, shorter cables can be used. Alternatively, multiple
cables can be connected in parallel to reduce the equivalent resistance of the
connection. During the first power up of the device, the bandgap reference has to be
trimmed to be as close as the nominal designed value of 660mV using the trim bits
available through the pins VBG. The bandgap reference voltage can be observed
through the regulatory feedback pin but this node is highly sensitive and may affect the
performance of the converter during probing. Instead, the bandgap reference is
observed through the low dropout regulator by enabling it and configuring it as unity-gain
buffer though the random offset of the LDO may affect the observation. The states of the
trim bits pins are then adjusted until the LDO output is closest to 660mV. This procedure
is required only during the first power up of the device. Subsequently the same setting
can be used for the particular device.
The output of the buck-boost converter is observed by connecting an oscilloscope to the
V33 node. The input supply voltage can be adjusted (within the input operating supply
range) using the functions of the power supply to verify the performance of the buckboost converter in the wide input supply range.
3
Using the test setup and method as mentioned previously, the performance of the
designed buck-boost converter is evaluated using the in-house PCB designed. The
laboratory test equipment used for the evaluation includes a DC power supply, multimeter and an oscilloscope. The test results obtained from the bench evaluations will be
presented in this section.
-
Figures D-2 and D-3 show the startup profiles of the buck-boost converter under no load
condition when input supply of -0.76V and -2.0V is applied to the substrate of the
converter. It can be observed that in both instances, the designed buck-boost converter
is able to startup and boost the output to the regulated level of 3.0V. The ability of the
converter to startup at a minimal input supply of -0.76V verifies the concept of the design
which theoretically requires a threshold voltage to startup. However it can be observed
from the test results that the input supply is extremely noisy when the buck-boost
converter is switching. For instance, from figure D-2, an input supply variation of 150mV
can be observed when probing the substrate node on the PCB and this noisy input
supply will certainly affect the performance of the device. Recommendations to improve
this large input supply variation will be provided later.
V
V
-2 Buck-boost converter bench evaluation - startup profile (VPSUB = -0.76V)
-
V
V
-3 Buck-boost converter bench evaluation - startup profile (VPSUB = -2.0V)
As the buck-boost converter starts up successfully, the regulatory control circuitries will
take over the control of the converter as it enters regulatory mode. In this mode, the
converter will remain in standby mode until the regulatory comparator monitoring the
output detects that the output has fallen below the threshold level. Once this happens, a
charging cycle will be initiated as the power NMOS is turned on and inductor be charged
to a pre-determined level. Figure D-4 shows the regulatory profile of the buck-boost
converter under no load condition when VPSUB is -0.76V. A peak-to-peak ripple voltage of
200mV can be observed at the output while V33 maintains an average value of 2.985V.
Also, a considerable amount of voltage drop of 200mV is observed on VPSUB during the
charging cycles of the converter. This will result in a significant difference between the
3
-
actual inductor current peak observed and that designed and achieved through the
adaptive on-time generator.
V
V
-4 Buck-boost converter bench evaluation - regulatory profile (VPSUB = -0.76V)
Figure D-5 shows the regulatory profile of the buck-boost converter under no load
condition when VPSUB is increased to -3.50V. The peak-to-peak ripple voltage observed
at the output is smaller than the previous case but the output V33 is observed to be
noisier as the output averages around 2.982V which is a small difference to that
observed when input is -0.76V. Although the input voltage is observed to have also
dropped in this case, its impact on the inductor current peak is not expected to be as
significant as compared to the previous case. In both cases, large magnitude ringing is
observed at V33 whenever the power NMOS or PMOS switches on, resulting in a noisy
output which is not observed in simulation results.
-
V
V
-5 Buck-boost converter bench evaluation - regulatory profile (VPSUB = -3.50V)
By adjusting the input supply voltage using the power supply and observing the buckboost converter output V33 using the oscilloscope, the line transient response of the
converter can be evaluated. Figures D-6 and D-7 show the line transient responses of
the buck boost converter output (under no load condition) when input VPSUB changes
from -0.30V to -1.30V and -1.30V to -0.30V respectively. The maximum output variation
observed during this supply variation is about 100mV as the output is still being
regulated at the designed value of about 3.0V. The results also verify the functionality of
the device when input drops to -0.30V which is part of the design specifications
mentioned previously.
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-6 Buck-boost bench evaluation – line transient (VPSUB ~ -0.30 to -1.30V)
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-7 Buck-boost bench evaluation – line transient (VPSUB ~ -1.30 to -0.30V)
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-8 Buck-boost bench evaluation – line transient (VPSUB ~ -1.0 to -2.0V)
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-9 Buck-boost bench evaluation – line transient (VPSUB ~ -2.0 to -1.0V)
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Figures D-8 and D-9 show the line transient responses of the buck boost converter
output (under no load condition) when input VPSUB changes from -1.0V to -2.0V and from
-2.0V to -1.0V respectively. No observable drop in V33 is observed during the line
transient event, verifying the line transient performance of the designed device.
4
As observed from the bench results in the previous section, the output ripple voltage of
200mV when VPSUB is -0.76V and also when VPSUB is higher is larger than the theoretical
output ripple voltage (18mV) expected for the design. One possible reason for the large
output ripple observed is the large parasitic capacitance at the external regulatory
feedback node. This capacitance together with the large feedback resistance used form
a significant RC delay. As a result, there is a delay in response for the regulatory
comparator as the regulatory feedback node serves as the input of the comparator. Due
to this delay, the converter continues on its charging cycle even when V33 has
exceeded the threshold, causing a larger output ripple. This is verified by the fact that
whenever an oscilloscope probe is connected to this sensitive node, thereby introducing
additional capacitance, a larger peak-to-peak ripple is observed at the output. In order to
reduce the delay introduced, it is suggested that the parasitic capacitance at this
sensitive node be minimized. This can be achieved by placing the sensitive node closer
to the device and reduce the PCB thread capacitance by using a better quality PCB.
Also the socket of the IC can be removed and that the large lead pins of the IC can be
reduced by changing the package to one which is surface mount.
In addition, it can be observed from the test results that a significant voltage drop of
200mV is present on the input VPSUB whenever the power NMOS is turned on and the
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large current used to charge the inductor flows through the test setup. This will result in
the inductor peak current to be different from that designed. This effect will be
particularly significant when the input supply voltage is low and result in difference in
performance as the input supply value changes. Due to the limited number of layers
available for the in-house PCB and the DIL40 package used, it is very difficult to have all
nodes which carry large instantaneous current to be sized wide on the circuit board.
Again, an improved PCB design using a better quality PCB fabrication facility can reduce
the voltage drop on the input when power NMOS is turned on.
Besides that, during the bench evaluations, large magnitude voltage spikes have been
observed on the common node of the power NMOS and PMOS whenever the power
PMOS turns on. These perturbations are subsequently reflected on the regulated output
(since the power PMOS is in the process of switching on), affecting the quality of the
output observed on the oscilloscope, evidenced by the large magnitude, high frequency
ringing profiles observed in the test results. One possible root cause to this observation
is the significant parasitic inductances associated with the DIL40 package. As the power
PMOS switches on, these parasitic inductances which are in series to the power PMOS
are to be charged to the main inductor current level in a relatively short amount of time
determined by the switching rise time. In order to achieve that, significant voltage
change will result on the common node between the power transistors and reflected on
the regulated output. There are two possible solutions to this problem. One of them is to
change the package to one with lower parasitic inductances, such as TQFP. The other
being increasing the switching rise time of the power PMOS, allowing the parasitic
inductor to be charged in a longer time so as to reduce the magnitude of the ringing
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profile. However this proposal may affect the overall conversion efficiency of the buckboost converter.
Future works on this design can start off with further evaluations on the current version
of the design. It is strongly suggested that the package be changed with TQFP44 being
a possible candidate. Upon doing so, a better quality PCB is to be designed for the
newly packaged IC, bearing in mind the important points noted in this preliminary
evaluation report, for instance minimizing the parasitic capacitances involved in the
regulatory comparator feedback node. More surface-mounted components such as
resistors and capacitors can be utilized in the improved PCB design so as to improve the
performance. Further evaluations and bench testing can then be performed using the
newly packaged IC and improved PCB to evaluate the actual performance of the current
design.
[...]... operate at a minimum supply voltage of 1.8V, i.e the wind energy harvester can only transmit data when wind speed is faster than approximately 5m/s Table 1-1 summarizes a few dc-dc converters and their performance It can be observed from the table that only the boost converter can operate with a low supply voltage of 0.7V and chip manufacturers have lowered the minimum supply required for the boost converters... energy harvesting shoes will be able to transmit data back to base more frequently Majority of the buck- boost dc-dc converters developed generate a non-inverting regulated output supply and are designed with a battery input in mind This offers great convenience to hardware developers, as the same input supply can be used to power other subsystems on board However these buck- boost converters can at most... considerably over the past few years These boost converters are designed for ultra-low supply applications such as those utilizing solar cells On the other hand, the minimum operating voltages for buck- boost converters remain relatively high with respect to that of the boost architecture and they required at least 1.8V to operate Hence these buckboost converters are not optimized to operate in a system... that of the conventional inverting buck- boost converter which is shown in figure 2-1 The setup is simple and requires the same number of external components as a buck or a boost converter It involves an inductor, a capacitor, a MOS switch and a diode, which in actual implementation is replaced by a MOS switch, so as to reduce the conduction loss However, a major setback of this topology, as its name... voltage of 3.3V, 2.5V and 1.0V can be calculated Using these figures, the ideal open-loop transient response of this converter under steady state condition can be simulated as shown in figures 2-7, 2-8 and 2-9 Hence this converter is able to seamlessly regulate the output voltage for a wide range of input supply voltage, without any extra circuitry to reconfigure the converter for each given input supply. .. sources can be designed However, the different characteristics, i.e differences in supply voltage ranges etc., of the energy sources have to be considered in designing the power management unit - - - 1-1: Linear low-dropout regulator block diagram Figure 1-1 shows a general block diagram of a linear regulator It consists of a bandgap reference generator and an error amplifier used to regulate the output... and buck- boost converters The buck- boost converter is best suited for applications involving a wide input supply range, since it is able to both step-up and step-down the input and provide a stable output supply Hence, by implementing a buck- boost converter in place of the linear regulators 6 - used in the designs, operating conditions for both systems can be further extended, i.e the person wearing... the input voltage It should be noted that the above derivations are made using the assumptions that the converter is operating in ideal conditions and there is no power losses Hence the duty cycle D obtained in practical implementations will differ from that obtained from (2.5) Using an inductor of 4.7µH and output capacitor of 4.7µF (Note that the inductance and capacitance values used for the ideal... 22 Buck- Boost Converter Topologies The buck- boost converter provides a solution to applications with wide input power supply ranges by stepping up or down the input supply to generate a regulated supply voltage There are many buck- boost converter topologies [9], [10], [11] which have been developed over the years Each of these topologies has been designed to meet the requirements for the different applications... transistor is always turned off while the PMOS is switched at a duty ratio D Notice that the reconfigured buck- boost converter in buck mode is identical to a standard buck converter except for an extra diode (transistor) from the inductor to the load If the diodes are implemented using transistors, this extra diode will always be on thereby making the implementation in figure 2-13 similar to a buck converter ... can be observed that the voltage generated has a wide range and it can reach up to 8.8V as the wind speed reaches 6.7m/s Again, - a linear regulator is used to generate a stable output voltage... remain in steady-state operations even as input drops to 0.30V With an input of 5.0V and an external load of 25mA, the designed converter possesses a conversion efficiency of 88.3% ii LIST OF TABLES... this case as some of them are always on in certain configuration Notice that the maximum voltage across any transistor is the same as the case of the conventional 4switches buck-boost converter,
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