Large signal modeling of gaas MESFET device 1

LARGE SIGNAL MODELING OF GaAs MESFET DEVICE MA JINGYI (M.Eng, BEIJING INSTITUTE OF TECHNOLOGY, P.R.CHINA) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2002 Acknowledgements i Acknowledgements I would like to deeply thank my supervisors, Dr. Ooi Ban Leong, Professor Leong Mook Seng, and Professor Kooi Pang Shyan, who led me into this interesting world of device modeling, and gave me full support for my study. I would also like to express my sincere gratitude to them for their patient guidance, valuable advices and discussions. I believe what I have learnt from them will always be beneficial to me. Special thanks go to Professor Xu QunJi and Dr Lin FuJiang for their encouragement and helpful discussions in circuit design, device physics and measurement techniques. I also wish to thank Teo T. C., Sing C. H., Wu Bin and Madam Lee in microwave and MMIC lab, for their kind helps and assistances in using the test facilities, conducting device and circuit measurement, and kindly providing me with useful documents. My gratitude also goes to all the friends in microwave division, for their kind help, and for the wonderful time we shared together. Finally, I would like to thank my family, for their endless support and encouragement. Table of Contents Table of Contents Summary .vi List of Tables . viii List of Figures .x List of Symbols .xvii List of Publications Arising from Present Thesis Research Work xix Chapter Introduction 1.1 1.2 1.3 1.4 History Device Model Objectives .5 Scope of this work Chapter Basic Operation and Device Models .11 2.1 Device Description 12 2.2 Physical Meaning of Small-Signal Equivalent Circuit Elements .14 2.2.1 Parasitic Inductances Lg, Ld and Ls .16 2.2.2 Parasitic Resistances Rs, Rd and Rg .16 2.2.3 Parasitic Capacitances Cpg and Cpd 16 2.2.4 Capacitances Cgs, Cgd and Cds 17 2.2.5 Transconductance gm 17 2.2.6 Output Conductance gds 18 2.2.7 Charging Resistance Ri .18 2.2.8 Transconductance Delay .19 2.3 Nonlinear Properties in Large Signal Models 19 2.4 Second Order Effects 20 2.4.1 Frequency Dispersion .20 2.4.2 Self-heating Effect 21 2.4.3 Sub-threshold Effect .23 2.5 Existing Small Signal Modeling Approaches 24 2.6 Existing Nonlinear MESFET Models 26 2.6.1 Physical Model .27 2.6.2 Empirical Model .29 2.6.3 Table-base Model .33 2.6.4 Other Approaches .34 ii Table of Contents Chapter Small Signal Modeling of GaAs MESFET .36 3.1 Introduction .36 3.2 De-embedding Technique .37 3.2.1 De-embedding of Series Parasitics 38 3.2.2 De-embedding of Parallel Parasitics .40 3.2.3 De-embedding Procedure of A Typical MESFET Device Parasitics 41 3.3 Objective Function 43 3.4 Cold-FET Techniques .44 3.4.1 Extraction of Parasitic Resistances and Inductances .45 3.4.2 Extraction of Parasitic Capacitances .52 3.5 An Improved Model for MESFET Parasitic Capacitance Extraction .57 3.5.1 Introduction 57 3.5.2 The Improved Model 59 3.5.3 Numerical Results 63 3.5.4 Conclusion 65 3.6 Hot-FET Techniques .65 3.6.1 Analytical Method and Optimization Method .66 3.6.2 Multi-Plane Data Fitting Approach .67 3.7 Comparison of Small Signal Equivalent Circuit 70 3.8 Numerical Results and Discussions .72 3.8.1 Equivalent Circuit Elements Determination 73 3.8.2 Cold-FET Extraction Results 74 3.8.3 Multi-Plane Data Fitting Extraction Results .77 3.9 Conclusion 86 Chapter A New Drain Current Model for GaAs MESFET .89 4.1 4.2 4.3 4.4 Introduction .89 An Examination of the Existing Empirical Drain Current Models .91 The New Model 98 Numerical Results and Discussions .107 4.4.1 Model Parameter Extraction .107 4.4.2 Modeling Results and Discussions 109 4.4.3 Amplifier Design Result .114 Chapter A New Charge Model for GaAs MESFET .119 5.1 Introduction .119 5.2 A Study of Some Existing Empirical Gate Capacitance Models 121 5.2.1 Diode Junction Capacitance Model .122 5.2.2 Statz Model 123 iii Table of Contents 5.2.3 Discussions .125 5.3 The New Model 130 5.4 Numerical Results and Discussions .133 5.4.1 Model Parameter Extraction .133 5.4.2 Modeling Results and Discussions 135 Chapter Model Verification 146 6.1 S-Parameter at Multi-Bias Points 146 6.2 Large Signal Performance Verification .150 6.3 A GaAs MESFET MMIC Power Amplifier 152 6.3.1 MMIC Power Amplifier Circuit .152 6.3.2 Device Modeling Result .155 6.3.3 Comparison of Simulation and Measurement Amplifier Results .162 6.4 Conclusion 167 Chapter Conclusions .169 Bibliography 174 Appendix A Large Signal Empirical MESFET Models 183 A.1 Curtice-Quadratic GaAs MESFET Model 183 A.2 Curtice-Ettenberg GaAs MESFET Model 184 A.3 Advanced Curtice Quadratic GaAs MESFET Model 184 A.4 Statz Model 185 A.5 Materka-Kacprazk GaAs MESFET Model .187 A.6 Chalmers Model .188 A.7 Rodriguez Model 188 A.8 TriQuint’s Own Model .189 A.9 TOM-2 GaAs MESFET Model 189 A.10 Model Proposed by V.I. Cojocaru and Brazil .191 A.11 Tajima MESFET Model 191 A.12 Parker MESFET Model .192 Appendix B TEE Network and PI Network Conversion 195 B.1 TEE Network to PI Network Conversion .195 B.2 PI Network to TEE Network Conversion .195 Appendix C Small Signal Parameter Extraction Formulation .197 C.1 Circuit Topology with Seven Intrinsic Elements 197 C.1.1 Analytical Method .197 iv Table of Contents C.1.2 Least-Square Error Function with Frequency as the Weighting Factor .199 C.2 Circuit Topology of Eight Intrinsic Elements with Cdc Introduced .200 C.2.1 Analytical Method .201 C.2.2 Least-Square Error Function with Frequency as the Weighting Factor .202 C.3 Circuit Topology of Eight Intrinsic Elements with Rgd Introduced .204 C.3.1 Analytical Method .205 C.3.2 Least-Square Error Function with Frequency as the Weighting Factor .206 v Summary vi Summary GaAs MESFET is the most widely used GaAs device. GaAs ICs and MMICs using MESFET technology have found a wide range of applications in wireless, optical, broadband data and satellite communication, as well as in industrial, automotive and military market. GaAs MESFET dominates in such applications as power amplifiers, low noise amplifiers and switches. It is also widely used in both analog and digital ICs. The accuracy of high speed, RF and microwave circuit design is mainly determined by the accuracy of the device model. Therefore, reliable modeling methodology and accurate device models are important and in great demand. Extensive works have been done in the field of GaAs MESFET modeling. Many models have been proposed. However, experience shows that they are generally only capable of modeling device performance under certain specific condition. In this work, a detailed study of GaAs MESFET large signal models for nonlinear microwave circuit design is carried out. Although the main focus of the study is on nonlinear modeling, the small signal modeling methodology is also investigated. An improved model for parasitic capacitances extraction is proposed. Unlike the conventional parasitic capacitance model, the resulting Cpd remains the same for different bias voltage, which is in agreement with theory. Different methods for extracting small-signal equivalent circuit parameters were studied, and a reliable extraction procedure is proposed. A new empirical model is developed to more accurately model drain current I-V characteristics of GaAs MESFET transistor. The newly proposed model expressions are original. Moreover, unlike some commonly used models that have a conditional pinch-off and are not continuous over the entire Summary device operation region, the new model and its derivatives are continuous under all bias conditions. It is capable of accurately modeling the device current-voltage behavior at different operating regions. Most specially, device operation around the pinch-off region is more accurately described, and the sub-threshold effect is modeled. A new gate terminal charge model for Cgs and Cgd description is also proposed. The resultant model is very accurate in describing device operation. Its accuracy in linear region, saturation knee region, and near Vds=0 is greatly improved. The model expressions and its derivatives are continuous over the entire device bias range. And most importantly, gate charge conservation law is observed for the new model. The new nonlinear current and charge models are implemented into circuit simulator for various MESFET devices. An MMIC power amplifier was designed and fabricated with the aid of the new models. Simulated and measured results are employed to evaluate the new model. Detailed model verification is discussed. vii List of Tables List of Tables Table 3.1 Parasitic Capacitances Calculated from the Model Proposed in [94] for A 2*100µm and A 2*150µm MESFET Devices 53 Table 3.2 The RMS Variation of Calculated Cpd under Three Different Vgs Bias Using Dambrine’s Model, White’s Model and the Improved Model (1-10GHz) .65 Table 3.3 Parasitic Elements Extracted from Procedure 1, Cpg and Cpd Use White’s Model 74 Table 3.4 Parasitic Elements Extracted from Procedure 1, Cpg and Cpd Use Dambrine’s Model .74 Table 3.5 Parasitic Elements Extracted from Procedure 1, Cpg and Cpd Use the Improved Model 74 Table 3.6 Intrinsic Elements Calculated from Procedure 1, Cpg and Cpd Use White’s Model, Vgs=0.4V, Vds=5.0V 75 Table 3.7 Intrinsic Elements Calculated from Procedure 1, Cpg and Cpd Use Dambrine’s Model, Vgs=0.4V, Vds=5.0V .75 Table 3.8 Intrinsic Elements Calculated from Procedure 1, Cpg and Cpd Use the Improved Model, Vgs=0.4V, Vds=5.0V .75 Table 3.9 Parasitic Elements Extracted from Procedure 3, Equivalent Circuit Topology as in Figure 3.25 78 Table 3.10 Parasitic Elements Extracted from Procedure 3, Equivalent Circuit Topology as in Figure 3.27 78 Table 3.11 Parasitic Elements Extracted from Procedure 3, Equivalent Circuit Topology as in Figure 3.26 78 Table 3.12 RMS Error of Modeled S-parameter, Equivalent Circuit Elements Extracted from Procedure 3, Calculation Made for Three Small Signal Equivalent Circuit Topology. Vgs=-2.0-0.5V, Vds=0.0-4.0V, f=1-30GHz .79 Table 4.1 The Drain Current Expressions of Some Existing GaAs MESFET Models 91 Table 4.2 The DC Drain Current Accuracies of Some Existing Models for a 2*150μm GaAs MESFET 97 Table 4.3 Parasitic Element Values of the Small-signal Equivalent Circuit (2*150µm Wafer device) 108 viii List of Tables Table 4.4 Parasitic Element Values of the Small-signal Equivalent Circuit (Fujitsu FLC103WG) .108 Table 4.5 Model Parameters for the New Drain Current Model (2*150µm Wafer device) .108 Table 4.6 Model Parameters for the New Drain Current Model (Fujitsu FLC103WG) 109 Table 4.7 Comparison of the Maximum Fitting Error and RMS Error of the New Model with Curtice Model, Chalmers Model and Parker Model (2*150μm Wafer device) 113 Table 5.1 Comparison of Cgs Accuracies of Diode Junction Capacitance Model and Statz Model for a 2*150μm GaAs MESFET 129 Table 5.2 Comparison of Cgd Accuracies of Diode Junction Capacitance Model and Statz Model for a 2*150μm GaAs MESFET 129 Table 5.3 Model Parameters for the New Gate Charge Model (2*150µm Wafer Device) 134 Table 5.4 Comparison of Cgs Accuracies of Diode Junction Capacitance Model, Statz Model and the New Model for a 2*150μm GaAs MESFET .143 Table 5.5 Comparison of Cgd Accuracies of Diode Junction Capacitance Model, Statz Model and the New Model for a 2*150μm GaAs MESFET .144 Table 6.1 MMIC Power Amplifier Design Specification 153 Table 6.2 List of the Equipments Used during the MMIC Power Amplifier Measurement .163 Table 6.3 Measured and Simulated MMIC Power Amplifier dB(S11) Response at 8.5GHz, 9.5GHz and 10.5GHz Respectively 167 ix Chapter A New Drain Current Model for GaAs MESFET 103 continuity of the new model provides better description for current transition, output conductance and transconductance. To illustrate the model continuity with respect to Vds, drain-source output conductance and its first-order derivatives are calculated based on the new model. The results are shown in Figure 4.7 and Figure 4.9 respectively. In Figure 4.7, modeled result for Ids and gds using the new model are plotted and compared to the measurement data. The result is extracted from DC I-V measurement. As can be seen, modeled and measured results for both Ids and gds perfectly match to each other. 60 (mS) 50 (mA) / g ds 40 I 30 ds (V gs = - 0.5V) I ds 20 10 g ds (V gs = - 0.5V) -10 -1 V ds (V) Figure 4.7 Ids and gds described by the new model ( modeled Ids, οοοο measured Ids, ------ modeled gds, •••• measured gds). In Figure 4.8, the gds result predicted by the new model extracted from DC I-V measurement is compared with the gds result from high frequency measurement. Discrepancy is observed for the modeled and measured output conductance which is Chapter A New Drain Current Model for GaAs MESFET 104 as expected. And it is caused by the frequency dispersion effect of the output conductance. 70 60 (mA) / g ds (mS) 50 40 20 I ds 30 10 g ds (V gs =- 0.5V) -10 -1 V ds (V) Figure 4.8 Comparison between gds predicted by the new model based on DC Ids measurement, and gds from high frequency measurement ( modeled gds, •••• measured gds). V gs =- 0.5V -0.1 -0.15 dg ds /dV ds (S/V) -0.05 -0.2 -0.25 -0.3 -0.35 -0.4 V (V) ds Figure 4.9 Second order derivative with respect to Vds described by the new model. Chapter A New Drain Current Model for GaAs MESFET 105 In Figure 4.9, the second-order derivative of Ids with respective to Vds calculated from the new model is shown. The curve is continuous. The higher-order derivatives of the new model with respect to Vds are well behaved. To illustrate the model continuity with respect to Vgs, transconductance, its first and second order derivatives are calculated based on the new model. The results are plotted in Figure 4.10, Figure 4.11 and Figure 4.12 respectively. 80 g g m m - N ew m od el I - Measu red d ata (mS) m ds V ds = 1.0V 40 20 I ds (mA) / g - Measu red d ata I ds 60 - N ew m od el -20 -2 V -1.5 -1 V gs -0.5 (V) ds = 0.2V 0.5 Figure 4.10 Comparison of measured and simulated Ids vs. Vgs and gm vs. Vgs characteristic based on the new model (2*150μm wafer device). In Figure 4.10, modeled Ids vs. Vgs and gm vs. Vgs characteristics predicted by the new model are plotted and compared to the measurement data. As can be seen, modeled and measured results for both Ids and gm perfectly match each other. The new model function is continuous over different biasing regions, and its derivative with respective to Vgs is continuous. Chapter A New Drain Current Model for GaAs MESFET 106 ∂g m ∂2g vs. Vgs and m vs. Vgs ∂V gs ∂ Vgs Figure 4.11 and 4.12 provide the simulated characteristics respectively. As demonstrated by these figures, higher order derivatives of the new model remains continuous. The new model and its derivatives are all well behaved, providing superior prediction of device behavior. All the above calculations and measurement data are for a 2*150μm wafer device. 0.07 0.06 0.04 m dg /dV gs (S/V) 0.05 0.03 V ds =2.0 V 0.02 0.01 -2 V -1.5 -1 =0.2 V -0.5 V Figure 4.11 Simulated ds gs 0.5 (V) ∂g m vs. Vgs characteristic based on the new model (2*150μm ∂V gs wafer device). The new nonlinear model function implemented for the drain current can accurately describe the FET behavior around various areas of the bias spectrum: linear, knee, saturation, and pinch-off regions. It converges smoothly toward zero when Vgs drops below pinch-off. It is capable of following the negative slope as observed in most practical MESFET’s operating in the saturation region at high value of gate voltage where the electron traps and self-heating effects become prominent. Chapter A New Drain Current Model for GaAs MESFET 107 0.5 0.4 (S/V ) 0.3 0.2 ds =2.0 V m d g /d V gs V 0.1 V ds =0.2 V -0.1 -0.2 -2 -1.5 -1 -0.5 V Figure 4.12 Simulated ∂ gm ∂ 2Vgs gs 0.5 (V) vs. Vgs characteristic based on the new model (2*150μm wafer device). 4.4 Numerical Results and Discussions 4.4.1 Model Parameter Extraction The devices used to verify the new model are a 2*150µm, a 16*125µm, and a 4*25µm sub-micron gate-length MESFET devices (wafer device) and a Fujitsu FLC103WG packaged high power MESFET transistor. The S-parameter data are measured at multi-bias condition. The small-signal equivalent circuit models are extracted under multi-bias conditions using the cold-FET method combined with the multi-plane data fitting approach [26]. All the parasitic element values are kept constant in the large-signal model. The extracted parasitic element values are listed in Table 4.3 and Table 4.4 respectively for the 2*150µm wafer device and Fujitsu FLC103WG. Chapter A New Drain Current Model for GaAs MESFET 108 Table 4.3 Parasitic Element Values of the Small-signal Equivalent Circuit (2*150µm Wafer device) Cpg(fF) Cpd(fF) Lg(pH) Ld(pH) Ls(pH) Rs(Ω) Rg(Ω) Rd(Ω) 32.9 30.1 155.4 160.6 3.0 2.1 5.9 4.3 Table 4.4 Parasitic Element Values of the Small-signal Equivalent Circuit (Fujitsu FLC103WG) Cpg(pF) Cpd(pF) Lg(nH) Ld(nH) Ls(pH) Rs(Ω) Rg(Ω) Rd(Ω) 1.31 0.436 1.49 1.29 59.5 0.99 1.53 1.96 Pulsed DC I-V characteristics of the device are measured at the extrinsic bias plane. After de-embedding of the parasitic elements, DC I-V characteristics at intrinsic device plane are obtained. The large signal model parameters are extracted from the drain current I-V data at the intrinsic device plane, and are listed in Table 4.5 and Table 4.6 respectively for the 2*150µm wafer device and Fujitsu FLC103WG. All the parameter extractions are performed by an in-house developed software running under MATLAB by MathWorks. A simplex algorithm is used for the optimization. Table 4.5 Model Parameters for the New Drain Current Model (2*150µm Wafer device) VTO (V) γ VST b1 b2 b3 -1.21 0.0358 0.103 -0.71 2.783 4.235 b4 b5 g MVST cpin 14.31 23.96 0.146 0.162 1.562 Chapter A New Drain Current Model for GaAs MESFET 109 Table 4.6 Model Parameters for the New Drain Current Model (Fujitsu FLC103WG) VTO (V) γ VST b1 b2 b3 -2.28 0.00916 0.436 -4.85 0.78 0.241 b4 b5 g MVST cpin 102.4 221.86 -0.136 -0.068 4.87 4.4.2 Modeling Results and Discussions Figure 4.13 and 4.14 shows the comparison between the modeled drain current with the measured data of a 16*125μm and a 4*25μm 0.5μm gate-length high power GaAs MESFET respectively. 700 New model Measured data 600 400 I ds (m A ) 500 300 200 100 0 V ds 10 (V) Figure 4.13 Comparison of measured and modeled drain current characteristics by the new model, 16*125μm MESFET wafer device, Vgs=-3.1 V – 0.5V. Chapter A New Drain Current Model for GaAs MESFET 110 250 New model Measured data 150 I ds (mA) 200 100 50 0 V ds 10 (V) Figure 4.14 Comparison of measured and modeled drain current characteristics by the new model, 4*25μm MESFET wafer device, Vgs=-3.0V – 0.5V. As observed from Figures 4.13 and 4.14, the new model provides accurate prediction of device drain current for both high current and low current operation. The current drop at high current due to self-heating effect is precisely modeled. A small fluctuation is observed for Ids measurement data, especially at high current region. This may be caused by the measurement setup. Model parameters for a 2*150µm sub-micron gate-length on-wafer MESFET device are extracted for Curtice model, Chalmers model, Parker model and the new model. The purpose is to compare the performance of the new model with other commonly used models. The modeled drain current results using Curtice model [61], Chalmers model [64], Parker model [70] and the new model are plotted in Figure 4.15 together with the measured data. It is seen that the overall performance of Curtice model [61] is poor. The fitting error is quite significant in the linear region, the knee region and the saturation region Chapter A New Drain Current Model for GaAs MESFET 111 especially as the drain current is reduced. Also, it has a conditional cutoff in the pinch-off region. Chalmers model [64] offers an improvement over the Curtice model. The fitting accuracy in the linear region and the saturation region is much better, and the transition to pinch-off is continuous. But, the fitting of the Chalmers model in the knee region, saturation region and for small drain current is still poor. Both the Parker model [70] and the proposed new model give very accurate fitting results over various device operation regions. The Parker model [70] also gives continuous transition over different operating conditions. 80 Vgs=0.5V 70 Vgs =0.3V 60 ( mA ) 50 Vgs =0.0V New model Meas ured data Parker model Chalmers Model Curtic e Model Vgs=-0.4V 30 I ds 40 20 Vgs=-0.8V 10 Vgs=-1.2V Vgs=-1.4V -10 0.5 1.5 V ds 2.5 3.5 (V) Figure 4.15 Comparison of measured and modeled drain current characteristics of the new model, Parker model, Chalmers model and Curtice model, 2*150μm wafer device. Figures 4.13 to 4.15 show that the simulated drain current results using the new model match the measured I-V characteristics perfectly. The two results are in good agreement in different device operation regions, especially the linear and knee regions that are difficult to model. The small negative Ids vs. Vds slope for large Ids is well Chapter A New Drain Current Model for GaAs MESFET 112 described by the new model. The modeled drain current goes smoothly to zero when Vgs approaches or drops below pinch-off. The new model also gives an accurate sub-threshold modeling, as indicated in Figures 4.16 and 4.17 for the 2*150μm device. Figure 4.16 shows the comparison of measured and modeled drain current characteristics in sub-threshold region. Figure 4.17 shows the measured and simulated gm results near pinch-off region of the same device. Both figures show superior match between modeled and measured characteristics when the device approaches pinch-off. The new model provides very accurate device sub-threshold behaviour prediction. Another major advantage of the new model is its continuity. As discussed in the earlier section, the model as well as its higher order derivatives with respective to both Vgs and Vds are all continuous over the entire device biasing spectrum. Thus, the model is capable of providing realistic description for inter-modulation distortion. V =-1.2 V gs New model Measured data I ds (mA) V gs=-1.4 V Vgs=-1.7 V V =-2.0 V gs -1 0.5 1.5 V (V) 2.5 3.5 ds Figure 4.16 Comparison of measured and modeled drain current characteristics around pinch-off region. Calculations are based on the new model, Vpinchoff = -1.21V, 2*150μm wafer device. Chapter A New Drain Current Model for GaAs MESFET 113 0.03 Vgs=-1.0 V 0.025 0.02 Vgs=-1.2 V gm (S) 0.015 New model Measured data 0.01 Vgs=-1.4 V 0.005 -0.005 Vgs=-1.7 V 0.5 1.5 Vds (V) 2.5 3.5 Figure 4.17 Comparison of measured and simulated gm characteristic close to pinchoff based on the new model (2*150μm wafer device). Table 4.7 Comparison of the Maximum Fitting Error and RMS Error of the New Model with Curtice Model, Chalmers Model and Parker Model (2*150μm Wafer device) Models New Model Parker Model Curtice Model Chalmers Model Models New Model Parker Model Curtice Model Chalmers Model Vgs=0.5V Vgs=0.0V Vds=0.5-4.0V Vds=0.5-4.0V Max. Err. RMS Err. Max. Err. RMS. Err. (%) (%) (%) (%) 1.90 0.78 1.54 0.50 1.17 0.55 1.81 0.72 6.77 3.26 2.81 1.48 5.19 2.71 2.70 1.08 Vgs=-0.8V Vgs=-1.2V Vds=0.5-4.0V Vds=0.5-4.0V Max. Err. RMS Err. Max. Err. RMS Err. (%) (%) (%) (%) 2.43 1.20 1.31 0.75 1.82 1.00 17.89 10.13 18.83 11.14 146.81 82.60 16.75 8.78 45.47 27.39 Vgs=-0.5V Vds=0.5-4.0V Max. Err. RMS Err. (%) (%) 0.56 0.26 1.46 0.52 7.73 3.91 6.13 3.83 The maximum fitting error and the RMS error of Curtice model, Chalmers model, Parker model and the new model are calculated and listed in Table 4.7 for Chapter A New Drain Current Model for GaAs MESFET 114 comparison. The calculation is made under five bias levels for Vgs, while Vds changes from 0.5V to 4.0V (on-wafer 2*150μm device). Table 4.7 shows that both the maximum fitting error and the RMS error are greatly reduced for the new model as compared to Curtice model and Chalmers model. The maximum fitting error and RMS error for both the Parker model and the new model are all very small. But, near pinch-off condition ( Vgs = −1.2V , V pinchoff = −1.21V ), the new model produces a much better fitting result as compared to Parker model. The newly proposed model contains more model parameters than the Curtice model [61] and Chalmers model [64]. But, from the parameter extraction procedure, we can see that there is no significant increase in simulation time required for the new model. This is because the new model only uses simple functions instead of hyperbolic-tangent type of function which requires more simulation time, and most importantly, the model is continuous. The proposed model gives a comparable performance to the Parker model [70], and the number of model parameters is one less than Parker’s model. The new model can be easily implemented into EDA tools, and could be very useful in microwave circuit simulation. 4.4.3 Amplifier Design Result A single stage class AB amplifier is designed and fabricated using a Fujitsu FLC103WG to verify the performance of the new model. Figure 4.18 shows the modeled and measured DC I-V characteristic of the Fujitsu FLC103WG. Good agreement was obtained. The MESFET is biased at Vgs = −1.8V , and Vds = 6.5V for a class AB operation. The designed amplifier operates from 4.2 to 4.7GHz with a gain of 10dB. Chapter A New Drain Current Model for GaAs MESFET 115 400 New model Measured data 350 300 Ids (mA) 250 200 150 100 50 0 Vds (V) 10 Figure 4.18 Comparison of measured and simulated I-V characteristic of Fujitsu FLC103WG based on the new model. Figure 4.19 Comparison of measured and simulated S21 of the amplifier. Chapter A New Drain Current Model for GaAs MESFET 116 Figure 4.20 The measured third order inter-modulation distortion of the amplifier, (Pin=10 dBm). Figure 4.21 The simulated third order inter-modulation distortion of the amplifier, (Pin=10 dBm). Chapter A New Drain Current Model for GaAs MESFET 117 Figure 4.22 The measured third order inter-modulation distortion of the amplifier, (Pin=–10 dBm). Figure 4.23 The simulated third order inter-modulation distortion of the amplifier, (Pin=–10 dBm). Chapter A New Drain Current Model for GaAs MESFET 118 Both the S-parameters and third order inter-modulation distortions are measured and compared. The two-tone input signals are at 4.5GHz and 4.51GHz respectively. Figure 4.19 shows the measured and simulated S21 performance of the amplifier. Figures 4.20 and 4.21 are the measured and simulated third order inter-modulation distortions at 10dBm input power respectively. Figures 4.22 and 4.23 are the measured and simulated third order inter-modulation distortions at -10dBm input power respectively. The simulated response and the measured performance are in good accordance. The above results show that the new model is capable of accurately representing the actual device characteristics over an extended range of operating conditions. The new empirical model function for drain current characteristics is unique as compared to most commonly used models [61,64,70]. The new model equations use a third order polynomial of effective gate-source voltage Veff, which in turn is described by a rational function of Vgs. Model performance near pinch-off regions is greatly improved through the use of a special transformation for Vgs. Moreover, the model and its derivatives are continuous, which gives a smooth transition to different operation regions. The model equations only adopt simple functions, thus, the parameter extraction is simple. It can be a useful tool for modern communication and microwave circuits design. [...]... resistance of a MESFET device Parasitic gate resistance of a MESFET device Resistor introduced in some small signal equivalent circuits to fit the Y12 Equivalent charge resistance of a MESFET device Parasitic source resistance of a MESFET device Output resistance of a MESFET device List of Symbols Pin Pout q Qg S 11, S12,S 21, S22 Vbi Vds VDsat Vgd Vgs Vpinchoff,VT0, Vp VST Z 11, Z12,Z 21, Z22 Y 11, Y12,Y 21, Y22 α... .15 9 Figure 6 .14 Modeled and simulated S-parameter for the 10 *10 0µm MESFET (Vgs =1. 0V, Vds=8V, f=0.5-20GHz, •••• measured,  modeled) (a) S 11, (b) S12 *10 , (c) S 21/ 15, and (d) S22 16 0 Figure 6 .15 Modeled and simulated S-parameter for the 12 *10 0µm MESFET (Vgs =1. 0V, Vds=8V, f=0.5-20GHz, •••• measured,  modeled) (a) S 11, (b) S12 *10 , (c) S 21/ 15, and (d) S22 16 1 Figure 6 .16 Modeled... Transconductance of a MESFET device Drain-to-Source current of a MESFET device Saturation drain source current of a MESFET device with zero gate-to-source bias applied Current flowing through the gate terminal of the MESFET device Boltzmann’s constant Gate length of a MESFET device Parasitic drain inductance of a MESFET device Parasitic gate inductance of a MESFET device Parasitic source inductance of a MESFET device. .. pinch-off region Calculations are based on the new model, Vpinchoff = 1. 21V, 2 *15 0μm wafer device .11 2 Figure 4 .17 Comparison of measured and simulated gm characteristic close to pinchoff based on the new model (2 *15 0μm wafer device) 11 3 Figure 4 .18 Comparison of measured and simulated I-V characteristic of Fujitsu FLC103WG based on the new model .11 5 Figure 4 .19 Comparison of measured... Vgs=0.0V, Vds=2.0V 14 4 Figure 6 .1 RMS errors of S-parameter calculated from the large signal model as a function of bias (a) S 11, (b) S12, (c) S 21, and (d) S22 14 8 Figure 6.2 RMS errors of S-parameter calculated from small signal equivalent circuit at different bias (a) S 11, (b) S12, (c) S 21, and (d) S22 14 9 Figure 6.3 Single-tone large signal test result for a 2 *15 0µm MESFET ( Simulation,... current as a function of Vds for a 16 *12 5µm GaAs MESFET, Vgs=-2.7V-0.5V 22 Figure 2.7 Output conductance as a function of Vds for a 16 *12 5µm GaAs MESFET, Vgs= -1. 1V-0.5V (● Vgs= -1. 1V,   Vgs=-0.7V —— Vgs=-0.3V, Vgs=0.1V, ο Vgs=0.5V) 22 Figure 2.8 Measured drain current characteristics around pinch-off region, Vpinchoff = 1. 21V 24 Figure 3 .1 Adding of device Z-parameter... modeled) 15 8 Figure 6 .11 Comparison of modeld and measured pulse I-V resultfor the 12 *10 0µm device (Vgs = –3.0-0.5V, Vds = 0 -10 V, •••• measured,  modeled) 15 8 Figure 6 .12 Comparison of modeled and measured pulse I-V result for the 16 *10 0µm device (Vgs = –3.0-0.5V, Vds = 0 -10 V, •••• measured,  modeled) 15 9 Figure 6 .13 Comparison of modeled and measured gate capacitances at Vds=8.0V for the 12 *10 0µm device. .. Imaginary parts 50 x List of Figures Figure 3 .11 Real and imaginary parts of Z parameters versus frequency, 2 *10 0μm MESFET (Vgs>Vbi, floating drain, Z 11, —— Z12, ○○○ Z 21, ●●● Z22) (a) Real parts, and (b) Imaginary parts 51 Figure 3 .12 Real part of Z 11 versus 1/ Igs for a 2 *10 0μm MESFET (Vgs>Vbi>0, floating drain) 51 Figure 3 .13 Imaginary parts of Y parameters against frequency...List of Figures List of Figures Figure 2 .1 Cross-sectional view of a MESFET 12 Figure 2.2 Basic current-voltage characteristics of a MESFET .13 Figure 2.3 MESFET small -signal equivalent circuit including parasitic elements 15 Figure 2.4 Physical origin of the MESFET small signal model 15 Figure 2.5 Equivalent circuit for MESFET large- signal model 19 Figure 2.6 Measured... 0.5μm gate length ( Y 11, —— Y12, ○○○ Y 21, ● Y22) (a) 2 *15 0μm MESFET, and (b) 2 *10 0 μm MESFET 54 Figure 3 .14 Parasitic capacitance extraction using Dambrine’s and White’s model (— —Vgs=-5.0, Vgs=-2.0, ● Vgs= -1. 7) (a) 2 *10 0μm MESFET, and (b) 2 *15 0μm MESFET .56 Figure 3 .15 Measurement results for Im(Y22)+Im(Y12), Im(Y22)+2*Im(Y12), and Im(Y22)+ (1+ α)*Im(Y12) under three different . Introduction 1 1. 1 History 1 1. 2 Device Model 4 1. 3 Objectives 5 1. 4 Scope of this work 6 Chapter 2 Basic Operation and Device Models 11 2 .1 Device Description 12 2.2 Physical Meaning of Small -Signal. A.8 TriQuint’s Own Model 18 9 A.9 TOM-2 GaAs MESFET Model 18 9 A .10 Model Proposed by V.I. Cojocaru and Brazil 19 1 A .11 Tajima MESFET Model 19 1 A .12 Parker MESFET Model 19 2 Appendix B TEE Network. V pinchoff ,V T0 , V p Pinch-off or threshold voltage of a MESFET device V ST Model parameter for the new drain current model Z 11 ,Z 12 ,Z 21 ,Z 22 Z-parameter of the device Y 11 ,Y 12 ,Y 21 ,Y 22