Large signal modeling of gaas MESFET device 2

Chapter A New Charge Model for GaAs MESFET 119 Chapter A New Charge Model for GaAs MESFET 5.1 Introduction The large signal equivalent circuit as shown in Figure 4.1 is used to model the nonlinear performance of a MESFET. As mentioned before, there are a few nonlinear properties in the equivalent circuit. Among them, the most important ones are the DC I-V characteristics and the nonlinear gate capacitance Cgs and Cgd. Charge (capacitance) modeling of MESFET is very important for accurately simulating transistor nonlinear behavior. The accuracy of the charge (capacitance) model affects the simulation result for frequency dependent characteristics like S-parameter, as well as nonlinear properties including distortion, harmonic analysis, third order intermodulation product (TOI), and ACPR (Adjacent-Channel Power Ratio) etc. Therefore, charge (capacitance) modeling is very important for the design of nonlinear circuits using MESFETs, especially power amplifiers. Accurate estimation of quantities of interest for power amplifier at the design stage demands an accurate MESFET capacitance model. In Chapter 2, the basic operation of the MESFET is briefly discussed. Physically, the depletion layer beneath the gate creates a continuous space-charge region under the gate that expands from the source region to the drain region. The charge in this depletion region is balanced by an equal amount of charge on the gate electrode. The gate charge changes with gate to source and drain to source voltage. As a result, Cgs and Cgd each depend on both Vgs and Vds, they are not two-terminal capacitors that Chapter A New Charge Model for GaAs MESFET 120 depend only on the voltage across them. The gate drain capacitance Cgd is considerably smaller in magnitude than Cgs except in a certain transition region where both drain and source voltages are approximately equal. Charge is a constitutive relation that cannot be directly measured. The nonlinear capacitances are usually extracted from S-parameter measurement in the whole transistor working domain. There are different ways in modeling MESFET charge (capacitance). Physical models as proposed by Takada et al. [102], Shur et al. [103,104], Snowden et al. [44,47,105] and D’Agostino and Beti-Beruto [106] require a detailed knowledge of the device physical construction to fit measurement data. Multi-dimensional spline functions are employed in table-based models. The empirical model is the most commonly used approach in GaAs MESFET nonlinear modeling, it uses analytical functions to describe bias dependence of the capacitances. Extensive work has been done in MESFET charge modeling, and several models have been proposed. But, the number of models is less than that of DC I-V models for which a large variety of empirical formulations have been proposed. The existing MESFET capacitance models can be classified into two groups. In the first group of models, analytical equations are found to fit Cgd and Cgs separately, and the equations not satisfy terminal charge conservation. These models may be difficult to implement in circuit simulators whose capacitance is always the derivative of an internal state variable (charge). In addition, the simulation may have convergence problems if charge conservation is not maintained. These include the model proposed by Scheinberg et al. [107], Angelov et al. [64], and Rodriguez et al. [66]. In the second group, analytical equations are proposed for terminal charge, and the capacitor values are derived from the partial derivatives of charge with respect to the Chapter A New Charge Model for GaAs MESFET 121 appropriate voltages, such as Statz model [58] and the model proposed by Parker and Skellern [70]. Modeling MESFET capacitance precisely is complicated. Most existing models are capable of accurately describing capacitance performance in only certain device operation regions. Modeling in the linear region and in the saturation knee region is difficult, and normally the inaccuracy is most significant. Capacitance fitting at Vds=0 and in sub-threshold region are generally poor too. Charge (capacitance) performance is critical in predicting the nonlinear characteristics of MESFETs and circuits using them. Thus, accurate capacitance modeling is important. In this chapter, some widely used gate capacitance models are first investigated. A new gate charge model is subsequently proposed. The model equation is unique, and it is accurate under various device biasing conditions. Most specially, the performance prediction in the linear region, saturation knee region, sub-threshold region and at Vds=0 is greatly improved. A sub-micron MESFET device is adopted to verify the proposed model. Gate capacitances Cgs and Cgd are extracted from measured S-parameters in the whole device working region under various biasing levels. Terminal voltages at the intrinsic device are used in model parameter extraction of the nonlinear charge model. Terminal voltages at the intrinsic device plane are obtained after de-embedding of the parasitic elements. 5.2 A Study of Some Existing Empirical Gate Capacitance Models Two of the most widely used MESFET capacitance models are the models based on pn junction depletion capacitance formula [7] and Statz model [58]. In this Chapter A New Charge Model for GaAs MESFET 122 section, these two models are compared and discussed. A detailed model formulation of each model can be found in Appendix A. 5.2.1 Diode Junction Capacitance Model In the diode junction capacitance model, both Cgs and Cgd are modeled as two terminal capacitors whose capacitances depend only on the voltage cross them. Gatesource and gate-drain capacitance share the same expression which is given by equation 5.1, and is expressed as: C gs , gd = C gs , gd  Vgs , gd 1 − Vbi     m . (5.1) In equation 5.1, Cgs0 and Cgd0 represent gate–source and gate-drain capacitance at zero Vgs bias respectively, Vbi is the built-in voltage of the Schottky gate, and m is the capacitance gradient factor. In some models like the Curtice model, m is assumed to be 0.5, however, with m as model parameter allows C-V relationship to be more accurately modeled. Equation 5.1 was originally developed for silicon devices, and it works well for silicon-based devices. However, model accuracy is poor when equation 5.1 is applied to GaAs MESFET devices. This is because of the linear approximation law, i.e. (log(Cgs0,gd0/Cgs,gd)=mlog(Vbi-Vgs,gd)-mlog(Vbi)). Also, the model assumes Cgs and Cgd only depends on the voltage across them, drain-source voltage dependence is not included. This assumption does not agree with real GaAs MESFET device operation and large fitting errors can be introduced into simulations, especially for operation at low drain to source voltage. Equation 5.1 cannot be used to represent device capacitance when the device is forward biased. Chapter A New Charge Model for GaAs MESFET 123 5.2.2 Statz Model In the Statz model [58], a simple gate charge Qg expression was proposed. The model was based on the observation of the measured Cgs and Cgd characteristic. Gate source capacitance Cgs can be approximated by the diode junction capacitance model in the normal bias range where Vds>>0. Gate drain capacitance Cgd is small in this same voltage range as compared to Cgs, Its value is approximately constant and nearly independent of Vgs or Vgd. The Statz model gate charge expressions are given as follows. For Vn>Vmax,    V Q g = C gs 2Vbi 1 − − max   Vbi    C gs = C gd = ∂Q g ∂Vgs ∂Qg ∂Vgd = C gs K K1 = C gs K K1 V − max Vbi V − max Vbi  Vn − Vmax +  V  − max Vbi   +C V , gd eff    (5.2) + C gd K , (5.3) + C gd K , (5.4) for Vn≤Vmax,  V  Q g = C gs 2Vbi 1 − − n  + C gd 0Veff , Vbi   C gs = C gd = ∂Q g ∂Vgs ∂Qg ∂Vgd = C gs K K1 = C gs K K1 V 1− n Vbi V 1− n Vbi (5.5) + C gd K , (5.6) + C gd K , (5.7) Chapter A New Charge Model for GaAs MESFET 124 where, 1 Veff + VT +  Vn = (V − VT ) + δ  ,  eff (5.8) Veff 1 1   = Vgs + Vgd + (Vgs − Vgd ) +    , 2  α    (5.9) Veff 1 = Vgs + Vgd − 2  (5.10) (V − Vgd ) gs 1 +  α   ,   Vmax=0.5, δ=0.2, K1 =  ∂Vn = 1 + ∂Veff   K2 = K3 = ∂Veff ∂Vgs ∂Veff ∂Vgd = = ∂Veff ∂Vgd ∂Veff ∂Vgs  , 2  (Veff − VT ) + δ  Veff − VT (5.11)   1 = 1 +      Vgs − Vgd  , and  (Vgs − Vgd )2 +    α   (5.12)   1 = 1 −      Vgs − Vgd  .  1  (Vgs − Vgd ) +    α   (5.13) Equations 5.9 and 5.10 are employed to achieve a gradual transition of capacitance values near Vds=0. Veff1 and Veff2 represent the bigger and the smaller value between Vgs and Vgd respectively. Parameter α produces a smooth transition width of 1/α in the value of Veff1 and Veff2 as a function of Vgs and Vgd. The transformation in equation 5.8 is employed to model capacitance beyond pinch-off. In the pinch-off region, the gate-source capacitance drops to a small value, which is normally determined by the fringing capacitance of the depletion region. The smooth transformation of equation 5.8 would set Vn to Veff1 before pinch-off, and to VT0 when Chapter A New Charge Model for GaAs MESFET 125 Veff1 is biased beyond pinch-off. Parameter δ stands for the voltage range over which the transition between Veff1 and VT0 occurs, and is set to 0.2. From equations 5.2 and 5.5, we can see that charge Qg does not change if the values of Vgs and Vgd are inter-changed. This is achieved through the transformation of equations 5.9 and 5.10. Thus, the model yields a symmetry behavior of the transistor. For positive Vds (normal operation model), Cgs shows diode capacitance behavior with Vgs, whereas in the reverse-biased direction (Vds0, and exhibits diode capacitance behavior with Vgd when Vds0, Statz model for Cgs expression approximates the simple junction capacitance model. 400 350 V gs = 0.0V C gs (fF) 300 250 V gs=-0.5V 200 V =-1.0V gs V gs=-1.2V 150 V gs=-1.4V 100 50 -0.5 V gs=-2.0V 0.5 1.5 V ds (V) 2.5 3.5 Figure 5.1 Measured and simulated Cgs characteristics using diode junction capacitance model for a 2*150μm GaAs MESFET (——modeled, ---- Measured Vgs=0.0V, οοοο Measured Vgs=-0.5V, ×××× Measured Vgs=-1.0V, ●●● ● Measured Vgs=-1.2V, +++ Measured Vgs=-1.4V, ∗∗∗∗ Measured Vgs=-2.0V, Vds=0-4.0V). Chapter A New Charge Model for GaAs MESFET 127 350 V gs = 0.0V 300 V gs V 200 =-0.5V gs = -1.0V V C gs (fF) 250 V gs gs =-1.2V =-1.4V 150 100 50 -0.5 V 0.5 1.5 V ds 2.5 gs = -2.0V 3.5 (V) Figure 5.2 Measured and simulated Cgs characteristics using Statz capacitance model for a 2*150μm GaAs MESFET (——modeled, ---- Measured Vgs=0.0V, οοοο Measured Vgs=-0.5V, ×××× Measured Vgs=-1.0V, ●●● ● Measured Vgs=-1.2V, +++ Measured Vgs=-1.4V, ∗∗∗∗ Measured Vgs=-2.0V, Vds=0-4.0V). 250 200 C gd (fF) 150 V gs =0.0V 100 V gs =-1.0V 50 -0.5 V gs =-0.5V V gs =-1.4V 0.5 1.5 V ds 2.5 3.5 (V) Figure 5.3 Measured and simulated Cgd characteristics using diode junction capacitance model for a 2*150μm GaAs MESFET (——modeled, ●●● ● Measured Vgs=0.0V, ---- Measured Vgs=-0.5V, οοοο Measured Vgs=-1.0V, ∗∗∗∗ Measured Vgs=-1.4V, Vds=0-4.0V). Chapter A New Charge Model for GaAs MESFET 128 250 V =0.0V gs 200 V =-0.5V gs (fF) 150 V =-1.0V C gd gs 100 V =-1.4V gs 50 -0.5 0.5 1.5 V ds (V) 2.5 3.5 Figure 5.4 Measured and simulated Cgd characteristics using Statz capacitance model for a 2*150μm GaAs MESFET (——modeled, ●●● ● Measured Vgs=0.0V, ---Measured Vgs=-0.5V, οοοο Measured Vgs=-1.0V, ∗∗∗∗ Measured Vgs=-1.4V, Vds=04.0V). The measured and calculated result for Cgd using the diode junction capacitance model and the Statz model are shown in Figures 5.3 and 5.4 respectively. Cgd is plotted in the bias range of Vgs = −1.4 − 0.0V and Vds = 0.0 − 4.0V . Both models show big error for Cgd as compared with measurement device Cgd result. For the junction capacitance model, this inaccuracy arises from the fact that Cgd is modeled as a two terminal capacitor whose capacitance depends on the voltage across it only. On the other hand, for the Statz model, this inaccuracy may be caused by the symmetrical assumption where the same parameters need to fit both Cgs and Cgd simultaneously. The maximum fitting error and the RMS error are illustrated in Tables 5.1 and 5.2 for Cgs and Cgd respectively. The comparisons are made for three different device operation regions, they are, (a) Vgs = −2.0 − 0.0V , Vds = 0.6V , which corresponds to Appendix A Large Signal Empirical MESFET Models   V I d = βV 1 − 1 − DT   VGT 193  ,  (A.77)    VGST  , VGT = VST (1 + M VST Vds )ln 1 + exp ( ) V + M V  ST VST ds   (A.78) Q GT    Q ( ) ( ) VGST = Vgs − VT − γ lf Vgd − γ hf Vgd − Vgd − η hf Vgs − Vgs , (A.79) γ lf = LFGAM − LFG1Vgs + LFG Vgd , (A.80) γ hf = HFGAM − HFG1Vgs + HFG Vgd , (A.81) η hf = HFETA − HFE1Vgd + HFE Vgs , (A.82) Vgs = Vgs − τ G d Vgs Vgd = Vgd − τ G d Vgd VDT = VDP dt dt , (A.83) , (A.84) ( VDP + Z + Vsat P  VGT   = Vds  Q  φ b − VT  Vsat = ξ (φ b − VT ) ) + ZV sat − (V DP + Z − Vsat ) + ZV sat , (A.85) P −Q , and VGT . ξ (φ b − VT ) + VGT (A.86) (A.87) The gate-charge model equations are given by: If Vnew < FC φ b , (A.88)  V Q gg = 2C gs 0φ b 1 − − new φb    + C gd 0Veff ,   (A.89) if FC φ b < Vnew , Q gg  (Vnew / φb − FC )2 Vnew / φb − FC  = C gs 0φ b 2 − − FC + + + C gd 0Veff2 , (A.90) 3/ 1/  4(1 − FC ) (1 − FC )   ( ) Appendix A Large Signal Empirical MESFET Models 194 where, Vnew   = Veff X C + (1 − X C )Veff + VT +   (V eff − VT )  0.2   +   (1 − X C )     ,  (A.91) ( ) (A.92) ( ) (A.93) Veff = Vgs + Vgd + Vds2 + α + γ ACVds , Veff = Vgs + Vgd − Vds2 + α + γ ACVds , and α= ξ φ b − VT . ξ +1 (A.94) Appendix B TEE Network and PI network Conversion 195 Appendix B TEE Network and PI Network Conversion B.1 TEE Network to PI Network Conversion R'1 R1 R1 R'2 R2 R'2 Figure B.1 TEE network to PI network conversion. R'1 = R2 ⋅ (2 R2 ) + R1 , and R1 (B.1) R' = R2 + R1 . (B.2) B.2 PI Network to TEE Network Conversion R1 R'1 R2 R2 R'1 R'2 Figure B.2 PI network to TEE network conversion. Appendix B TEE Network and PI network Conversion 196 R'1 = R1 ⋅ R2 , and R2 + R1 (B.3) R' = R22 . R2 + R1 (B.4) Appendix C Small Signal Parameter Extraction Formulation 197 Appendix C Small Signal Parameter Extraction Formulation The expression below applies to the formulations throughout this appendix. Also, N in the following equations refers to the number of frequency points. f = 10 , f = fk * f0 , ω k = 2πf k , and ω = 2πf k f . (C.1) Where, fk is the frequency at the kth measurement point in GHz. C.1 Circuit Topology with Seven Intrinsic Elements Figure 3.25 shows the most commonly used GaAs MESFET small signal equivalent circuit topology. The intrinsic device has seven elements Cgs, Cgd, Ri, gm, τ, gds and Cds. The parameter extraction formulae are separately derived for two methods, namely analytical method, and least-square error function with frequency as the weighting factor. C.1.1 Analytical Method 1. Control Voltage V Taken from the Voltage Between Cgs For the small-signal equivalent circuit in Figure 3.25, the Y-parameter of the intrinsic device can be expressed as the following form if the control voltage V is taken from the voltage between Cgs.  ω Ri C gs2  C gs  C gd + + j ω  2  + ω Ri2 C gs2 [Y ] = 1 + ω C gs Ri − jωτ gme  − jωC gd + jωRi C gs        .  g ds + jωC ds + jωC gd   − jωC gd (C.2) Appendix C Small Signal Parameter Extraction Formulation ωRi C gs = C gd = − Re (Y11 ) , Im(Y11 ) + Im(Y12 ) 198 (C.3) Im(Y12 ) , ω (C.4) g ds = Re(Y22 ) , (C.5) Cds = Im(Y22 ) + Im(Y12 ) , ω (C.6) C gs = [Im(Y11 ) + Im(Y12 )]2 + [Re(Y11 )]2 , [Im(Y11 ) + Im(Y12 )]ω (C.7) Ri = Re(Y11 ) Re(Y11 ) = , [Im(Y11 ) + Im(Y12 )](ωCgs ) [Re(Y11 )] + [Im(Y11 ) + Im(Y12 )]2 gm = τ = [(Re(Y 21 ]( ) ) ) + (Im(Y21 ) − Im(Y12 )) + ω Ri2C gs2 , and  − ωRi C gs Re(Y21 ) − Im(Y21 ) + Im(Y12 )   . sin −1  ω gm   2. (C.8) (C.9) (C.10) Control Voltage V Taken from the Voltage across Cgs and Ri For small-signal equivalent circuit in Figure 3.25, the Y-parameter of the intrinsic device can be expressed as the following form if the control voltage V is taken from the voltage cross Cgs and Ri.  ω Ri C gs2    C gs   + j ω + C − j ω C   gd gd 2  + ω Ri2 C gs2  1 + ω C gs Ri .   − j ωτ  g me − jωC gd g ds + jωC ds + jωC gd   gm = τ= (Re(Y21 ) )2 + (Im(Y21 ) − Im(Y12 ) )2 , and  − Im(Y21 ) + Im(Y12 )   . tan −1  ω Re(Y21 )   (C.11) (C.12) (C.13) The expressions for Cgd, gds, Cds, Cgs, and Ri are the same as those in equations C.3 to C.8. Appendix C Small Signal Parameter Extraction Formulation 199 C.1.2 Least-Square Error Function with Frequency as the Weighting Factor 1. Control Voltage V Taken from the Voltage between Cgs The small signal equivalent circuit is as in Figure 3.25. The extraction equations are: C gd ∑ω =− f ∑ ω k4 g ds = C ds Im(Y12 ) k (C.14) ∑ ω Re(Y ) , ∑ω k 22 (C.15) k ∑ ω [Im(Y ) + Im(Y )] , = f ∑ω (C.16) ∑ ω A1 , = f ∑ω (C.17) k 22 12 k C gs , k k Ri ∑ ω A2 , = ∑ω (C.18) gm ∑ ω A3 , = ∑ω (C.19) τ= k k k k ∑ω k sin −1 ( A4) f ∑ ω k4 , (C.20) 2 [ Im(Y11 ) + Im(Y12 )] + [Re(Y11 )] , A1 = [Im(Y11 ) + Im(Y12 )] A2 = A3 = Re(Y11 ) [Re(Y11 )] + [Im(Y11 ) + Im(Y12 )]2 [(Re(Y 21 (C.21) , (C.22) ) ) + (Im(Y21 ) − Im(Y12 ) )   [ Re(Y11 )] , and 1 + 2  [Im(Y11 ) + Im(Y12 )]  ] (C.23) Appendix C Small Signal Parameter Extraction Formulation − A4 = [(Re(Y )) + (Im(Y21 ) − Im(Y12 )) 21 2. Re(Y21 ) Re(Y11 ) − Im(Y21 ) + Im(Y12 ) Im(Y11 ) + Im(Y12 )   [ Re(Y11 )] 1 + 2  [Im(Y11 ) + Im(Y12 )]  ] 200 . (C.24) Control Voltage V Taken from the Voltage across Cgs and Ri The following equations apply to the parameter extraction when the control voltage V is taken from the voltage cross Cgs and Ri: gm τ= ∑ ω A3 , = ∑ω k (C.25) k ∑ω k tan −1 ( A4) f ∑ ω k4 , A3 = [(Re(Y A4 = − Im(Y21 ) − Im(Y12 ) . Re(Y21 ) 21 (C.26) ] ) ) + (Im(Y21 ) − Im(Y12 ) ) , and (C.27) (C.28) The expressions for Cgd, gds, Cds, Cgs, and Ri are the same as those in equations C.14 to C.18. C.2 Circuit Topology of Eight Intrinsic Elements with Cdc Introduced In the small signal equivalent circuit topology shown in Figure 3.26, an additional capacitance Cdc is added to account for drain electrode to conduction channel feedback current. There are totally eight intrinsic device elements Cgs, Cgd, Ri, gm, Cdc, τ, gds and Cds. The parameter extraction formulae are separately derived for two methods. They are analytical method, and least-square error function with frequency as the weighting factor. Appendix C Small Signal Parameter Extraction Formulation 201 C.2.1 Analytical Method 1. Control Voltage V Taken from the Voltage between Cgs For the small-signal equivalent circuit in Figure 3.26, the Y-parameter of the intrinsic device can be expressed as the following form if the control voltage V is taken from the voltage between Cgs.  − ω Ri C gs C dc + jω C gs + jω C gd  + jω Ri (C gs + C dc )   ω Ri C gs C dc + jω Ri C dc g m e − jωτ + − jω C gd  + jω Ri (C gs + C dc )  + jω Ri (C gs + C dc )   + jω Ri (C gs + C dc ) .  ω Ri C dc2 + jω (C ds + C gd + C dc ) +  + jω Ri (C gs + C dc )  ω Ri C gs C dc g gs − jω C gd (C.29) C gs = Ri = [Im(Y11 + Y12 )]2 + [Re(Y11 + Y12 )]2 , (C.30) ω Im(Y11 + Y12 ) Re(Y11 ) Re(Y11 ) = , ωC gs Im(Y11 + Y12 ) [Im(Y11 + Y12 )]2 + [Re(Y11 + Y12 )]2 C dc = [ ] [Im(Y11 + Y12 )] + [Re(Y11 + Y12 )] Re(Y12 ) , Re(Y12 ) C gs = Re(Y11 ) ω Im(Y11 + Y12 ) Re(Y11 ) (C.31) (C.32) 2 Im(Y12 ) ω Ri C gs C dc (C gs + C dc ) − , ω + ω Ri2 (C gs + C dc ) (C.33) 2 Im(Y22 ) ω Ri C dc (C gs + C dc ) C ds = − C gd − C dc , + ω + ω Ri2 (C gs + C dc ) (C.34) C gd = − g ds Z= ω Ri2 C dc2 = Re(Y22 ) − , + ω Ri2 (C gs + C dc ) + jωRi C dc + jωRi (C gs + C dc ) gm = Y21 − Y12 Z , and , (C.35) (C.36) (C.37) Appendix C Small Signal Parameter Extraction Formulation    Im Y21 − Y12  g Z m −1  τ = tan  −  ω  Re Y21 − Y12  g Z  m   2. 202    .      (C.38) Control Voltage V Taken from the Voltage across Cgs and Ri For the small-signal equivalent circuit in Figure 3.26, the Y-parameter of the intrinsic device can be expressed as the following form if the control voltage V is taken from the voltage cross Cgs and Ri.  − ω Ri C gs C dc + jω C gs + jω C gd  + jω Ri ( C gs + C dc )   ω Ri C gs C dc − jωτ + − jω C gd g me + jω Ri (C gs + C dc )    + jω Ri (C gs + C dc ) .  ω Ri C dc2 g gs + jω (C ds + C gd + C dc ) +  + jω Ri (C gs + C dc )  ω Ri C gs C dc − jω C gd (C.39) g m = Y21 − Y12 , and τ=  Im(Y21 − Y12 )   . tan −1  − ω  Re (Y21 − Y12 )  (C.40) (C.41) The expressions for Cgd, gds, Cds, Cgs, Cdc, and Ri are the same as those in equations C.30 to C.35. C.2.2 Least-Square Error Function with Frequency as the Weighting Factor 1. Control Voltage V Taken from the Voltage between Cgs The small signal equivalent circuit is as in Figure 3.26. The extraction equations are: C gs ∑ ω A1 , = f ∑ω k k (C.42) Appendix C Small Signal Parameter Extraction Formulation Ri 203 ∑ ω A2 , = ∑ω k (C.43) k ∑ ω A3 , f ∑ω (C.44) ∑ ω A4 , =− f ∑ω (C.45) ∑ ω A5 , f ∑ω (C.46) g ds ∑ω A6 , = ∑ω (C.47) gm ∑ω A7 , = ∑ω (C.48) C dc = k k C gd k k C ds = k k k k k k ∑ω τ= k tan −1 (− A8) f ∑ ω k4 , (C.49) 2 [ Im(Y11 + Y12 )] + [Re(Y11 + Y12 )] , A1 = (C.50) Im(Y11 + Y12 ) A2 = A3 = Re(Y11 ) [Im(Y11 + Y12 )]2 + [Re(Y11 + Y12 )]2 [(Im(Y 11 , (C.51) ] (C.52) + Y12 ) ) + (Re(Y11 + Y12 ) ) Re(Y12 ) , Im(Y11 + Y12 ) Re(Y11 ) A4 = Im(Y22 ) + [ Re(Y12 )[Re(Y11 ) + Re(Y12 )] (Im(Y11 + Y12 ) ) + (Re(Y11 + Y12 ) ) [ Im(Y11 + Y12 ) (Im(Y11 + Y12 ) ) + [Re(Y11 ) + Re(Y12 )] ] ], (C.53) A5 = Im(Y22 ) + ω Ri' C dc'2 (C gs' + C dc' ) + ω Ri'2 (C gs' + C dc' ) ' − ωC gd − ωC dc' , ω Ri'2 C dc' A6 = Re(Y22 ) − , + ω Ri' (C gs' + C dc' ) (C.54) (C.55) Appendix C Small Signal Parameter Extraction Formulation A7 = Y21 − Y12 204 , and (C.56) Y −Y  Im 21 ' 11  gm Z  . A8 =   Y21 − Y11   Re '  gmZ  (C.57) 2. Z Control Voltage V Taken from the Voltage across Cgs and Ri The following equations apply to the parameter extraction when the control voltage V is taken from the voltage cross Cgs and Ri: gm = τ = ∑ ω A7 , ∑ω k ∑ω A7 = A8 = (C.58) k k tan −1 (− A8) f ∑ ω k4 , [Re(Y21 − Y12 )]2 + [Im(Y21 − Y12 )]2 , and Im(Y21 − Y12 ) . Re(Y21 − Y12 ) (C.59) (C.60) (C.61) The expressions for Cgd, gds, Cds, Cgs, Cdc, and Ri are the same as those in equations C.42 to C.47. C.3 Circuit Topology of Eight Intrinsic Elements with Rgd Introduced An additional resistance Rgd is added to better fit Y12 in the small signal equivalent circuit topology shown in Figure 3.27. There are totally eight intrinsic device elements Cgs, Cgd, Ri, gm, Rgd, τ, gds and Cds. The parameter extraction formulae are separately derived for two methods, namely analytical method, and least-square error function with frequency as the weighting factor. Appendix C Small Signal Parameter Extraction Formulation 205 C.3.1 Analytical Method 1. Control Voltage V Taken from the Voltage between Cgs For the small-signal equivalent circuit in Figure 3.27, the Y-parameter of the intrinsic device can be expressed as the following form if the control voltage V is taken from the voltage between Cgs.  ω R gd C gd  ω Ri C gs2  C gd C gs  + jω  + +  2 2 2 2 1+ω R C + ω Ri2 C gs2  + ω R gd C gd + ω Ri C gs  gd gd   jωC gd g m e − jωτ  −  + jωRi C gs + jωR gd C gd       1+ω R C .  jωC gd  g ds + jωC ds + + jωR gd C gd  − ω R gd C gd + jωC gd gd gd (C.62) C gd = − R gd = − [Re(Y12 )]2 + [Im(Y12 )]2 , (C.63) Re(Y12 ) (C.64) ω Im(Y12 ) [Re(Y12 )]2 + [Im(Y12 )]2 , Im(Y22 + Y21 ) , ω (C.65) g ds = Re(Y22 + Y12 ) , (C.66) C ds = C gs 2 [ Re(Y11 + Y12 )] + [Im(Y11 + Y12 )] , = Ri = gm = τ= (C.67) ω Im(Y11 + Y12 ) Re(Y11 + Y12 ) [Re(Y11 + Y12 )]2 + [Im(Y11 + Y12 )]2 [(Re(Y 21 , (C.68) ]( ) − Y12 )) + (Im(Y21 − Y12 )) + ω Ri2 C gs2 , and  Re(Y21 − Y12 )ωRi C gs + Im(Y21 − Y12 )  sin −1 − . ω gm   (C.69) (C.70) Appendix C Small Signal Parameter Extraction Formulation 2. 206 Control Voltage V Taken from the Voltage across Cgs and Ri For the small-signal equivalent circuit in Figure 3.27, the Y-parameter of the intrinsic device can be expressed as the following form if the control voltage V is taken from the voltage cross Cgs and Ri. 2  ω Rgd C gd    + jωC gd C gd C gs ω Ri C gs2  ω Rgd C gd      + + + −  j ω 2 2 2 2  + ω R C + ω R 2C  + ω R gd C gd  + ω R gd C gd + ω Ri C gs  . gd gd i gs     jωC gd jωC gd   g m e − jωτ − g ds + jωC ds + + jωRgd C gd + jωRgd C gd   (C.71) gm = τ= (Re(Y21 − Y12 ))2 + (Im(Y21 − Y12 ) )2 , and  Im(Y21 − Y12 )  tan −1 − . ω  Re(Y21 − Y12 )  (C.72) (C.73) The expressions for Cgd, gds, Cds, Cgs, Rgd, and Ri are the same as those in equations C.63 to C.68. C.3.2 Least-Square Error Function with Frequency as the Weighting Factor 1. Control Voltage V Taken from the Voltage between Cgs The small signal equivalent circuit is as in Figure 3.27. The extraction equations are: C gd ∑ ω A1 , =− f ∑ω (C.74) ∑ ω A2 , =− ∑ω (C.75) k k Rgd Cds k k ∑ω = k Im(Y22 + Y21 ) f ∑ ω k4 , (C.76) Appendix C Small Signal Parameter Extraction Formulation ∑ω = g ds C gs k Re(Y22 + Y12 ) ∑ω k 207 , (C.77) ∑ ω A3 , = f ∑ω k (C.78) k Ri ∑ω A4 , = ∑ω (C.79) gm ∑ω A5 , = ∑ω (C.80) k k k k ∑ω τ = k sin −1 (− A6) f ∑ ω k4 , (C.81) 2 [ Re(Y12 )] + [Im(Y12 )] , A1 = Im(Y12 ) A2 = A3 = A4 = A5 = A6 = 2. (C.82) Re(Y12 ) , [Re(Y12 )]2 + [Im(Y12 )]2 (C.83) [Re(Y11 + Y12 )]2 + [Im(Y11 + Y12 )]2 , (C.84) Im(Y11 + Y12 ) Re(Y11 + Y12 ) , [Re(Y11 + Y12 )]2 + [Im(Y11 + Y12 )]2 (C.85) (Re(Y11 + Y12 ) )2  , and 2  − Y ) ) + ( Im( Y − Y ) ) +  21 12 21 12 2  (Im(Y11 + Y12 ) )  [(Re(Y ] Re(Y21 − Y12 ) Re(Y11 + Y12 ) + Im(Y21 − Y12 ) Im(Y11 + Y12 )   (Re(Y21 − Y12 ))2 + (Im(Y21 − Y12 ) )2 1 + (Re(Y11 + Y12 ) )2   (Im(Y11 + Y12 ) )  [ ] . (C.86) (C.87) Control Voltage V Taken from the Voltage across Cgs and Ri The following equations apply to the parameter extraction when the control voltage V is taken from the voltage cross Cgs and Ri: Appendix C Small Signal Parameter Extraction Formulation gm τ= ∑ ω A5 , = ∑ω k (C.88) k ∑ω A5 = A6 = k tan −1 (− A6) f ∑ ω k4 208 , (Re(Y21 − Y12 ) )2 + (Im(Y21 − Y12 ) )2 , and Im(Y21 − Y12 ) . Re(Y21 − Y12 ) (C.89) (C.90) (C.91) The expressions for Cgd, gds, Cds, Cgs, Rgd, and Ri are the same as those in equations C.74 to C.79. [...]... ) (5 .25 ) (5 .26 ) 2 c *veff 1 If 2 = c7 ∗ veff 1 + c5 ∗ (e 6 − veff 2 veff 1 + veff 2 ), (5 .27 ) 3 2 2 If 3 = c9 ∗ v gs + c10 ∗ veff 2 + c11 ∗ veff 1 , f3 = ∂If 3 3 = c9 + ∗ c10 ∗ veff 2 ∗ dveff 2 + 2 ∗ c11 ∗ veff 1 ∗ dveff 1 , ∂Vgs 2 ( (5.30) ) (5.31) 1 2 v gst 0 + v gst 0 + δ 2 , 2 veff 2 = 1 2 dveff 1 = (5 .29 ) ) veff 1 = (v (5 .28 ) 2 gst 0 ∂veff 1 ∂v gs + δ 2 − v gst 0 , v gst 0 1 = 1 +  2 2 v gst... If 2 ∗ sec h 2 (c8 ∗ vds ) ∗ c8 + If 3 − C gd 0 ) , (5 .23 ) ∂Vgs ∂Qg ∂Vds (5 .21 ) If1 = c1 ∗ v gs + c 2 ∗ e 2 c3 ∗veff 1 + c4 ∗veff 2 , (5 .24 ) f1 = ∂If1 c *v 2 + c *v = c1 + c 2 ∗ e 3 eff 1 4 eff 2 ∗ (2 ∗ c3 ∗ veff 1 ∗ dveff 1 + c 4 ∗ dveff 2 ) , ∂Vgs f2 = dv ∗ v − v * dv ∂If 2 c *v 2 = c7 ∗ dveff 1 + c5 ∗ (e 6 eff 1 * 2 ∗ c6 ∗ veff 1 ∗ dveff 1 − eff 2 eff 1 eff 2 2 eff 1 ) , ∂Vgs (veff 1 + veff 2 )... S 22 (%) RMS error S21 (%) V (V) -2 0 10 10 5 0 1 5 0 1 4 0 3 2 -1 V (V) gs 1 -2 0 (c) V (V) ds 4 0 3 2 -1 V (V) gs 1 -2 0 V (V) ds (d) Figure 6.1 RMS errors of S-parameter calculated from the large signal model as a function of bias (a) S11, (b) S 12, (c) S21, and (d) S 22 The RMS error of S-parameter calculated from small signal equivalent circuit was plotted in Figure 6 .2 for comparison The small signal. .. 54 .2 23.7 17.5 11.8 65.6 18.3 Statz 26 .9 15.6 14.3 7.3 26 .9 10.4 Models Table 5 .2 Comparison of Cgd Accuracies of Diode Junction Capacitance Model and Statz Model for a 2* 150μm GaAs MESFET Vgs= -2. 0V ~ 0.0V Vgs= -2. 0V ~ 0.0V Vgs= -2. 0V ~ 0.0V Vds=0.6V Vds =2. 5V Vds=0.0V ~ 4.0V Max Err RMS Err Max Err RMS Err Max Err RMS Err % % % % % % Diode 36.5 22 .1 114.0 57.0 191.5 57.1 Statz 41.6 26 .1 50.7 32. 8 50.9 28 .7... W 2= W 2D2 um W1 =W2D 2 u m SU BST =s1 0mi l C M M S P B 1 E 0 N 3 D 9 y M b C p P a 1 s 2 s 4 1 9 W 4 = 2 0 u m E Q U A T I O N L 2 G 5 = 4 0 5 T C P M 0 P 5 5 F 7 E 3 T G C M M S P T 5 L 8 4 SUB ST=s 10m il L=1 55 u m W=4 0 um C M M S P T 7 L 6 4 W= W2D 2 um S UBS T=s 10mi l SUB ST=s 10m il W3 =W2 D2 um L=L 2D3 um W=W 2D2 um W = U L S = L B W 2 3 T D G S 2 4 = s u u 1 m m 0 m i l C M M P S 1 T 2 L... 1 L 1 3 V d 2 P V N W = d = u 2 s 1 = = 1 8 2 0 0 u m SUB ST= s10m il L=1 55 um W=4 0 u m C M P 7 5 9 S u m U B S L W T = = = L W s 2 2 1 D D 0 4 2 m i u u l m m C M M S P T 8 L 1 1 C M M S P T 3 L 7 E Q Q Q E E E E E E E Q U U U Q Q Q Q U U U U U A A A A A A A A T T T T T T T T I I I I I I I I O O O O O O O O N N N N N N N N C C L L L L W W 2 2 2 2 2 2 2 2 D D D D D D D D 2 1 4 3 2 1 2 1 = = = = =... P F 6 E 2 T G P VN W = d= u s1 = 2 =0 1 8 0 0 u m I C M M S P T 9 L 3 4 W L S = = U 1 4 B 1 u S 0 m T = u s m 1 0 m i l W L S = = U 2 4 B 0 u S 0 m T = u s m 1 0 m i l T C C M A P P 7 N 9 2 4 A O L D F C N F P C G = G P = = = 3 = = 3 1 1 p 0 0 0 F 0 0 u 0 0 m C M M P S 1 T 0 L 2 0 I W 1=W2 G1 um W2 =W2 G1 um E Q U A T I O N L 2 G 3 = L 3 D D L 2 D 2 0 5 * W 2 G 1 0 5 * W 2 D 2 W 2 = W 2 D 1 u... W 2 D 2 W 2 = W 2 D 1 u m W 1 = W 2 D 2 u m M C S M S P T 7 E 9 P 0 C T M V P I 5 A 4 I TC CM AP P2 N 26 B W = U = L S W 0 B 3 u S G T 2 m = s u 1 m 0 m i l W W 3 = 2 W = 2 3 G 0 2 u u m m C M M P S 1 T 2 L 2 8 W 4 = 2 0 u m W 1 = W C M 3 G P 1 2 2 3 3 u W =m S = L U W L B 3 3 S G G T 2 3 = s u u 1 m m 0 m i l C M P S M T 5 L 9 9 S UBS T=s 10m il L =L3 G2 um W =W3 G2 um C M P S M T 6 L 0 6 E Q E Q U... Model for GaAs MESFET 144 Table 5.5 Comparison of Cgd Accuracies of Diode Junction Capacitance Model, Statz Model and the New Model for a 2* 150μm GaAs MESFET Vgs= -2. 0V ~ 0.0V Vgs= -2. 0V ~ 0.0V Vgs= -2. 0V ~ 0.0V Vds=0.6V Vds =2. 5V Vds=0.0V ~ 4.0V Max Err RMS Err Max Err RMS Err Max Err RMS Err % % % % % % Diode 36.5 22 .1 114.0 57.0 191.5 57.1 Statz 41.6 26 .1 50.7 32. 8 50.9 28 .7 New 14.4 9.5 7 .2 4.4 17.6 8.5... um W=W 3D2 um W L U = = S W L B 3 3 T D D S 2 1 = 0 s u u 1 m m 0 m i l W=W 3D1 um SU BST =s1 0mi l S UBS T=s 10m il L= L3D 6 u m M C S M B P E 7 N 0 D 5 C M M P S 1 T 2 L 5 4 C M M P S 1 T 2 L 5 6 MC SM BP E4 N7 D4 T C C M A P P 2 N 2 4 SUB ST= s10m il L =2 0 u m W =2 0 u m B 1 I SUB ST= s10m il W1 =W3 G3 um W 2= W 3G2 um C M M S P T 8 L 8 2 W 3 = W 3 G 2 u m W 2 = 2 0 u m C M M S P T 1 L 0 2 1 S U B . 24 2 13 21 1 effeff vcvc gs ecvcIf ∗+∗ ∗+∗= , (5 .24 ) )2( 24 113 ** 21 1 1 24 2 13 effeffeff vcvc gs dvcdvvcecc V If f effeff ∗+∗∗∗∗∗+= ∂ ∂ = + , (5 .25 ) () ) * 2* ( 2 21 121 2 116 * 517 2 2 2 16 effeff effeffeffeff effeff vc eff gs vv dvvvdv dvvcecdvc V If f eff + − ∗ −∗∗∗∗+∗= ∂ ∂ =. () ) * 2* ( 2 21 121 2 116 * 517 2 2 2 16 effeff effeffeffeff effeff vc eff gs vv dvvvdv dvvcecdvc V If f eff + − ∗ −∗∗∗∗+∗= ∂ ∂ = , (5 .26 ) )( 21 2 * 51 72 2 16 effeff eff vc eff vv v ecvcIf eff + −∗+∗= , (5 .27 ) 2 111 2 3 21 093 effeffgs vcvcvcIf ∗+∗+∗= , (5 .28 ) 111 122 109 3 3 2 2 3 effeffeffeff gs dvvcdvvcc V If f. , (5 .29 ) ( ) 22 001 2 1 δ++= gstgsteff vvv , (5.30) ( ) 0 22 02 2 1 gstgsteff vvv −+= δ , (5.31)           + += ∂ ∂ = 22 0 01 1 1 2 1 δ gst gst gs eff eff v v v v dv , (5. 32) Chapter