Modeling and characterization of high dielectric constant tunnel barriers for nanoelectronic applications

MODELING AND CHARACTERIZATION OF HIGH DIELECTRIC CONSTANT TUNNEL BARRIERS FOR FUTURE NONVOLATILE MEMORY APPLICATIONS KOH BIH HIAN (B.Eng (Hons), NUS) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2005 Acknowledgements Eight years of undergraduate and postgraduate studies in the NUS campus have left both wonderful memories and as well as those stressful days that I will remember forever. The vibrant campus life and ever-changing landscape that has captivated me all these years will keep me coming back to my alma mater, no matter how far I shall venture in the future. Throughout my graduate studies, many individuals and organizations have contributed generously to my work. First of all, I would like to express my heartfelt thanks and gratitude to my thesis advisor, Assoc. Prof. Chim Wai Kin. No matter how occupied he was, he always found time to hear my problems and offer his guidance. I would like to thank Assoc. Prof. Choi Wee Kiong, for giving me unrestricted access to the equipment in Microelectronics laboratory (MicroE Lab). The work in this thesis would be impossible without his kind gesture. I also wish to acknowledge the research scholarship and President’s Graduate Fellowship from NUS, and the scholarship from Chartered Semiconductor Manufacturing Limited. I am grateful to the people who made my stay in the Center for Integrated Circuit Failure Analysis and Reliability (CICFAR) and MicroE Lab enjoyable. Thanks to staff and ex-staff of CICFAR and MicroE Lab, Mrs. Ho, Mr. Goh, Mr. Walter Lim, Yong Yu, Xiao Yun and Kar Sin, for the assistance they have given me. To the graduate students from both labs, Yeow Hoe, Merrvyn, Yan Jian, Måns, Kok Kiong, Kin Mun, Jianxin, Soon Leng, Tsu Huat, Heng Wah, Alfred, Kuan Song, Ric, Eric, Lee Wee, Li Juan, Vincent, Chen Zhong, David, Chin Heng, Guo Feng, Chen Gang, Chee Lip, Yong Tian, Gu Hua, Choon Wai, Hong Peng, Wei Yan Zheng and i others for the wonderful company and friendship they had provided. Many thanks to the honours students, Edmund, Kah Meng, Vincent, Gene, Jieyi, Karen, Sing Yang, Anthony, Kah Cheong, Chi Liang and others that I have worked together before, and hope that the friendship would last beyond this candidature. I am appreciative of the constant encouragement and advice from all my good friends, especially, Kaisheng, Jinpiau, Gerald and Jinghui. I would like to also thank my parents, who despite being unhappy with my decision to undertake graduate studies initially, nonetheless supported me morally and slowly accepted me decision. Hopefully, they would feel proud when seeing the figures and equations in the thesis. Not forgetting my brother, Damien, my sister-in-law, Deedee, and my sister, Kleo, who constantly asked me when I would be graduating. I am also thankful to my in-laws, Mum, Jason and Dad for giving me their support and encouragement. I really enjoyed all the gourmet treats they had treated me! Thanks to those who I have left out unintentionally but have helped in any way or contributed to my work. Finally, my deepest gratitude to my wife, Grace, for the patience, care and the love she has given unconditionally throughout the candidature. Koh Bih Hian, Jayson 2005 “Only those who risk going too far can possibly find out how far one can go.” -Thomas Stearns Eliot (1888-1965) ii CONTENTS Acknowledgements……………………………………………………………………. i Contents……………………………………………………………………………… iii List of Figures……………………………………………………………………… vii List of Tables…………………………………………………………………………xv Summary……………………………………………………………………………. xvi Chapter Introduction 1.1 Background 1.2 Motivation 1.3 Objectives of Project 1.4 Organization of Thesis .10 References 11 Chapter 2.1 Literature Review Review on Quantization and Tunneling Models .14 2.1.1 Carrier Quantization Models .14 2.1.2 Carrier Tunneling Models .19 2.2 Issues in Modeling of Quantization Effects and Tunneling .24 2.2.1 Effective Mass 24 2.2.2 Dispersion Relationship 25 2.2.3 Wave Function Penetration Effects 26 2.2.4 Polysilicon Depletion Effects .27 2.2.5 Image Force 28 2.3 Review on the Modeling of Nanocrystal Based Memory 29 2.4 Charge Retention Issues in Nanocrystal Based Memory .32 2.5 Review on High Dielectric Constant Materials .37 2.5.1 High Dielectric Constant Materials and Crystalline Oxides on silicon 37 2.5.2 Yittrium Oxide – A Potential Candidate for the Implementation of Crystalline Oxide on Silicon 40 iii 2.6 Crested Barrier Structure .46 2.7 Conclusion .49 References 50 Chapter Quantum Mechanical Quantization and Tunneling Model for Metal-Insulator-Semiconductor Devices 3.1 Introduction 63 3.2 Description of the Carrier Quantization Model .63 3.3 Modeling of the Gate Tunneling Current .72 3.3.1 Derivation of Recursive Equations for Gate Tunneling Current Calculation .74 3.3.2 Calculation of the Gate Tunneling Current .82 3.4 Modeling Issues and Assumptions .84 3.4.1 Conservation of Momentum .84 3.4.2 Image Force Effect in the Tunnel Barrier .85 3.4.3 Wave Function Penetration .86 3.4.4 Hole Dispersion Relationship and Effective Masses 91 3.4.5 Polysilicon depletion .96 3.5 Capacitance-Voltage Modeling .97 3.6 Current-Voltage Modeling .100 3.7 Analysis of High-κ MIS Structures Using the Developed Simulation Model 102 3.7.1 Fabrication Details of High-κ MIS Structures 103 3.7.2 Electrical Characterization of High-κ MIS Structures 105 3.7.3 Conduction Mechanism in the Non-ohmic Region of High-κ MIS Structures .108 3.7.4 Fitting of Simulated Capacitance-Voltage and Current-Voltage Characteristics of High-κ MIS Structures 113 3.8 Conclusion .117 References 118 iv Chapter High-κ Tunnel Barriers – Single Layer and Crested Barrier Stacked Structure 4.1 Introduction 124 4.2 Review of Tunnel Barriers .125 4.3 Comparison between Single High-κ Layer and Crested Barrier Structure 132 4.4 Selection of Suitable Materials and Devising a Design Rule for Crested Barrier Structures .139 4.5 Experimental Results on Si3N4/Al2O3/Si3N4 Crested Barrier Structure 151 4.6 Epitaxial Y2O3 on Si Substrate for Y2O3/Al2O3/Y2O3 or Y2O3/SiO2/Y2O3 Crested Barrier Structure .161 4.6.1 C-V Hysteresis and Trapped Charge Analysis of Y2O3 163 4.6.2 Flatband Voltage and Oxide Fixed Charge Density Analysis of Y2O3 168 4.6.3 Amorphous Yttrium Silicate Formation .171 4.6.4 Summary .174 4.7 Conclusion .175 References 176 Chapter Modeling of Charging and Discharge Mechanisms in Germanium Nanocrystal Memory Structures 5.1 Introduction 179 5.2 Modeling of Nanocrystal Memory .180 5.2.1 Modeling of Write Operation 182 5.2.2 Modeling of Erase Operation and Charge Retention 187 5.2.3 Comparison between Present and Existing Model .194 5.3 Conclusion .195 References 196 v Chapter Characterization of Discharge Mechanism in Germanium Nanocrystal Memory Structures 6.1 Introduction 199 6.2 Fabrication of Ge Nanocrystal Memory Structures .201 6.3 Characterization of Ge Nanocrystal Memory Structures .203 6.4 Retention Measurements and Trap Energy Extraction 206 6.4.1 Trap Energy Extraction by Experiment 207 6.4.2 Trap Energy Extraction by Simulation Fitting with Experimental Data 210 6.5 Discussion on the Trap Energy Level 212 6.6 Trap Level Engineering .213 References 217 Chapter Conclusion 7.1 Summary 220 7.2 Recommendations for Further Work .222 Appendix A: Calculation of Dit using Terman’s method A-1 Appendix B: Derivation of the Physical Thickness of the Stacked Dielectric B-1 Appendix C: Analyzing Transmission Coefficient of High-κ Materials using Simplified WentkelKramers-Brillouin (WKB) Approximation C-1 Appendix D: Relevant Binding Energy for X-ray Photoelectron Spectroscopy .D-1 Appendix E: List of Publications E-1 vi List of Figures Figure 2-1: Pictorial illustrations of (a) Fowler-Nordheim (F-N) and (b) direct tunneling in a nMOS structure. Vox is the oxide voltage drop and ΦB is the conduction band offset at the Si/SiO2 interface 16 Figure 2-2: Electron density in different quantization models. z is the vertical distance from the Si/SiO2 interface and n is the carrier density of the selected quantized state. After Schenk et al. [11] 17 Figure 2-3: C–t characteristics at a bias of -10 V after injecting electrons at 20 V for s. The inset shows the retention time variation as a function of bias voltage. After Kim et al. [103] .33 Figure 2-4: Energy band profiles of (a) nc-Si/SiO2/n-Si and (b) nc-Si/SiO2/p-Si structures. .35 Figure 2-5: Measured retention times as a function of the gate bias. After Compagnoni et al. [104] 35 Figure 2-6: Inversed discharging time constants divided by squared temperature (T). Etrap in the plot is equivalent to Et in this work. After Baik et al. [109] 37 Figure 2-7: (a) Basic building blocks and (b) unit cell of Yttrium Oxide. .41 Figure 2-8: Conduction band edge diagrams of various tunnel barriers: (a) a typical uniform barrier; (b) idealized crested symmetric barrier; (c) idealized asymmetric barrier; (d) crested, symmetric layered barrier; and (e) asymmetric layered barrier. Dashed lines in panels (a) and (b) show the barrier tilting caused by the applied voltage V. After Likharev [140]. .48 Figure 3-1: Schematic diagram showing the propagatory nature of wave functions in the gate electrode and the quasi-bound wave function when the n-type silicon (Si) MIS structure is biased into accumulation. ……………………………………… 64 Figure 3-2: Flow diagram showing the implementation of quantum-mechanical modeling of a MIS device incorporating the capacitance-voltage calculation procedure 71 Figure 3-3: Diagram showing the conduction band profile represented by step potentials of a MIS structure. κj is the wave number at j. zj indicates the distance of the node j from the input electrode. κin and κout are the wave numbers at the input and output electrodes, respectively .76 vii Figure 3-4: Calculated room temperature (T = 300 K) low-frequency C-V curves with (open circles) and without (solid circles) wave function penetration. The substrate doping concentration is 1x1018 cm-3, oxide thickness is nm and polysilicon doping concentration is 5x1020 cm-3 .88 Figure 3-5: (a) The eigenenergies of the first three subbands, E10, E11 and E20, with (open symbols) and without (solid symbols) wave function penetration, as a function of the surface electric field. (b) The average distance of electrons in the subbands, z10 and z20, and the average distance of total electrons, zav, from the surface with (open symbols) and without (solid symbols) wave function penetration, as a function of the surface electric field. The simulated results were obtained at a temperature T = 300 K. 89 Figure 3-6: Potential profile of a MOS device under (a) low and (b) high negative gate voltage bias. The energy difference of the quantized tunneling hole, E, with respect to the valence band edge is indicated as ΔEx and ΔEy in (a) and (b) respectively. .92 Figure 3-7: The hole direct tunneling currents in p-MOSFETs, as given by the source/drain currents in a carrier separation measurement. The open circles are the measured values. The solid and dashed lines denote the calculated values by assuming the hole dispersion in the SiO2 band gap obeys Franz type (mox = 0.55mo) and parabolic (mox = 0.4mo) relationships, respectively. mox is the hole effective mass in conduction defined in Ref. [42]. After Hou et al. [42]. .93 Figure 3-8: Plots showing the experimental source/drain (hole) current density (in open symbol, obtained from Hou et al.[42] ) and the simulated hole current density (in lines) of pMOS devices with SiO2 as the tunnel barrier. The hole current is obtained from the source/drain current in a carrier separation measurement. The doted and bold lines indicate the simulations performed using one-band and two-band dispersion relationships, respectively. The EOTs used for the simulation are indicated in the plot and they are the same as the EOTs obtained from C-V fittings in Hou et al. [42]. .95 Figure 3-9: Plots showing the experimental gate current density (in open symbol, obtained from Hou et al.[42]) and the simulated electron current density (in lines) of nMOS devices using SiO2 as insulator. The simulations are performed using a two-band dispersion relationship. The EOTs used for the simulation are indicated in the plot and they are the same as the EOTs obtained from C-V fitting in Hou et al. [42] .96 viii Figure 3-10: Quantum-mechanical C-V modeling of gate capacitance using the gate capacitance (solid line) compared to experimental measurements (open circles) on a (a) pMOSFET: Oxide thickness, Tox = 1.35 nm, Substrate doping (Nsub) = x 1017 cm-3 and polysilicon doping (Npoly) = x 1019 cm-3. (b) nMOSFET: Oxide thickness, Tox = 1.35 nm, Substrate doping (Nsub) = 8x 1017 cm-3 and polysilicon doping (Npoly) = x 1019 cm-3. 100 Figure 3-11: Schematic diagram showing the band structure and band offset values used for a p+ polySi/SiO2/n-Si MOS structure at flatband. .101 Figure 3-12: Comparison of the simulated (lines) gate current density with the experimental measurements (symbols) for a MOS structure (area = 10 x 10 μm2) with SiO2 as the gate dielectric for two different oxide thickness (Tox) of 1.57 nm and 2.05 nm. The simulated results are performed using the recursive relationship method of Casperson et al. [18]. The simulations were performed using an electron effective mass in the oxide of 0.42mo, Nsub = x 1018 cm-3 and Npoly = x 1020 cm-3 102 Figure 3-13: TEM micrograph of the (a) Al/ZrO2/ZrSixOy/n-Si MIS device, (b) Al/SiO2/HfO2/SiO2/n-Si MIS device. 105 Figure 3-14: Jg-Vg plots of typical low and high leakage devices from the Al/ZrO2/ZrSixOy/n-Si MIS structure 106 Figure 3-15: C-V plots of typical low and high leakage devices from the Al/ZrO2/ZrSixOy/n-Si MIS structure 106 Figure 3-16: Dit versus surface band bending (ψs) in a typical (a) high and (b) low leakage device from the Al/ZrO2/ZrSixOy/n-Si MIS structure. .107 Figure 3-17: Diagram showing the three different conduction regions in Ig as a function of Vg of a typical low leakage sample from the Al/ZrO2/ZrSixOy/n-Si MIS structure 108 Figure 3-18: Measured Jg-F characteristics for the (a) interfacial layer and (b) bulk ZrO2 of a typical low leakage Al/ZrO2/n-Si MIS device (area = 1.26 x 10-2 cm2) in the low gate bias region compared with that calculated based on the Schottky emission and Frenkel-Poole emission mechanisms. The calculated Jg-Vg characteristics were obtained with T = 295 K, ε = 15 (interfacial layer) or 25 (bulk ZrO2), Φt = eV (interfacial layer) or 0.9 eV (bulk ZrO2), ΦB = 1.4 eV, A = 120 A cm-2 K-2 (the free-electron Richardson constant was assumed for both the interfacial layer and bulk ZrO2), and B = 25.95 A cm-1 V-1 (interfacial layer) or 667 A cm-1 V-1 (bulk ZrO2). Values of ε used in the fitting were taken from the Q-M C-V simulation. The inset in ix [17] J. Fage-Pedersen, A.N. Larsen and A. Mesli, “Irradiation-induced defects in Ge studied by transient spectroscopies”, Physical Review B, vol. 62, no. 15, pp. 10116-10125, 2000. [18] P. Vanmeerbeek, P. Clauws, “Local vibrational mode spectroscopy of dimer and other oxygen-related defects in irradiated and thermally annealed germanium”, Physical Review B, vol. 64, no. 24, article no. 245201, pp. 1-6, 2001. [19] V.V. Litvinov, L.I. Murin, J.L. Lindstrom, V.P. Markevich, and A.N. Petukh, “Local vibrational modes of the oxygen–vacancy complex in germanium”, Semiconductors, vol. 36, no. 6, pp. 621-624, 2002. [20] V.P. Markevich, V.V. Litvinov, L. Dobaczewski, J.L. Lindström, L.I. Murin, A.R. Peaker, “Radiation-induced defects and their transformations in oxygenrich germanium crystals”, Physica Status Solidi (c), vol. 0, no. 2, pp. 702-706, 2003. [21] V.P. Markevich, I.D. Hawkins, A.R. Peaker, V.V. Litvinov, L.I. Murin, L. Dobaczewski and J.L. Lindström, “Electronic properties of vacancy–oxygen complex in Ge crystals”, Applied Physics Letters, vol. 81, no. 10, pp. 18211823, 2002. [22] H. Haesslein, R. Sielemann, C. Zistl, “Vacancies and self-interstitials in germanium observed by perturbed angular correlation spectroscopy”, Physical Review Letters, vol. 80, no. 12, pp. 2626-2628, 1998. [23] A.J.R. da Silva, A. Janotti, A. Fazzio, R.J. Baierle, R. Mota, “Self-interstitial defect in germanium”, Physical Review B, vol. 62, no. 15, pp. 9903–9906, 2000. [24] Y.M. Niquet, G. Allen, C. Deleerue and M. Lannoo, “Quantum confinement in germanium nanocrystals”, Applied Physics Letters, vol. 77, no. 8, pp. 11821184, 2000. 219 Chapter Conclusion 7.1 Summary The charge retention issue of nanocrystal based memories has been addressed in this thesis. The study on the charge retention time of nanocrystal based memories is based on the charge leakage through the tunnel barrier during low voltage bias operation. This is because the tunnel barrier is the predominant route of charge leakage in Flash memories in view of its smaller thickness as compared to the control or capping oxide. A quantum mechanical model is required for accurate calculation of the charge leakage through the tunnel barrier because of the small electrical oxide thickness of the latter. A thorough literature review on modeling of the charge quantization effect and the gate tunneling current and the charge retention issues in nanocrystal based memories have been presented. Various issues in the modeling and assumptions made were also explained in Chapter 3. Firstly, the issue of hole effective mass has been considered by using a two-band dispersion relationship approach. Wave function penetration and polysilicon depletion effects are also included in the simulation model. Electrical measurements on MOS devices were used to verify the developed simulation model. MIS structures using Al/ZrO2/ZrSixOy/n-Si and Al/SiO2/HfO2/SiO2/n-Si multilayered stack dielectrics were fabricated and measurements, as well as simulations, were performed on these structures to provide information on the interfacial and bulk quality of the high-κ films. 220 Chapter introduces tunnel barrier structures that are able to increase the charge retention time and at the same time, decrease the charging and discharging durations of nanocrystal memory devices. The concept of the crested barrier structure is explained and demonstrated through a simulation model described in Chapter 4. A simulation design rule for possible crested barrier structures is devised in this work. The design rule enables the physical thickness of each selected material/layer in the crested barrier structure to be selected based on the criterion of high electric field sensitivity to meet the specified |Vprog/Vret| ratio. Si3N4/Al2O3/Si3N4 crested barrier structures were fabricated to demonstrate the electric field sensitivity of such structures experimentally. Due to the possible epitaxial growth of Y2O3 on Si substrate for Y2O3/LBG layer/Y2O3 crested barrier structures, electron-beam evaporation of Y2O3 on Si has been investigated in this work. However, from the TEM micrographs, large amount of silicate growth is found at the Y2O3/Si interface. The presence of silicate increases the bandgap of the Y2O3 material and thus diminishes the difference between the maximum and minimum potential in the crested barrier structure. This would cause the structure to lose the high electric field sensitivity characteristic. Hence, further work is needed to find ways for minimization of the silicate formation. The modeling of the charging, discharging and charge retention mechanisms of the germanium nanocrystal memory is presented in Chapter 5. The models use the self-consistent quantum mechanical calculation method described in Chapter 3. Charge quantization effects in both the nanocrystals and Si substrate and Coulomb blockade effect during charging are considered. The discharge model in this work is based on the trap-related emission mechanism. The use of such a mechanism is the result of the observed temperature-dependent charge retention time characteristics and 221 further results that suggest trap related charge storage and discharge in the Ge nanocrystal memory structures fabricated by our research group. In Chapter 6, nanocrystalline Ge memory transistors were fabricated for investigating the trap energy level in nc-Ge. Theoretical simulations show that the trap energy level in nc-Ge lies at 0.16 eV below the Ge conduction band edge, which agree well with experimental transient drain current measurements that give an extracted trap energy level of about 0.13 eV below the Ge conduction band edge. The trap energy level is close to the reported self-interstitial trap energy level of EV + 0.31 eV in Ge. Test capacitors using nc-Ge/Al2O3 and nc-Ge/SiO2 structures were fabricated to demonstrate that a deeper trap energy level in Ge nanocrystals is able to increase the charge retention time. The results also showed that by varying the material of the tunnel oxide or the interface of the nanocrystal, the trap sites at the nanocrystals in close proximity to the tunnel oxide can be made deeper in energy level below the conduction band. Lastly, the trap energy in nc-Ge required for long term (10-year) charge retention was also obtained through simulation as a function of nanocrystal size, thus providing a direction for engineering the required trap depth to achieve a specified charge retention performance. 7.2 Recommendations for Further Work The high electric field sensitivity of Si3N4/Al2O3/Si3N4 crested barrier structures have been demonstrated in this work. The next step is to incorporate the Si3N4/Al2O3/Si3N4 crested barrier structure into the nanocrystal memory transistor. However, the nucleation of nc-Ge requires a series of high temperature and long duration annealing. Therefore, experiments have to be performed to find the optimal annealing conditions for the nanocrystal memory transistor in order to ensure that the 222 three layers in the crested barrier structure are chemically and structurally stable and, most importantly, not intermix with the neighbouring material layer. Further investigation on the deposition parameters is needed to reduce the silicate formation in the electron-beam evaporated Y2O3 film. One possible approach is to perform annealing in an oxygen free ultrahigh vacuum condition. Another factor that should be considered is the optimization of the deposition temperature. The modeling of the nanocrystal based memory in this work is based on a one-dimensional analysis. It would be useful to extend the current work to a two-dimensional model which incorporates the source and drain regions of the transistor. This would account for the non-uniformity of electric field along the channel and thus would predict more precisely the charging and discharging at the edge of the drain/source regions as in a Flash memory transistor during hot carrier programming. The quantization effect in the nc-Ge is based on the analytical approximation of the simulation results from first principles calculations. In most cases where the nanocrystal is spherical, the approximation is acceptable. However, not all nanocrystals are perfectly spherical; thus for these non-spherical cases, a first principles model is required to calculate the quantized states of the nanocrystals. It has been demonstrated that the charge retention time of the nanocrystal memory transistor is largely dependent on the trap energy level in the nanocrystals. Future work could therefore investigate the possibility of introducing deep trap energy into the nanocrystal bandgap by doping with suitable materials. Possible candidate materials are metals as metals have work functions that can be larger than the electron affinity of Ge. If the metal implanted in the nc-Ge does not react with the surrounding material, it may create a trap energy level in the nc-Ge bandgap which has a trap 223 energy given by the difference between the Ge electron affinity and the work function of the metal. Table 7-1 shows the work functions of selected metals and the electron affinity of Ge. From the prediction of the required trap energy for long-term charge retention requirement shown in Figure 6-8, it can be seen that Co, Au and Ni can easily satisfy the trap energy level for nc-Ge diameter of nm and above. However, the introduction of metallic impurities into the nanocrystal memory device may cause leakage and mobile ions and other process compatibility related issues. Table 7-1: Comparison of the electron affinity of Ge with work functions of selected metals. Material Ge Al Ag Zn Cr Sb Cu Co Au Ni Pt Electron affinity 4.0 - Work function 4.33(Intrinsic) 4.28 4.22 4.33 4.5 4.55 4.65 5.0 5.1 5.15 5.65 Source Ref.[1] in footnote Ref.[2 ] in footnote S.M. Sze, “Physics of Semiconductor Devices”, 2nd Ed., John Wiley, New York, Appendix H. H.B. Michaelson, “The work function of the elements and its periodicity”, Journal of Applied Physics, vol. 48, no. 11, pp. 4729, 1977. 224 Appendix A Calculation of Dit using Terman’s method The Terman’s method will be presented briefly as follows. First, consider the gate voltage equations for the ideal and measured cases, shown in Equations (A-1) and (A-2). Vg (measured ) = V fb − Qit Qox − +γ ψS Cox Cox V g (ideal ) = Φ ms + γ ψ S (A-1) (A-2) If Equation (A-1) is subtracted from Equation (A-2), ΔV g = V g (measured ) − V g (ideal ) (A-3) and differentiating with respect to the surface band bending, ψs, Equation (A-3) becomes d (ΔV g ) dψ S =− dQit (ψ S ) C ox dψ S dQit = − qDit dψ S (A-4) (A-5) Combining Equations (A-4) and (A-5) and re-arranging it, d (ΔV g ) dψ S = qDit C ox (A-6) A-1 which gives Dit (ψ S ) = C ox d (ΔV g ) q dψ S (A-7) To implement the method mentioned above, the first step is to simulate the ideal C-V curve and find the flatband capacitance (Cfb) which is found by locating Vfb(ideal), corresponding to ψs = 0. Since the simulated data is taken at voltages at discrete points, it is necessary to use interpolation method to find the exact point where the C-V crosses Vfb(ideal). Once the Cfb is obtained, the ideal C-V curve simulated is shifted along the voltage axis to allow both Vfb(ideal)=Vfb(measured), where Vfb(measured) is the gate voltage corresponding to Cfb on the measured C-V curve. The oxide trapped charge density (Not) is found from the voltage shift, ΔVfb, of the ideal C-V curve. The flow diagram for implementing Terman’s method is shown in Figure A-1. The code is written in Matlab in order to integrate it to the carrier quantization program which is also written in Matlab. Once the user invokes the main program, self-consistent calculations are performed. For every node point, the self-consistent result is calculated and repeated with a second applied voltage (to simulate an a.c. small signal voltage change). Once this set of self-consistent results is obtained, the gate capacitance is calculated. The function that calculates Dit, Ditcalculate.m, is then invoked. The first step performed by the function is to find Vfb (ideal) corresponding to ψs=0 to obtain the value of Cfb. Then, Vfb(measured) is found: this is the Vg corresponding to Cfb on the measured C-V curve. The ideal C-V curve is then shifted to coincide with the measured C-V curve at the flatband point. For various values of fixed ψs, the gate voltage difference ΔVg A-2 between measured and shifted ideal C-V curves is determined, and a plot of ΔVg vs ψs is obtained. Dit is obtained by using Equation (A-7). Start Main program Self-consistent calculation for bound states Simulate C-V curves Find Vfb(ideal)corresponding to ψs=0 Dit function Find value of Cfb Find Vfb(measured) Calculate voltage shift for the measured and simulated C-V to coincide at Cfb and shift the ideal C-V curve. Determine for various fixed ψs, the gate voltage difference ΔVg between measured and shifted ideal C-V curves. Plot ΔVg vs ψs. Find Dit as shown in Equation (A-7) Figure A-1: Flow Diagram for the implementation of Terman’s method. . A-3 Appendix B Derivation of the Physical Thickness of the Stacked Dielectric B.1 Dual-layered Dielectric Structure C1 ≈ C2 ≈ ε1 t1 Equivalent Capacitance, ≡ CT ≈ ε2 ε SiO tT t2 1 = + CT C1 C ε SiO = tT ε 1ε ε t + ε t1 Since t EOT _ = ε1 ε SiO t1 and t EOT _ = ε2 t2 ε SiO where tEOT_1 and tEOT_2 are the EOTs of layer and layer 2, respectively, then ε SiO t Overall = = (ε 1ε / ε SiO2 ε EOT _ 1ε EOT _ )t EOT _ + (ε 1ε / ε SiO )t EOT _ ε SiO t EOT _ + t EOT _ (B-1) Therefore the EOT of the dual-layered dielectric stack, tOverall, is obtained by adding all the individual EOT of each layer. B-1 B.2 Triple-Layered and Multi-Layered Dielectric Structure C1 ≈ C2 ≈ C3 ≈ ε1 t1 ≡ ε2 Equivalent Capacitance, CT ≈ t2 ε SiO tT ε3 t3 1 1 = + + CT C1 C C ε SiO t Overall = ε 1ε ε ε ε t1 + ε 1ε 3t + ε 1ε t Again, t EOT _ = ε1 ε SiO ε ε2 t and t EOT _ = t , where tEOT_3 is the EOT of ε SiO ε SiO t1 , t EOT _ = layer 3. ε SiO t Overall = ε EOT _ 1ε EOT _ ε EOT _ (ε EOT _ 1ε EOT _ ε EOT _ / ε SiO )(t EOT _ + t EOT _ + t EOT _ ) = ε SiO t EOT _ + t EOT _ + t EOT _ (B-2) Thus, the same relationship is derived for triple-layered stack. Therefore, it can be concluded that ε SiO t Overall = ε SiO (t EOT _ + t EOT _ + t EOT _ + K + t EOT _ n ) (B-3) where n denotes the n-th (last) layer. B-2 Appendix C Analyzing Transmission Coefficient of High-κ Materials using Simplified Wentkel-Kramers-Brillouin (WKB) Approximation C.1 Introduction The Wentkel-Kramers-Brillouin (WKB) approximation of the transmission coefficient across a single layer barrier can be derived as shown in Equation (C-1). TC ( E ) = TR ( E )TWKB ( E ) (C-1) where TR is the correction factor. In most cases, the correction factor is not considered and the transmission coefficient is approximated by TC ( E ) ≈ TWKB ( E ) and TWKB can be derived as t ox TWKB ( E ) = exp[−2 ∫ κ ( E , z )dz ] (C-2) where tox is the physical thickness of the insulator layer, κ is the wave number and z is the tunneling direction of the electron or the vertical axis of the metal-oxide-semiconductor (MOS). C.2 Single Step Barrier Assuming that the potential barrier (at flatband) is rectangular and the electron resides near the conduction band, Equation (C-2) can be further simplified as shown in Equation (C-3). C-1 TWKB ≈ exp[−2 t ox (2φ hk m * )1 / ] h (C-3) where φhk is the barrier height of the high-κ material on Si and m* is the effective mass of the high-κ material. C.3 Multilayered Stack at Flatband The above method can be modified to suit a multi-layered stack structure. Assuming that the transmission probability across each layer is independent of the adjacent layer, then n TWKB ( E ) ≈ ∏ TWKB , j (C-4) j =1 TWKB = exp{ −2 [t1 (φ hk ,1 m1* )1 / + t (φ hk , m2* )1 / + t (φ hk ,3 m3* )1 / h + K + t n (φ hk ,n mn* )1 / ]} or ε t ε t − 2 ε 1t SiO [ (φ hk ,1 m1* )1 / + SiO (φ hk , m2* )1 / + SiO (φ hk ,3 m3* )1 / ε SiO ε SiO h ε SiO ε t + K + n SiO (φ hk ,n mn* )1 / ]} TWKB = exp{ ε SiO (C-5) for a crested barrier at flatband, where φhk,n is the conduction band offset of the high-κ layer n to Si. C-2 C.4 Single Layer under Electric Field Using the similar derivation and applying to a single high-κ layer under an electric field ξ, TWKB can be derived as TWKB ≈ exp{−2 ∫ sqrt[ t ox = exp{ Am *1 / [ where A= 1/ − 2m * 3/ (φ hk − ξz )]dz} = exp{− A ' m * [ ((φ hk − ξt ox ) / − φ hk )]} 3ξ h (φ hk − ξt ox ) / − φ hk 3/ ]} ξ (C-6) 3h C.5 Multilayered Stack under Electric Field Equation (C-6) can be applied to a multi-layered stack dielectric, 2m1* 2m * (φhk ,1 − ξ1 z )]dz} x exp{−2 ∫ sqrt[ 2 (φhk , − ξ1t1 − ξ z )]dz} x h h t2 n TWKB ≈ ∏ TWKB , j = exp{−2 ∫ sqrt[ j =1 t1 * n −1 K x exp{−2 sqrt[ 2m2 n (φhk ,n − ∑ ξ j t j − ξ n z )]dz} ∫ h j =1 tn (φhk ,1 − ξ1t1 ) / − φhk ,1 3/ = exp{ A[m1* + m3* ξ1 ( Φ − ξ 3t ) 3/ ξ3 − Φ3 + m2* 3/ + K + mn* (Φ − ξ t ) / − Φ 3/ ξ2 (Φ n − ξ n t n ) 3/ ξn − Φn 3/ ]} n −1 where Φ = φhk , − ξ1t1 , Φ = φhk ,3 − ξ1t1 − ξ 2t and Φ n = φhk ,n − ∑ ξ j t j j =1 3/ * (φhk ,1 − ξ SiO 2t SiO ) − φhk ,1 [m1 ξ SiO 2ε SiO / ε 3h 3/ TWKB = exp{ + m3* (Φ − ξ SiO 2t SiO ) / − Φ ξ SiO 2ε SiO / ε + m2* 3/ ]} + K + mn* (Φ − ξ SiO 2t SiO ) / − Φ ξ SiO 2ε SiO / ε (Φ n − ξ SiO 2t SiO ) / − Φ n ξ SiO 2ε SiO / ε n 3/ 3/ ]} (C-7) C-3 Appendix D Relevant Binding Energy for X-ray Photoelectron Spectroscopy Y (1s22s22p63s23p63d104s24p64d15s2)- Sensitivity Factor = 2.2 Si (1s22s22p63s23p2 )- Sensitivity Factor = 0.36 O (1s22s22p63s23p4 )- Sensitivity Factor = Y2O3 Spin-orbit splitting: Y3d5/2 : 156.8eV Y3d3/2 :158.8eV O1s: 529.5eV SiO2 O1s: 533.0 eV {532.9 (topsite) & 532.0 (Bridge and backbond site)} Si2p: 103.3 eV Si Si2p: 99.3 eV Y-O-S Y3d5/2 :158.3eV Y3d3/2 :160.83eV O1s: 532 eV Si2p: 102-103 eV YSi2 Y3d5/2: 155.8eV Y3d3/2 :157.83eV Si2p: 97.9eV Y-Y Y3d5/2: 155.7eV Y3d3/2 : 157.7eV D-1 Appendix E List of Publications Publications covered in this thesis 1. W.K. Chim, T.H. Ng, B.H. Koh, W.K. Choi, J.X. Zheng, C.H. Tung, and A.Y. Du, “Interfacial and bulk properties of zirconium dioxide as a gate dielectric in metal–insulator–semiconductor structures and current transport mechanisms”, Journal of Applied Physics, vol. 93, no. 8, pp. 4788-4793, April 15, 2003. 2. W.K. Chim, J.X. Zheng and B.H. Koh, “Modeling of charge quantization and wave function penetration effects in a metal-oxide-semiconductor system with ultra-thin gate oxide”, Journal of Applied Physics, vol. 94, no. 8, pp. 5273-5277, October 15, 2003. 3. B.H. Koh, W.K. Chim, T.H. Ng and W.K. Choi, “Quantum mechanical modeling of capacitance and gate current through tunnel dielectric stack structures for nonvolatile memory application”, Journal of Applied Physics, vol. 95, no. 9, pp. 5094-5103, May 1, 2004. 4. B.H. Koh, E.W.H. Kan, W.K. Chim, W.K. Choi, D.A. Antoniadis and E.A. Fitzgerald, “Traps in germanium nanocrystal memory and effect on charge retention – modeling and experimental measurements”, Journal of Applied Physics, vol. 97, pp.124305, June, 2005. 5. B.H. Koh, T.H. Ng, J.X. Zheng, W.K. Chim and W.K. Choi ,“Quantum mechanical modeling of capacitance and gate current for MIS structures using zirconium dioxide as the gate dielectric”, Proceedings of 2002 IEEE International Conference on Semiconductor Electronics, pp. 135-140, 19-21 Dec. 2002. Publications relevant to this thesis 1. T.H. Ng, B.H. Koh, W.K. Chim, W.K. Choi, J.X. Zheng, C.H. Tung and A.Y. Du, “Zirconium dioxide as a gate dielectric in metal-insulator-silicon structures and current transport mechanisms”, Proceedings of 2002 IEEE International Conference on Semiconductor Electronics, pp. 130-134, 19-21 Dec. 2002. 2. T.H. Ng, V. Ho, L.W. Teo, M.S. Tay, B.H. Koh, W.K. Chim, W.K. Choi, A.Y. Du and C.H. Tung, Fabrication and characterization of a trilayer germanium nanocrystal memory device with hafnium dioxide as the tunnel dielectric”, Proceedings of the 2nd International Conference on Materials for Advanced Technologies, at Suntec City Singapore Convention and Exhibition Centre, 7-12 December 2003. “ 3. T.H. Ng, V. Ho, L.W. Teo, M.S. Tay, B.H. Koh, W.K. Chim, W.K. Choi, A.Y. Du and C.H. Tung, “ Fabrication and characterization of a trilayer germanium nanocrystal memory device with hafnium dioxide as the tunnel dielectric”, Thin Solid Film, vol. 462-463, pp. 46-50, 2004. 4. E.W.H. Kan, B.H. Koh, W.K. Choi, W.K. Chim, D.A. Antoniadis and E.A. Fitzgerald, “Nanocrystalline Ge Flash memories: Electrical characterization and trap engineering” Singapore-MIT Alliance Symposium, 19-20 Jan 2005. E-1 [...]... List of Tables Table 4-1: Comparison of the |Vprog/Vret| ratio of MIS structures with Al gate and Si substrate using (a) crested tunnel barriers and (b) single-layered tunnel barriers of different materials for the insulator layer 137 Table 4-2: Physical thicknesses of the MIS structures with Al gate and Si substrate using (a) crested tunnel barriers and (b) single-layered tunnel barriers of. .. Figure 3-20: (a) Measured and QM simulated C-V curves of the Al/SiO2/HfO2/SiO2/n-Si MIS device (gate area = 1.26 x 10-2 cm2) Relative dielectric constant values of 3.9 and 7.117 have been used for the SiO2 (thickness of 1 nm and 2.3 nm from TEM) and bulk HfO2 (thickness of 2.9 nm from TEM) layers, respectively, in obtaining the simulated C-V curve, and (b) Conduction band profile of the Al/SiO2/HfO2/SiO2/n-Si... illustrations of (a) Fowler-Nordheim (F-N) and (b) direct tunneling in a nMOS structure Vox is the oxide voltage drop and ΦB is the conduction band offset at the Si/SiO2 interface In view of this potential limitation in scaling of the gate oxide thickness, researchers are interested in looking for solutions to overcome the problem and also investigating the limits of SiO2 For the modeling of quantized... single-layered tunnel barrier at flatband condition, (b) single-layered tunnel barrier during charging, (c) single-layered tunnel barrier during discharging, (d) duallayered tunnel barrier at flatband condition, (e) dual-layered tunnel barrier during charging, (f) dual-layered tunnel barrier during discharging, (g) crested tunnel barrier at flatband, (h) crested tunnel barrier during charging and (i) crested tunnel. .. through the use of high dielectric constant tunnel barriers and trap engineering By using a crested barrier structure as the tunnel barrier, a high electric field sensitivity can be achieved which would enable both fast charging and long charge retention Possible crested barrier structures have been proposed and the design of such structures is investigated through quantum mechanical modeling Based... it will take a strenuous engineering effort to meet the demands of Moore's Law for future developments of the FG structure The limitation for scaling stems from the extreme requirements place on the FG tunnel oxide layer During charging and discharging of the memory device, the tunnel oxide has to allow quick and efficient charge transfer to and from the FG The tunnel oxide should preferably be under... HfO2/Al2O3/HfO2 dielectric stack using EOT of 3 nm (square symbol), 4 nm (circle symbol) and 5 nm (triangle symbol) for the entire HfO2/Al2O3/HfO2 stack 136 Figure 4-8: Comparison of the simulated gate current density across single-layered Al2O3 and SiO2 tunnel barriers using EOT of 3 nm (square symbol) and 5 nm (triangle symbol) Current density of SiO2 and Al2O3 are represented by closed and opened symbols,... [7] and this has prompted many incumbent Flash manufacturers to explore alternative storage requirements The major problem lies in the thickness of the tunnel barrier According to the most authoritative industrial forecast, the International Technology Roadmap for Semiconductors (ITRS), tunnel oxide thickness of 6 to 7 nm (for NAND flash requirements) is required for technology nodes of 65 nm and beyond... Fowler-Nordheim (F-N) tunneling to direct tunneling as the SiO2 barrier layer thickness reduces In F-N tunneling, electrons tunnel through a barrier of triangular shape into the conduction band of the oxide layer under high oxide fields as shown in Figure 2-1(a), while in direct tunneling, electrons tunnel through a trapezoidal shaped barrier under low oxide fields Unlike F-N tunneling, the electron tunneling... .130 x Figure 4-3: Tunneling current characteristics versus applied electric field for single and crested barriers After Baik et al.[8] 131 Figure 4-4: Conduction band profiles of (a) Al/Y2O3/Al2O3/Y2O3/Si, (b) Al/Y2O3/SiO2/Y2O3/Si and (c) Al/HfO2/Al2O3/HfO2/Si crested barrier structures Band offsets and permittivities are taken from Ref [1] 133 Figure 4-5: Comparison of the simulated gate . tunnel barriers and (b) single-layered tunnel barriers of different materials for the insulator layer. 137 Table 4-3: Conduction band offset and relative permittivity of selected high- κ dielectric. MODELING AND CHARACTERIZATION OF HIGH DIELECTRIC CONSTANT TUNNEL BARRIERS FOR FUTURE NONVOLATILE MEMORY APPLICATIONS KOH BIH HIAN (B.Eng. retention performance of nanocrystal memory through the use of high dielectric constant tunnel barriers and trap engineering. By using a crested barrier structure as the tunnel barrier, a high electric