Modeling and characterization of on chip interconnects, inductors and transformers

MODELING AND CHARACTERIZATION OF ON-CHIP INTERCONNECTS, INDUCTORS AND TRANSFORMERS KAI KANG NATIONAL UNIVERSITY OF SINGAPORE AND ÉCOLE SUPÉRIEURE D’ÉLECTRICITÉ 2008 MODELING AND CHARACTERIZATION OF ON-CHIP INTERCONNECTS, INDUCTORS AND TRANSFORMERS KAI KANG (B. Eng., Northwestern Polytechnical University, P. R. China) A THESIS SUBMITTED FOR THE JOINT DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE AND ÉCOLE SUPÉRIEURE D’ÉLECTRICITÉ 2008 Acknowledgements This part of the thesis is probably the hardest to write. It is very difficult for me to find the words conveying the sincerity and magnitude of my gratitude to those who make this thesis possible through their significant supports and encouragements. First and foremost, I would like to thank Prof. Li Le-Wei, my principal thesis supervisor. I really appreciate that he offered me this great opportunity to study in his group at NUS. His kind decision definitely opens a new era of my life. I am grateful to him for creating this particularly stress-free environment which provides a large degree of freedom for me to enjoy my studies and research work. Throughout my time at NUS, I have been repeatedly surprised by the depth and breadth of his knowledge in all aspects of electrical engineering and his instincts for research and development for RF & microwave industries. He also always shares his valuable experiences and his intellectual maturity with me which are undoubtedly useful to my future career. I would also like to thank Prof. Saïd Zouhdi, who offered me the great opportunity to explore French culture and study for a year in Paris, the most beautiful city in the world. Without his support and advice, my studies at Supélec and LGEP could not be so fruitful. I would also like to thank Prof. Yin Wen-Yan at Shanghai Jiao-tong University, China. It was his vision and encouragement that first led me to investigate the modeling of on-chip passive components and consider the new ideas that eventually led to this thesis. He provides not only invaluable advice but also role model for me to explore the unknown scientific world with great interests and perseverance during my graduate studies and even my entire life. I am grateful to his patience and guidance throughout these years. Special thanks to Dr. Koen Mouthaan for his valuable discussion and funding support to the test structures fabrication. He has been -- II exceptionally helpful in my stay at NUS, during which his door has always been open for me. Prof. Yeo Tat-Soon has given me a lot of invaluable feedback on my research and has been very generous with his time on my qualify exam committee. I would also like to thank all of the helpful people I have encountered while working at Institute of Microelectronics. First, I would like to thank Dr. Shi Jinglin, who has given me invaluable advice and help on test structures designs and measurements. Furthermore, I would like to thank Dr. Subhash C. Rustagi, who gave me the chance to work on a project that would help direct my graduate studies. His experiences and advice regarding compact modeling and composing technical papers were very helpful to my research. I am also grateful to other staff at IME: Dr. James Brinkhoff, Dr. Lin Fujiang, Dr. Zheng Yuanjin, Dr. Xiong Yong-Zhong and Dr. Sun Sheng. I have been very lucky to work in a research group with many extraordinarily outstanding students. I am deeply grateful for the help, encouragement and collaboration of Qiu Cheng-Wei, Fei Ting, Yuan Tao, Zhang Lei, Feng Zhuo, Xu Wei, Nan Lan, Gao Yuan, Zhao Guang, Fan Yijin, Li Yanan, She Hao-Yuan and many others. I am also grateful to Dr. Yao Hai-Yin, Dr. Xin Hong, Dr. Zhang Min, Dr. Zhao Weijiang, Dr. Yuan Ning and Dr. Nie Xiaochun for their valuable help and friendship. Special thanks to Mr. Jack Ng for keeping the computer systems up and running. I would like to extend my appreciation to former members of Li group: Dr. Sun Jin, Mr. Pan Shu-Jun, Dr. Liu En-Xiao and many others. My friends at and outside NUS have provided important recreational and emotional support throughout the years: He Li, Dr. Chen Jianfeng, Shi Shaomei, Dr. Guo Rui, Dr. Wang Qiuhong, Li Ling, Wang Yadong, Zhang Tianxia, Dr. Ren Chi, Zhang Li, Darwin Chai, Liu Xiaofeng, Wu Man, Guo Minxuan, Yuan Yin, Dong Yang and many others. I will fondly remember all those -- III dinner gatherings, parties and trips during holidays. Last, but not certainly not least, I would like to thank all my family members for their love, support and constant encouragement in the long course of my study. I am very grateful to my parents in-law for treating me as their own son and for providing the much needed support. I would like to thank my mother and my father who have been there throughout my life and love me unconditionally despite all my failings. One really could not ask for more and I eternally indebted to them. And lastly, I offer my dearest thanks to my wife, Jing, to whom I owe this degree most to. Her constant love, support, kindness and funniness helped me to always keep my perspective and enjoy what I was doing. -- IV Table of Contents ACKNOWLEDGEMENTS II TABLE OF CONTENTS V SUMMARY VIII LIST OF TABLES IX LIST OF FIGURES X CHAPTER 1. INTRODUCTION 1.1 On-Chip Interconnects . 1.1.1 Background . 1.1.2 Motivation . 1.2 On-Chip Inductors and Transformers 1.2.1 Background . 1.2.2 Motivation . 1.3 Thesis Organization . 1.4 Original Contributions . 10 1.5 Publication List 14 CHAPTER 2. MODELING OF ON-CHIP SINGLE INTERCONNECT . 18 2.1 Introduction 18 2.2 A Wideband Scalable and SPICE-Compatible Model . 20 2.2.1 Skin Effect . 21 2.2.2 Proximity and Substrate Skin Effects 23 2.2.3 Substrate Skin Effect and Complex Image Method 26 2.2.4 Model Set-up . 33 2.3 Effect of Dummy Metal Fills . 35 2.4 Empirical Formulas for Elements in Series Branch . 36 2.5 Measurements and De-embedding . 38 2.6 Experimental Results and Model Validation 40 2.7 Summary 45 CHAPTER 3. CHARACTERIZATION OF ON-CHIP COUPLED (A)SYMMETRICAL INTERCONNECTS 46 V 3.1 Introduction 47 3.2 Coupled On-Chip Interconnects 48 3.3 Distributed Parameters and Propagation Constants . 51 3.3.1 Resistances and Inductances 52 3.3.2 Capacitances and Conductances 55 3.3.3 Propagation Constants . 63 3.3.4 Slow-wave Factors 68 3.4 Pulse Responses . 70 3.5 Average Power Handling Capabilities (APHC) . 75 3.6 Test Structure Fabrication and Measurements . 80 3.7 Experimental Results and Discussions 81 3.8 Summary 84 CHAPTER 4. MODELING AND DESIGN OF ON-CHIP INDUCTORS 86 4.1 Introduction 87 4.2 Greenhouse Method Incorporating with CIM Technique 89 4.3 Temperature-Dependent Substrate Conductivity . 93 4.4 Eleven-Element Equivalent Circuit Model of On-chip Inductors . 94 4.5 Results and Discussions . 95 4.5.1 4.5.1.1 4.5.1.2 4.5.2 4.6 Square Spiral Inductor . 95 Variations in the Substrate Conductivity………………………………98 Temperature Effects………………………………………………… 101 Differential Inductor .103 Design of A Vertical Tapered Solenoidal Inductor 105 4.6.1 Theory and Formulation .106 4.6.2 Layout .107 4.6.3 Measurement Results and Discussions .109 4.7 Summary . 111 CHAPTER 5. FREQUENCY-THERMAL CHARACTERIZATION OF ON-CHIP TRANSFORMERS WITH PATTERNED GROUND SHIELDS .113 5.1 Introduction . 114 5.2 Geometries of On-Chip PGS Transformers 116 5.3 Modified Temperature-Dependent Equivalent-Circuit Models 117 5.3.1 Equivalent Circuit Model for an Interleaved Transformer . 117 VI 5.3.2 Equivalent Circuit Model for a Center-tapped Interleaved Transformer 122 5.3.3 Temperature Effects 124 5.4 Fabrication and Measurements .132 5.5 Extraction of Performance Parameters and Discussion 133 5.5.1 Maximum Available Gain (Gmax) 133 5.5.2 Q Factor 137 5.5.3 Power Loss .139 5.6 Summary .140 CHAPTER 6. CONCLUSIONS 141 6.1 Summary .141 6.2 Future Work 144 BIBLIOGRAPHY . 145 VII Summary In today’s semiconductor industries, the mask cost increases dramatically, which makes the cost of a re-design more significant. On the other hand, on-chip passive components such as interconnects, inductors and transformers are widely used in high speed digital, mixed-signal and radio frequency integrated circuits (ICs). Therefore, accurate modeling of circuit behavior, especially for these passive components, is crucial for first-time-right designs. This research focus on modeling and characterization of on-chip interconnects, inductors and transformers. Firstly, a fully scalable and SPICE-compatible interconnects model is established and this model is accurate over a wideband frequency range from DC up to 110 GHz which has been verified by using measured S-parameters. In addition, this model also shows the capability to estimate the impact of metal dummy fills. Secondly, frequency- and temperature-dependent characteristics of on-chip coupled asymmetrical and symmetrical interconnects are investigated in detail, and a model for coupled interconnects is established and compared with experimental results. Furthermore, an eleven-element equivalent circuit model is established for simulating on-chip spiral inductors. The substrate skin effect is correctly characterized by this model. Additionally, a vertical tapered solenoidal inductor is designed to achieve a high resonance frequency. Finally, extensive studies on the performances of on-chip transformers with and without patterned ground shields at different temperatures are carried out. These transformers are fabricated using 0.18-μm RF CMOS processes and are designed to have either interleaved or center-tapped interleave geometries, respectively. VIII List of Tables Table 2.1 The Coefficients of Empirical Formulas for the Elements in Series Branch of the Proposed Model .37 Table 2.2 The Values of Lumped Elements of the Proposed Model for Interconnects with Different Widths and Lengths by Using (2.51) and (2.53)-(2.56) 43 Table 3.1 Coefficients of Aluminum, Gold, and Copper 50 Table 3.2 Effects of Variation in Different Parameters on the Pav (VE: Very Effective; EL: Effective, but Limited) .79 Table 5.1 Coefficients for Different Metals over a Temperature Range of 200 to 900 K 125 Table 5.2 Silicon Resistivity Values at Different Temperatures .129 Table 5.3 Extracted Circuit Parameters of (non)PGS Transformer of Desgin with N = 129 Table 5.4 Extracted Equivalent Circuit Parameters of Transformer of Design with N = .129 IX Chapter Conclusion RFIC designs. 6.2 Future Work As transistors continue to scale to higher operating frequencies, the importance of interconnects will also continue to escalate. Future active areas of research include i) accurate layout parameter extraction tools, ii) hierarchy methodologies and models for full-chip interconnects simulations, and iii) novel test structures to mimic real high speed digital and mixed-signal ICs and to characterize the long range mutual inductive coupling and substrate noise coupling. Over the past decades, on-chip inductors and transformers have established themselves as the standard components in mixed-signal and RFICs. They will continue to determine the overall quality of circuits in the future. Promising areas of research include i) inductors/transformers with novel structures fabricated by CMOS processes to achieve a high quality factor as well as a high self-resonance frequency, ii) wideband, scalable and SPICE-compatible models for on-chip inductors and transformers, iii) fixed models by using fast and accurate extraction approaches to directly obtain models from experiment results, and iv) new test structures and de-embedding technique, such as a four-port transformer test structure and its corresponding de-embedding method. 144 Bibliography [1] International Technology Roadmap for Semiconductor (ITRS). 2005. [2] http://www.intel.com/technology/mooreslaw/index.htm. Intel website, 2007. [3] J. D. Meindl, J. A. Davis, P. Zarkesh-Ha, C. S. Patel, K. P. Martin, and P. A. Kohl, "Interconnect opportunities for gigascale integration," IBM J. Res. & Dev., vol. 46, pp. 245-263, March/May, 2002. [4] J. A. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. J. Souri, K. Banerjee, K. C. Saraswat, A. Rahman, R. Reif, and J. D. Meindl, "Interconnect limits on gigascale integration (GSI) in the 21st century," Proceedings of the IEEE, vol. 89, pp. 305-324, 2001. [5] W. R. Eisenstadt and Y. Eo, "S-parameter-based IC interconnect transmission line characterization," IEEE Trans. Components, Hybrids, and Manufacturing Tech., vol. 15, pp. 483-490, 1992. [6] J. A. Davis and J. D. Meindl, "Compact distributed RLC interconnect models. I. Single line transient, time delay, and overshoot expressions," IEEE Trans. Electron Devices, vol. 47, pp. 2068-2077, 2000. [7] J. A. Davis and J. D. Meindl, "Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel networks," IEEE Trans. Electron Devices, vol. 47, pp. 2078-2087, 2000. [8] B. Krauter and S. Mehrotra, "Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis," in Proc. Design Automation Conf., pp. 303-308, 1998. [9] A. Weisshaar, H. Lan, and A. Luoh, "Accurate closed-form expressions for the frequency-dependent line parameters of on-chip interconnects on lossy silicon substrate," IEEE Trans. Adv. Packag., vol. 25, pp. 288-296, 2002. [10] A. M. Niknejad and R. G. Meyer, "Analysis of eddy-current losses over conductive substrates with applications to monolithic inductors and transformers," IEEE Trans. Microwave Theory Tech., vol. 49, pp. 166-176, 2001. [11] A. E. Ruehli, "Equivalent Circuit Models for Three-Dimensional Multiconductor Systems," IEEE Trans. Microwave Theory Tech., vol. 22, pp. 216-221, 1974. [12] R. F. Harrington, Field computation by moment methods. Piscataway, NJ, IEEE Press, 1993. [13] J. Jin, The Finite Element Method in Electromagnetics. 2nd ed., New York, John Wiley & Sons, 2002. [14] J. L. Volakis, A. Chatterjee, and L. C. Kempel, Finite element method for electromagnetics: with applications to antennas, microwave circuits, and scattering. New York, IEEE Press, 1998. [15] K. S. Yee, "Numerical solution of initial boundary value problems involving Maxwell's equations in isotropic media," IEEE Trans. Antennas Propagat., vol. 14, pp. 302-307, 1966. [16] A. Taflove and S. C. Hagness, Computational Electrodynamics: The Finite-Difference Time-Domain Method. 2nd ed., Boston, Artech House, 2000. [17] X. Huang, P. Restle, T. Bucelot, Y. Cao, T.-J. King, and C. Hu, "Loop-based interconnect modeling and optimization approach for multigigahertz clock network design," IEEE J. Solid-State Circuits, vol. 38, pp. 457-463, 2003. 146 [18] S. Yu, D. M. Petranovic, S. Krishnan, K. Lee, and C. Y. Yang, "Loop-based inductance extraction and modeling for multiconductor on-chip interconnects," IEEE Trans. Electron Devices, vol. 53, pp. 135-145, 2006. [19] J. R. Wait and K. P. Spies, "On the image representation of the quasistatic fields of a line current source above the ground," Canadian J. Physics., vol. 47, pp. 2731, 1969. [20] P. B. Bannister, "Applications of complex image theory," Radio Sci., vol. 21, pp. 605-616, Jul. 1986. [21] R. Jiang, W. Fu, and C. C.-P. Chen, "EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, pp. 1562-1571, Oct. 2005. [22] [23] http://www.3gamericas.org/English/Statistics/. J. N. Burghartz and B. Rejaei, "On the design of RF spiral inductors on silicon," IEEE Trans. Electron Devices, vol. 50, pp. 718-729, 2003. [24] C. P. Yue and S. S. Wong, "On-chip spiral inductors with patterned ground shields for Si-based RF ICs," IEEE J. Solid-State Circuits, vol. 33, pp. 743-752, 1998. [25] B. Razavi, "A 60-GHz CMOS receiver front-end," IEEE J. Solid-State Circuits, vol. 41, pp. 17-22, 2006. [26] C. H. Doan, S. Emami, A. M. Niknejad, and R. W. Brodersen, "Millimeter-wave CMOS design," IEEE J. Solid-State Circuits, vol. 40, pp. 144-155, 2005. [27] A. Natarajan, A. Komijani, X. Guan, A. Babakhani, and A. Hajimiri, "A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Transmitter and Local LO-Path Phase Shifting," IEEE J. Solid-State Circuits, vol. 41, pp. 2807-2819, 2006. 147 [28] A. Deutsch, G. V. Kopcsay, P. J. Restle, H. H. Smith, G. Katopis, W. D. Becker, P. W. Coteus, C. W. Surovic, B. J. Rubin, R. P. Dunne, Jr., T. Gallo, K. A. Jenkins, L. M. Terman, R. H. Dennard, G. A. Sai-Halasz, B. L. Krauter, and D. R. Knebel, "When are transmission-line effects important for on-chip interconnections?" IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1836-1846, 1997. [29] S. Kim and D. P. Neikirk, "Compact equivalent circuit model for the skin effect," in IEEE MTT-S International Microwave Symposium, San Francisco, pp. 1815-1818, 1996. [30] S.-P. Sim, C. Chao, S. Krishnan, D. M. Petranovic, N. D. Arora, K. Lee, and C. Y. Yang, "An effective loop inductance model for general non-orthogonal interconnect with random capacitive coupling," in IEDM Tech. Digest, pp. 315-318, 2002. [31] L. F. Tiemeijer, R. J. Havens, Y. Bouttement, and H. J. Pranger, "Physics-based wideband predictive compact model for inductors with high amounts of dummy metal fill," IEEE Trans. Microwave Theory Tech., vol. 54, pp. 3378-3386, 2006. [32] C. A. Chang, S.-P. Tseng, J. Y. Chuang, S.-S. Jiang, and J. A. Yeh, "Characterization of spiral inductors with patterned floating structures," IEEE Trans. Microwave Theory Tech., vol. 52, pp. 1375-1381, 2004. [33] [34] Q3D Extractor User's Guide. Ansoft Corporation, Pittsburg, PA, USA. N. A. Talwalkar, C. P. Yue, and S. S. Wong, "Analysis and synthesis of on-chip spiral inductors," IEEE Trans. Electron Devices, vol. 52, pp. 176-182, 2005. [35] F. W. Grove, Inductance Calculations. New York, Van Nostrand, 1946. [36] A. E. Ruehli, "Inductance calculations in a complex integrated circuit environment," IBM J. Res. Develop., vol. 16, pp. 470-481, Sep. 1972. 148 [37] M. Beattie, B. Krauter, L. Alatan, and L. Pileggi, "Equipotential shells for efficient inductance extraction," IEEE Trans. Computer-Aided Design, vol. 20, pp. 70-79, 2001. [38] A. Devgan, H. Ji, and W. Dai, "How to efficiently capture on-chip inductance effects: introducing a new circuit element K," in Proc. IEEE/ACM Int. Conf. Computer Aided Design, pp. 150-155, 2000. [39] B. Young, Digital Signal Integrity: Modeling and simulation with Interconnects and Packages. Englewood Cliffs, NJ, Prentice-Hall, 2001. [40] J. A. Tegopoulos and E. E. Kriezis, Eddy Currents in Linear Conducting Media. Amsterdam, The Netherlands, Elsevier, 1985. [41] R. L. Stoll, The Analysis of Eddy Currents. Oxford, U. K, Clarendon, 1974. [42] J. D. Stratton, Electromagnetics Theory. McGraw-Hill, 1941. [43] S. Sun, R. Kumar, S. C. Rustagi, K. Mouthaan, and T. K. S. Wong, "Wideband lumped element model for on-chip interconnects on lossy silicon substrate," in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. [44] F. Stellari and A. L. Lacaita, "New formulas of interconnect capacitances based on results of conformal mapping method," IEEE Trans. Electron Devices, vol. 47, pp. 222-231, 2000. [45] Y. Eo and W. R. Eisenstadt, "High-speed VLSI interconnect modeling based on S-parameter measurements," IEEE Trans. Components, Hybrids, and Manufacturing Tech., vol. 16, pp. 555-562, 1993. [46] R. F. Scholz, F. Korndorfer, B. Senapati, and A. Rumiantsev, "Advanced technique for broadband on-wafer RF device characterization," in 63rd ARFTG Conference Digest 149 Spring, pp. 83-90, 2004. [47] J. Song, F. Ling, G. Flynn, W. Blood, and E. Demircan, "A de-embedding technique for interconnects," in Electrical Performance of Electronic Packaging, pp. 129-132, 2001. [48] M. J. Kobrinsky, S. Chakravarty, D. Jiao, M. C. Harmes, S. List, and M. Mazumder, "Experimental validation of crosstalk simulations for on-chip interconnects using S-parameters," IEEE Trans. Adv. Packag., vol. 28, pp. 57-62, 2005. [49] L. Nan, K. Mouthaan, Y. Z. Xiong, J. Shi, S. C. Rustagi, and B.-L. Ooi, "Experimental characterization of the effect of metal dummies on spiral inductors," in IEEE Radio Frequency Integrated Circuits (RFIC), Honolulu, 3-8 June 2007 [50] H. Hasegawa, M. Furukawa, and H. Yanai, "Properties of Microstrip Line on Si-SiO/sub 2/ System," IEEE Trans. Microwave Theory Tech., vol. 19, pp. 869-881, 1971. [51] K. W. Goossen and R. B. Hammond, "Modeling of picosecond pulse propagation in microstrip interconnections of integrated circuits," IEEE Trans. Microwave Theory Tech., vol. 37, pp. 469-478, 1989. [52] S. Zaage and E. Groteluschen, "Characterization of the broadband transmission behavior of interconnections on silicon substrates," IEEE Trans. Components, Hybrids, and Manufacturing Tech., vol. 16, pp. 686-691, 1993. [53] D. F. Williams, "Metal-insulator-semiconductor transmission lines," IEEE Trans. Microwave Theory Tech., vol. 47, pp. 176-181, 1999. [54] W. Ryu, S.-H. Baik, H. Kim, J. Kim, M. Sung, and J. Kim, "Embedded microstrip interconnection lines for gigahertz digital circuits," IEEE Trans. Adv. Packag., vol. 23, 150 pp. 495-503, 2000. [55] Z.-F. Jin, J.-J. Laurin, and Y. Savaria, "A practical approach to model long MIS interconnects in VLSI circuits," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 10, pp. 494-507, 2002. [56] D. D. Roest, H. Ymeri, S. Vandenberghe, M. Stucchi, D. Schueurs, K. Maex, and B. Nauwelaers, "Some measurement results for frequency-dependent inductance of IC interconnects on a lossy silicon substrate," IEEE Electron Device Lett., vol. 23, pp. 103-104, 2002. [57] B. Kleveland, X. Qi, L. Madden, T. Furusawa, R. W. Dutton, M. A. Horowitz, and S. S. Wong, "High-frequency characterization of on-chip digital interconnects," IEEE J. Solid-State Circuits, vol. 37, pp. 716-725, 2002. [58] J. P. K. Gilb and C. A. Balanis, "MIS slow-wave structures over a wide range of parameters," IEEE Trans. Microwave Theory Tech., vol. 40, pp. 2148-2154, 1992. [59] V. K. Tripathi and N. Orhanovic, "Time-domain characterization and analysis of dispersive dissipative interconnects," IEEE Trans. Circuits Syst. I, vol. 39, pp. 938-945, 1992. [60] S. Voranantakul, J. L. Prince, and P. Hsu, "Crosstalk analysis for high-speed pulse propagation in lossy electrical interconnections," IEEE Trans. Components, Hybrids, and Manufacturing Tech., vol. 16, pp. 127-136, 1993. [61] M. Sung, W. Ryu, H. Kim, J. Kim, and J. Kim, "An efficient crosstalk parameter extraction method for high-speed interconnection lines," IEEE Trans. Adv. Packag., vol. 23, pp. 148-155, 2000. [62] J. Zheng, Y.-C. Hahm, V. K. Tripathi, and A. Weisshaar, "CAD-oriented 151 equivalent-circuit modeling of on-chip interconnects on lossy silicon substrate," IEEE Trans. Microwave Theory Tech., vol. 48, pp. 1443-1451, 2000. [63] A. Weisshaar and A. Luoh, "Closed-form expressions for the series impedance parameters of on-chip interconnects on multilayer silicon substrates," IEEE Trans. Adv. Packag., vol. 27, pp. 126-134, 2004. [64] C. N. Chiu, "Closed-form expressions for the line-coupling parameters of coupled on-chip interconnects on lossy silicon substrate," Micro. Opt. Tech. Lett., vol. 43, pp. 495-498, 2004. [65] T.-Y. Chiang, B. Shieh, and K. C. Saraswat, "Impact of Joule heating on scaling of deep sub-micron Cu/low-k interconnects," in VLSI Technology Symposium, pp. 38-39, 2002. [66] T.-Y. Chiang, K. Banerjee, and K. C. Saraswat, "Analytical thermal model for multilevel VLSI interconnects incorporating via effect," IEEE Electron Device Lett., vol. 23, pp. 31-33, 2002. [67] K. Banerjee and A. Mehrotra, "Global (interconnect) warming," IEEE Circuits and Devices Magazine, vol. 17, pp. 16-32, 2001. [68] L. Xue, C. C. Liu, H.-S. Kim, S. K. Kim, and S. Tiwari, "Three-dimensional integration: technology, use, and issues for mixed-signal applications," IEEE Trans. Electron Devices, vol. 50, pp. 601-609, 2003. [69] M. Golio, The RF and Microwave Handbook. vol. A-8, CRC Press, 2001. [70] N. Arora, MOSFET models for VLSI circuit simulation theory and practice. New York, Springer-Verlag, 1993. [71] V. K. Tripathi, "Asymmetric Coupled Transmission Lines in an Inhomogeneous 152 Medium," IEEE Trans. Microwave Theory Tech., vol. 23, pp. 734-739, 1975. [72] V. K. Tripathi, "Equivalent Circuits and Characteristics of Inhomogeneous Nonsymmetrical Coupled-Iine Two-Port Circuits," IEEE Trans. Microwave Theory Tech., vol. 25, pp. 140-142, 1977. [73] G. Wang, X. Qi, and Z. Yu, "Device level modeling of metal-insulator-semiconductor interconnects," IEEE Trans. Electron Devices, vol. 48, pp. 1672-1682, 2001. [74] Y. J. Yoon and B. Kim, "A new formula for effective dielectric constant in multi-dielectric layer microstrip structure," in IEEE Electrical Performance of Electronic Packaging Conf., pp. 163-167, 2000. [75] H. T. Vo, C. Davidson, and F. G. Shi, "New effective dielectric constant model for ultra-high speed microstrip lines on multilayer dielectric substrates: effect of conductor-dielectric interphase," in Proc. Electronic Components and Technology Conf., pp. 86-89, 2002. [76] M. Kirschning and R. H. Jansen, "Accurate Wide-Range Design Equations for the Frequency-Dependent Characteristic of Parallel Coupled Microstrip Lines," IEEE Trans. Microwave Theory Tech., vol. 32, pp. 83-90, 1984. [77] K. C. Gupta, R.Grag, I. J. Bahl, and P. Bhartia, Microstrip lines and slotlines. Artech House, 1996. [78] P. Pramanick and R. R. Mansour, "Dispersion characteristics of square pulse with finite rise time in single, tapered, and coupled microstrip lines," IEEE Trans. Microwave Theory Tech., vol. 39, pp. 2117-2122, 1991. [79] I. J. Bahl, "Average power handling capability of multiplayer microstrip lines," Int. J. RF and Microwave CAE, vol. 11, pp. 385-395, 2001. 153 [80] W.-Y. Yin and X. T. Dong, "Wide-band characterization of average power handling capabilities of some microstrip interconnects on polyimide and polyimide/GaAs substrates," IEEE Trans. Adv. Packag., vol. 28, pp. 328-336, 2005. [81] W. Y. Yin and X. T. Dong, "Wideband average power handling capability of coupled microstrips on polyimide and polyimide/GaAs substrates," IEE Proceedings Microwaves, Antennas and Propagation, vol. 151, pp. 385-392, 2004. [82] N. M. Nguyen and R. G. Meyer, "Si IC-compatible inductors and LC passive filters," IEEE J. Solid-State Circuits, vol. 25, pp. 1028-1031, 1990. [83] W. Y. Yin, S. J. Pan, L. W. Li, Y. B. Gan, and F. Lin, "Local scalable description of global characteristics of various on-chip asymmetrically octagonal inductors," IEEE Trans. Magnetics, vol. 39, pp. 2042-2048, Jul. 2003. [84] J. R. Long and M. A. Copeland, "The modeling, characterization, and design of monolithic inductors for silicon RF IC's," IEEE J. Solid-State Circuits, vol. 32, pp. 357-369, 1997. [85] C. P. Yue and S. S. Wong, "Physical modeling of spiral inductors on silicon," IEEE Trans. Electron Devices, vol. 47, pp. 560-568, 2000. [86] A. M. Niknejad and R. G. Meyer, "Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs," IEEE J. Solid-State Circuits, vol. 33, pp. 1470-1481, 1998. [87] Y. Cao, R. A. Groves, X. Huang, N. D. Zamdmer, J.-O. Plouchart, R. A. Wachnik, T.-J. King, and C. Hu, "Frequency-independent equivalent-circuit model for on-chip spiral inductors," IEEE J. Solid-State Circuits, vol. 38, pp. 419-426, 2003. [88] F. Rotella, B. K. Bhattacharya, V. Blaschke, M. Matloubian, A. Brotman, Y. Cheng, R. 154 Divecha, D. Howard, K. Lampaert, P. Miliozzi, M. Racanelli, P. Singh, and P. J. Zampardi, "A broad-band lumped element analytic model incorporating skin effect and substrate loss for inductors and inductor like components for silicon technology performance assessment and RFIC design," IEEE Trans. Electron Devices, vol. 52, pp. 1429-1441, 2005. [89] W. Gao and Z. Yu, "Scalable compact circuit model and synthesis for RF CMOS spiral inductors," IEEE Trans. Microwave Theory Tech., vol. 54, pp. 1055-1064, 2006. [90] K.-Y. Lee, S. Mohammadi, P. K. Bhattacharya, and L. P. B. Katehi, "A Wideband Compact Model for Integrated Inductors," IEEE Microwave Wireless Components Lett., vol. 16, pp. 490-492, 2006. [91] X. Huo, P. C. H. Chan, K. J. Chen, and H. C. Luong, "A physical model for on-chip spiral inductors with accurate substrate modeling," IEEE Trans. Electron Devices, vol. 53, pp. 2942-2949, 2006. [92] D. Melendy and A. Weisshaar, "A new scalable model for spiral inductors on lossy silicon substrate," in IEEE MTT-S International Microwave Symposium Digest, pp. 1007-1010, 2003. [93] W. A. Roshen, "Effect of finite thickness of magnetic substrate on planar inductors," IEEE Trans. Magn., vol. 26, pp. 270-275, 1990. [94] H. Greenhouse, "Design of planar rectangular microelectronic inductors," IEEE Trans. Parts, Hybrids, and Packaging, vol. 10, pp. 101-109, 1974. [95] D. M. Caughey and R. E. Thomas, "Carrier mobilities in silicon empirically related to doping and field," Proceedings of the IEEE, vol. 55, pp. 2192-2193, 1967. 155 [96] M. S. Tyagi, Introduction to Semiconductor Materials and Devices. New York, Wiley, 1991. [97] R. B. Adler, A. C. Smith, and R. L. Longini, Introduction to Semiconductor Physics. vol. 1, New York, John Wiley, 1964. [98] D. M. Pozar, Microwave Engineering. ed., New York, Wiley, 1998. [99] M. Danesh and J. R. Long, "Differentially driven symmetric microstrip inductors," IEEE Trans. Microwave Theory Tech., vol. 50, pp. 332-341, 2002. [100] P. Findley, G. Ali Rezvani, and J. Tao, "Novel differential inductor design for high self-resonance frequency," in IEEE IEDM Digest, Dec., pp. 467-470, 2004. [101] T. Ohguro, T. Ishikawa, S. Samata, A. Kawasaki, T. Nagano, T. Yoshitomi, and T. Toyoshima, "High performance digital-analog mixed device on a Si substrate with resistivity beyond 1k?cm," in IEDM Tech. Dig., pp. 757-760, 2000. [102] J. Zeng, A. J. Pang, C. H. Wang, and A. J. Sangster, "Flip chip assembled MEMS inductors," Electron. Lett., vol. 41, pp. 480-481, 2005. [103] J. N. Burghartz, M. Soyuer, and K. A. Jenkins, "Integrated RF and microwave components in BiCMOS technology," IEEE Trans. Electron Devices, vol. 43, pp. 1559-1570, 1996. [104] T. S. D. Cheung and J. R. Long, "Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits," IEEE J. Solid-State Circuits, vol. 41, pp. 1183-1200, 2006. [105] M. Kamon, M. J. Ttsuk, and J. K. White, "FASTHENRY: a multipole-accelerated 3-D inductance extraction program," IEEE Trans. Microwave Theory Tech., vol. 42, pp. 1750-1758, 1994. 156 [106] D. E. Meharry, J. E. Sanctuary, and B. A. Golja, "Broad bandwidth transformer coupled differential amplifiers for high dynamic range," IEEE J. Solid-State Circuits, vol. 34, pp. 1233-1238, 1999. [107] W. Simburger, H.-D. Wohlmuth, P. Weger, and A. Heinz, "A monolithic transformer coupled 5-W silicon power amplifier with 59% PAE at 0.9 GHz," IEEE J. Solid-State Circuits, vol. 34, pp. 1881-1892, 1999. [108] I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, "Distributed active transformer A new power-combining and impedance-transformation technique," IEEE Trans. Microwave Theory Tech., vol. 50, pp. 1881-1892, Dec. 2002. [109] A. Coustou, D. Dubuc, J. Graffeuil, O. Llopis, E. Tournier, and R. Plana, "Low phase noise IP VCO for multistandard communication using a 0.35um BiCMOS SiGe technology," IEEE Microwave Wireless Components Lett., vol. 15, pp. 71-73, 2005. [110] J. R. Long, "Monolithic transformers for silicon RF IC design," IEEE J. Solid-State Circuits, vol. 35, pp. 1368-1382, 2000. [111] Y. K. Koutsoyannopoulos and Y. Papananos, "Systematic analysis and modeling of integrated inductors and transformers in RF IC design," IEEE Trans. Circuits Syst. II, vol. 47, pp. 699-713, 2000. [112] K. T. Ng, B. Rejaei, and J. N. Burghartz, "Substrate effects in monolithic RF transformers on silicon," IEEE Trans. Microwave Theory Tech., vol. 50, pp. 377-383, 2002. [113] J. Hongrui, Z. Li, and N. C. Tien, "Reducing silicon-substrate parasitics of on-chip transformers on silicon," in IEEE Microelectromech. Syst. Conf., pp. 649-652, 2002. [114] T. Biondi, A. Scuderi, E. Ragonese, and G. Palmisano, "Wideband lumped scalable 157 modeling of monolithic stacked transformers on silicon," in Proc. Bipolar/BiCMOS Circuits and Technology, pp. 265-268, 2004. [115] S. J. Pan, W. Y. Yin, and L. W. Li, "Comparative investigation on various on-chip center-tapped interleaved transformers," Int. Journal of RF and Microwave CAE, vol. 14, pp. 424-432, 2004. [116] S. Kim, K. Lee, J. Lee, B. Kim, S. D. Kee, I. Aoki, and D. B. Rutledge, "An optimized design of distributed active transformer," IEEE Trans. Microwave Theory Tech., vol. 53, pp. 380-388, 2005. [117] T. O. Dickson, M.-A. LaCroix, S. Boret, D. Gloria, R. Beerkens, and S. P. Voinigescu, "30-100-GHz inductors and transformers for millimeter-wave Bi-CMOS integrated circuits," IEEE Trans. Microwave Theory Tech., vol. 53, pp. 123-133, 2005. [118] Y. Mayevskiy, A. Watson, P. Francis, K. Hwang, and A. Weisshaar, "A new compact model for monolithic transformers in silicon-based RFICs," IEEE Microwave Wireless Components Lett., vol. 15, pp. 419-421, 2005. [119] C.-P. Chien, A. F. Burnett, J. M. Cech, and M. H. Tanielian, "The signal transmission characteristics of embedded microstrip transmission lines over a meshed ground plane in copper/polyimide multichip module," IEEE Trans. Comp., Packag., Manufact. Technol., vol. 17, pp. 578-583, 1994. [120] R. Lowther and S.-G. Lee, "On-chip interconnect lines with patterned ground shields," IEEE Microwave Guided Wave Lett., vol. 10, pp. 49-51, 2000. [121] R. D. Luth, V. K. Tripathi, and A. Weisshaar, "Enhanced transmission characteristics of on-chip interconnects with orthogonal grided shield," IEEE Trans. Adv. Packag., vol. 34, pp. 288-293, Nov. 2001. 158 [122] P. Wang and E. C.-C. Kan, "High-speed interconnects with underlayer orthogonal metal grids," IEEE Trans. Adv. Packag., vol. 27, pp. 497-507, 2004. [123] S.-M. Yim, T. Chen, and K. K. O, "The effects of a ground shield on the characteristics and performance of spiral inductors," IEEE J. Solid-State Circuits, vol. 37, pp. 237-244, 2002. [124] Y.-S. Lin, H.-B. Liang, T. Wang, and S.-S. Lu, "Temperature-dependence of noise figure of monolithic RF transformers on a thin 20um silicon substrate," IEEE Electron Device Lett., vol. 26, pp. 208-211, 2005. [125] Y. Z. Xiong, T. H. Teo, and J. S. Fu, "Direct extraction of equivalent circuit parameters for balun on silicon substrate," IEEE Trans. Electron Devices, vol. 52, pp. 1915-1916, 2005. [126] C. Corvasce, M. Ciappa, D. Barlini, F. Illien, and W. Fichtner, "Measurement of the silicon resistivity at very high temperature with junction isolated van der Pauw structures," in Proc. Instrumentation and Measurement Technology Conf., Como, Italy, vol.1, pp. 133-138, 2004. [127] Agilent EEsof EDA, Palo Alto, CA 94304, U.S.A, 2004 159 [...]... Kang, K Mouthaan and T.K.S Wong, Characterization and Modeling of CMOS on- chip coupled interconnects”, ESSDERC, Munich, Sep.11-13, 2007 17 Chapter 2 Modeling of On- Chip Single Interconnect Chapter 2 Modeling of On- Chip Single Interconnect A fully scalable and SPICE compatible wideband model of on- chip interconnects valid up to 110 GHz is presented in this chapter The series branches of the proposed... determination of wideband series impedances and shunt conductances, conductive and dielectric attenuation constants of even (c) and odd (π) modes, pulse waveform distortion and crosstalk, and average power handling capability (APHC) Compared with previous studies of coupled symmetrical interconnects, the present work has focused on (i) 11 Chapter 1 Introduction asymmetrical coupled configurations; (ii)... characteristics of on- chip coupled asymmetrical and symmetrical interconnects based on several extended formulas to determine all frequency- and temperature-dependent distributed parameters These characteristics include wideband series impedances and shunt conductances, conductive and dielectric attenuation constants of even (c) and odd (π)- modes, pulse waveform distortion and crosstalk, and average power handling... processes Deep submicron transistors, due to the constantly shrinking feature size of CMOS technologies as mentioned in the previous section, allow the integration of the analog and digital blocks to form mixed-signal ICs for “system -on- chip solutions Fully integrated chip solutions are desired to eliminate off -chip components and to reduce cost The number of board-level passive components and ICs drops with... integration, which reduces the overall costs of assembly and parts Decrease in the number of passive components on board 7 Chapter 1 Introduction leads to smaller board sizes and usually lower power consumption, since there is no need to drive off -chip low impedance components Furthermore, on- chip passive components have the advantage of well controlled interconnecting parasitics over process variation,... reliability and the controllability of the end products Therefore, on- chip passive components, such as resistors, capacitors, inductors and transformers, are widely used in RFICs On- chip inductors and transformers are widely applied for impedance matching, RF filters, voltage controlled oscillators (VCO), power amplifiers (PA) and low noise amplifiers (LNA) In the past, on- chip passive components were... designs In this thesis, modeling and simulation efforts are devoted to exploring the characteristics of on- chip interconnects, inductors and transformers 1.1 On- Chip Interconnects 1.1.1 Background In the past four decades, the semiconductor industry has advanced at an incredible rate in both productivity and performance The size of transistors and the switching delay have been continuously reduced Transistor... system of inductors On- chip transformers have been widely used in designs for on- chip impedance matching, baluns, and low-noise amplifier feedback In addition to the losses caused by similar mechanisms as inductors, on- chip transformers also suffer from losses due to lateral conduction currents flowing in the substrate between the primary and secondary coils Such losses, together with those from shunt conduction... electromagnetic and thermal characteristics; and (iii) all geometric and physical parameters of the configuration, particularly metal line thickness, line conductivity, silicon conductivity and thermal conductivity Based on the numerical examples, effective ways to suppress silicon substrate loss and coupling effects, reduce crosstalk between two interconnects, and enhance their power handling capability... conductive silicon As a result, on- chip inductors typically exhibit the lowest Q-factor of the RF passives In addition, the high operating frequencies, at which deep sub-micron and nano-scale CMOS devices are able to operate, have made RFICs prone to the quality of the passive components [23] Therefore, accurate models of on- chip inductors are highly desired for first-time-right designs A conventional . MODELING AND CHARACTERIZATION OF ON- CHIP INTERCONNECTS, INDUCTORS AND TRANSFORMERS KAI KANG NATIONAL UNIVERSITY OF SINGAPORE AND ÉCOLE SUPÉRIEURE. accurate modeling of circuit behavior, especially for these passive components, is crucial for first-time-right designs. This research focus on modeling and characterization of on- chip interconnects,. INTRODUCTION 1 1.1 On- Chip Interconnects 1 1.1.1 Background 1 1.1.2 Motivation 3 1.2 On- Chip Inductors and Transformers 6 1.2.1 Background 6 1.2.2 Motivation 8 1.3 Thesis Organization 9 1.4