A low power low voltage biomedical signal acquisition chip

A LOW POWER LOW VOLTAGE BIOMEDICAL SIGNAL ACQUISITION CHIP YONG CHEE HONG NATIONAL UNIVERSITY OF SINGAPORE 2008 A LOW POWER LOW VOLTAGE BIOMEDICAL SIGNAL ACQUISITION CHIP YONG CHEE HONG (B Eng (Hons.), Nanyang Technological University, Singapore) A THESIS SUBMITTED FOR THE DEGREE OF MASTER OF ENGINEERING DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2008 Acknowledgement I am grateful to my supervisors Assoc Prof Xu Yong Ping, National University of Singapore for providing me with the valuable opportunity of conducting research under his supervision I sincerely thank him for his guidance, support and help throughout the course I would like to thank Mr Teo Seow Miang and Ms Zheng Huan Qun, Signal Processing and VLSI design laboratory, National University of Singapore, for helping me with setting up environment to carry out simulations and testing Special thanks to the Mediatek Singapore Pte Ltd for supporting me with a graduate research scholarship I thank my friends in the Signal Processing and VLSI design laboratory, National University of Singapore, especially Mr HeLin, Mr Chen Jian Zhong and Mr Yang Zhenglin, whose association making these two years an enjoyable research experience Finally, I thank my parents and my wife for their constant encouragement, understanding and blessings towards my endeavor i Table of Contents Acknowledgement i Table of Contents ii Summary v List of Figures vii List of Tables x List of Abbreviations and Symbols xi CHAPTER Introduction 1.1 Overview 1.2 Motivation 1.3 Scope of this work 1.4 Organization of thesis CHAPTER 2.1 Review of Previous Work Low Noise Low Power Amplifiers 2.1.1 Noise Sources in CMOS Amplifiers 2.1.2 Low Noise Low Power Amplifier Design 2.2 Low Power ADCs 12 2.2.1 ADC Architectures 13 2.2.2 Low Power ADC Design 16 2.3 Summary 20 CHAPTER 3.1 Acquisition Chip Design 21 Overall Chip Architecture 21 ii 3.2 The Design of Low Noise Amplifier 22 3.2.1 Low Noise Amplifier Design 24 3.2.2 Low Noise OTA Design 28 3.3 The Design of ADC 34 3.3.1 ADC System Architecture 35 3.3.2 Sampling-and-Hold Design 38 3.3.3 DAC Capacitor Array Design 41 3.3.4 Comparator Design 45 3.3.5 SAR and Digital Control Design 51 3.4 Design summary 55 CHAPTER 4.1 Overall System Implementation and Verification 56 Layout Design 56 4.1.1 Low Noise Amplifier (LN-AMP) Layout Design 57 4.1.2 SA-ADC Layout Design 60 4.1.3 Integrated System Floor Plan Design 63 4.2 Post Layout Simulation 64 4.2.1 LN-AMP Simulation Results 64 4.2.2 SA-ADC Simulation Results 69 CHAPTER 5.1 Measurements and Discussions 73 Measurement Results 74 5.1.1 LN-AMP Measurement Results 74 5.1.1.1 Differential Mode Gain and Bandwidth 74 5.1.1.2 Input referred noise 77 iii 5.1.1.3 Common mode rejection ratio 80 5.1.1.4 Power supply rejection ratio 82 5.1.1.5 Summary 84 5.1.2 5.2 SA-ADC and Overall Measurement Results 86 Testing Issues and Discussions 89 5.2.1 LN-AMP Input referred noise 89 5.2.2 ADC parameters measurement 90 5.2.3 External interference 92 CHAPTER Conclusion and Future Work 93 6.1 Conclusion 93 6.2 Future Work 94 References 96 Appendix A 102 Appendix B 103 iv Summary In recent years, numerous researches are done on non-invasive medical diagnostic as the method is suitable to provide essential information without invasive measures One of the main focuses is on portable medical devices which emphasizes on real-time monitoring Bio-signals of interest in recent researches include ECG (Electrocardiogram) and EEG (Electroencephalogram) signals To suit into long-term recording or monitoring, an ideal portable device would be highly integrated and fully portable However such devices would have stringent requirements on supply voltage and power consumption On top of that, ECG signal is usually weak in magnitude (in terms of mV) and in the range of low frequencies (0.1 to 150 Hz), which means the signal could be easily masked by flicker noise It is essential for the device to have ultra low input referred noise to pick up the ECG signal In addition, large DC offset due to the electrochemical interface between electrode and human skin needs to be rejected during signal acquisition This work presents a low power low voltage ECG signal acquisition IC chip The overall system consists of a low noise instrumentation amplifier (LN-AMP) with DC offset rejection, and an 11 bit successive approximation analog-to-digital converter (SAADC) The LN-AMP is basically a pseudo-differential amplifier with differential input and single-ended output structure Diode-connected PMOS transistors are used as pseudoresistor, which have resistance in the order of 1012 , to form an ultra-low cut-off frequency high pass filter with input capacitors to reject DC offset The low noise OTA v (LN-OTA) is using a standard current mirror OTA design The transistor sizes are optimized to achieve a low input referred noise OTA with reasonable phase margin and power consumption Successive approximation approach is used in the ADC design This is due to SAADC attains a well balance between resolution, speed, and circuit complexity The architecture of SA-ADC is modified from conventional structure so that the converter can achieve full swing input range To conserve power consumption, several tactics are used in the design The sample-and-hold (S/H) operation is integrated into the LN-AMP output stage and thus no additional power is needed for S/H operation Meanwhile, MSB capacitor array is “split” into a sub-array which is identical to the rest capacitor array so that switching energy is reduced during conversion phase In addition, comparator circuits are turn off during sampling phase and only active during ADC conversion phase Finally, serial output design is employed to reduce digital circuit complexity and thus power consumption Overall system was implemented in AMS 0.35µm standard CMOS process and the design performance was verified by post-layout simulation The fabricated chip was measured to extract the performance statistics Overall integrated system is consuming 4µW under 1.5V supply voltage The measured input referred noise is 1.862µVrms while the bandwidth is 5mHz to 190Hz Overall system achieves effective number of bit (ENOB) of 9.3 bit with 500S/s sampling rate In conclusion, there is still research window opened for improvement on the ECG signal acquisition chip Future development to integrate with RF circuit for wireless transmission is a possible pathway vi List of Figures Figure 1.1 A typical ECG signal graph Figure 2.1 A typical CMOS amplifier noise spectrum Figure 2.2 A DDA-based IA architecture Figure 2.3 Low noise amplifier architecture in [12] 10 Figure 2.4 Low noise OTA used in [13] 11 Figure 2.5 General flash ADC architecture 13 Figure 2.6 A general bit two-step ADC architecture 14 Figure 2.7 A general dual-slope integrating ADC architecture 15 Figure 2.8 D/A converter-based SA-ADC architecture 16 Figure 2.9 A modified low voltage SA-ADC architecture in [15] 17 Figure 2.10 A modified low voltage SA-ADC architecture in [16] 18 Figure 2.11 A modified low voltage SA-ADC architecture in [13] 19 Figure 3.1 Overall design architecture 21 Figure 3.2 Low noise amplifier (LN-AMP) 25 Figure 3.3 Incremental resistance of single MOS-bipolar element [12] 27 Figure 3.4 The schematic of LN-OTA circuit 29 Figure 3.5 Overall SA-ADC structure 36 Figure 3.6 Flow chart of SAR operation 37 Figure 3.7 LN-OTA with integrated S/H function 39 Figure 3.8 A typical 11 bit DAC capacitor array 41 Figure 3.9 An 11 bit series split DAC capacitor array 42 vii Figure 3.10 “Split” structure with MSB sub-array and the rest capacitors sub-array 43 Figure 3.11 Comparison of different approach for down conversion example 44 Figure 3.12 Overall comparator architecture 45 Figure 3.13 Comparator pre-amplifier circuit 47 Figure 3.14 Input offset cancellation of comparator pre-amplifier 47 Figure 3.15 Comparator regenerative latch 49 Figure 3.16 SR latch 50 Figure 3.17 SAR and control logics digital block 51 Figure 3.18 Shift register structure 52 Figure 3.19 Control and multiplexer structure 54 Figure 4.1 LN-AMP layout 57 Figure 4.2 Capacitor network of the LN-AMP 58 Figure 4.3 LN-OTA layout 59 Figure 4.4 SA-ADC layout 60 Figure 4.5 Comparator layout 61 Figure 4.6 DAC capacitor array layout 61 Figure 4.7 Overall integrated system layout 63 Figure 4.8 Magnitude response of LN-AMP 65 Figure 4.9 Phase response of LN-AMP 66 Figure 4.10 Input referred noise spectral density 67 Figure 4.11 Integrated input referred noise 68 Figure 4.12 Frequency response of the comparator preamp 70 Figure 4.13 Transient results of overall comparator 70 viii Finally, overall measurement results of the overall integrated system are summarized in Table 5.2 Parameters Values Supply voltage 1.5V ADC sampling rate 500S/s ADC ENOB 9.3 bit Total current 2.7µA Core chip area 1.06mm2 Table 5.2 Summary of overall measurement results for integrated system 5.2 Testing Issues and Discussions In the process of measuring the performance of the chip, there are several main testing issues encountered and will be discussed in this section 5.2.1 LN-AMP Input referred noise The measured integrated input referred noise is found to be higher than the expected value obtained from simulation In simulation results shown in chapter 4, the in-band integrated input referred noise is 1.7µVrms However, as depicted in the previous section, the measured value is 1.862µVrms, about 0.162µVrms higher than the simulation results There are two factors that results in higher input referred noise First factor is regarding to the bandwidth of the LN-AMP The in-band integrated input referred noise 89 integrates the input referred noise spectral density within the bandwidth of the LN-AMP The measured low pass 3dB cut-off frequency at 190 Hz is nearly the same with simulation results at 192Hz However, the measured high pass 3dB cut off frequency is much lower than the simulation results In simulation, the cut-off frequency is about 130mHz while measured result is about 5mHz which is more than a decade away The higher bandwidth results in more noise to be integrated for the in-band input referred noise parameter Second factor is the higher level of flicker noise in measurement than simulation From Figure 5.6 it can be seen that the flat thermal noise level is about 100 nV/ Hz near to simulation results However, the flicker noise level at 1Hz is recorded to be 320 nV/ Hz as compared to 230 nV/ Hz in simulation Furthermore the difference at lower frequency is even greater At 200mHz, simulation result shows 430 nV/ Hz while measurement reveals an almost double value of 800 nV/ Hz This clearly shows the simulation model underestimates the flicker noise level in physical device Hence in future design, an overestimation on noise level is definitely needed if the same simulation model is to be used 5.2.2 ADC parameters measurement In the ADC measurement test setup, a stand-alone ADC in the fabricated chip was initially used as the DUT However, the S/H circuit is inevitable in measuring the performance of an ADC Due to inexperience in ADC measurement and time-constraint, an internal S/H circuit was not integrated with the individual ADC block 90 To solve this problem, an external switch was used to form the S/H circuit with the on-chip DAC capacitor array in the individual ADC For such a simple S/H circuit, the time constant, τ is given by τ = RONCH (5.3) where RON is the on-resistance of the switch and CH is the holding capacitor The value of τ would decide the maximum holding time for an S/H circuit In this case, CH is approximately 128pF represented by the on-chip DAC capacitor array However, measurement revealed that the voltage at the ADC input node cannot be held throughout the whole conversion phase While RON of the external switch is at very low level, the time constant cannot be improve since CH is fixed Under such circumstances, the performance of the ADC can only be extracted from full integrated system measurements In integrated system architecture, the input stage is a LN-AMP followed by the SAADC Hence the full integrated system measurements cannot fully reflect the performance of the individual ADC as the input stage LN-AMP has introduced nonideality to the signal before ADC This is reflected from the power spectral density plot of the ADC digital output in Figure 5.10 The harmonics are basically introduced by the LN-AMP while the noise floor is elevated by the device noise from LN-AMP These would deteriorate the SQNR and hence the ENOB measured Besides that, the DNL and INL performance are seriously affected due to the same reason A ramp input signal is used in the test setup shown in Figure 5.11 for DNL and INL measurement However, there are constraints on the input where the frequency and magnitude of the ramp input signal is restricted by the LN-AMP Using a 6mVpp 50mHz 91 ramp input signal, the DNL reaches 4LSBs In overall, these results cannot fully reflect the actual performance of the ADC due to the mentioned factors 5.2.3 External interference Another issue observed during measurement is the external interference on the measurement results, especially the 50Hz power line interference The effect can be seen obviously in the input referred noise and ADC output power spectral density plot To minimize this interference, a notch filter at 50Hz can be used in the system However, very large capacitor and very low transconductance are needed to realize a high order filter with notching at frequency as low as 50Hz There is a limitation on area used if to achieve a fully integrated portable device while additional block would add to power consumption as well Hence it is hardly advisable to add a notch filter in the system A workable solution is to process the digital output using digital filter at base station As to be discussed in chapter 6, if future work is done to transmit the digital signal output wirelessly to a base station, it will be more sensible to filter the 50Hz interference at the base station 92 CHAPTER Conclusion and Future Work 6.1 Conclusion The design an ECG signal acquisition chip was presented in this thesis The design consists of a Low Noise Amplifier (LN-AMP) and an 11 bit Successive Approximation Analog-to-Digital Converter (SA-ADC) Overall work done for this research included circuit design, layout implementation, post-layout verification, testing setup and chip measurements With careful optimization of transistor sizes and operation in weak inversion region for better gm/ID efficiency, the chip achieves a performance of 1.862µVRMS input referred noise over the system bandwidth from 5mHz to 190Hz The sampling rate of the system is set to 500S/s with a 30 kHz clock rate Overall system achieves an Effective Number of Bit (ENOB) of 9.3 bit with a measured SQNR of 57.7dB The integrated system consumes a total current of 2.7µA under 1.5V supply voltage, which gives a power consumption of 4.05µW A comparison with other works is presented in Table 6.1 93 Design [8]*1 [12] *2 [13] *3 This work Process 0.5µm 1.5µm 0.35µm 0.35µm CMOS CMOS CMOS CMOS Supply voltage (V) +/- 1.5 +/- 2.5 1.5 Mid-band Gain (dB) - 80 39.5 40.2 46 Bandwidth (Hz) 0.3 – 150 25m – 7.2k 3m – 245 5m – 190 Input referred noise (µVrms) 0.86 2.2 2.7 1.862 Current consumption (µA) 485 16 2.3 2.7 Table 6.1 Comparison between few reported ECG chips and this work Notes: *1 Chip includes multiplexer, rail-to-rail IA, programmable gain amplifier, low pass filter, output scaling amplifier and digital control, for EEG and ECG signal acquisition *2 Chip includes a LN-AMP for general purpose *3 Chip includes a LN-AMP and a SA-ADC for ECG signal acquisition 6.2 Future Work As compared in table 6.1, noise efficient factor of the present LN-AMP design is considerably less than works in [12] and [13] although input referred noise is lower with comparable total system power consumption The noise efficient factor reflects the trade- 94 off between input referred noise performance and current consumption More works could be done to improve on the transconductance of the LN-OTA to achieve a better current efficiency with present input referred noise level As for the ADC, more efforts are needed to improve the SQNR performance In addition, there are issues in the ADC test setup as mentioned in chapter Hence in future work more attentions are required on the test plan in order to avoid such an issue happening once more Another possible future improvement is on the portability of the system It would be a possible innovation to integrate a wireless transmission circuit to transmit the acquire data to a base station for post processing As most of the post processing is in digital domain, letting the digital processing to be done at base station will greatly reduce the complexity of a signal acquisition chip and hence the power consumption This would certainly enhance the battery life of a portable device In conclusion, a full integration ECG signal acquisition chip would be an ideal portable device for the use of non-invasive diagnostic measure and long-term recording The research window is still open for further enhancing the performance 95 References [1] O.B.C Tsutomu, K.D Norie, H.F Manabu, N.G Satoshi, M Masako, N Emi, M Tadao, “Electroencephalographic Measurement of Possession Trance in the Field,” Clin Neurophysiol., Vol 113, No 3, March 2002, pp 435-445 [2] N Utsuyama, H, Yamaguchi, S Obara, H Tanaka, S Fukuta, J Nakahira, S Tanabe, E Bando, H Miyamoto, “Telemetry of Human Electrocardiograms in Aerial and Aquatic Environments,” IEEE Trans Biomed Eng., Vol 35, No 10, October 1988, pp 881-884 [3] Braunwald E., Heart Disease: A Textbook of Cardiovascular Medicine, 5th Edition, Philadelphia: W.B Saunders Co., 1997 [4] Van Mieghem C., Sabbe M., Knockaert D., “The Clinical Value of the ECG in noncardiac conditions,” Chest, Vol 125-4, April 2004, pp 1561-1576 [5] J.G Webster, Medical Instrumentation: Application and Design, 3rd Edition, New York: Wiley, 1998 [6] Rui Martins, Siegfried Selberherr, Francisco A.Vaz, “A CMOS IC for Portable EEG Acquisition Systems,” IEEE Trans Instrum Meas., Vol 47, No 5, Oct 1998, pp 1191-1196 96 [7] J J Pancrazio, P P Bey, Jr., A Loloee, S Manne, H C Chao, L L Howard, W M Gosney, D A Borkholder, G T A Kovacs, P Manos, D S Cuttino, and D A Stenger, “Description and Demonstration of a CMOS Amplifier-Based-System with Measurement and Stimulation Capability for Bioelectrical Signal Transduction,” Biosensors Bioelectron., Vol 13, 1998, pp 971–979 [8] K.A Ng, P.K Chan, “A CMOS Analog Front-End IC for Portable EEG/ECG Monitoring Applications,” IEEE Transactions on Circuits and Systems-I:Regular Papers, Vol 52, No 11, November 2005, pp 2335-2347 [9] Adel S Sedra, Kenneth C Smith, Microelectronic circuits, 5th edition, Oxford University Press, 2004 [10] David A Johns, Ken Martin, Analog Integration Circuit Design Toronto: John Wiley & Sons, Inc., 1996 [11] Aldert Van Der Ziel, “Unified Presentation of 1/f Noise in Electronic Devices: Fundamental 1/f Noise Sources,” Proc Of the IEEE, Vol 76, No 3, March 1988 [12] Reid R Harrison and Cameron Charles, “A Low-Power Low-Noise CMOS Amplifier for Neural Recording Applications,” IEEE Journal of Solid-State Circuits, Vol 38, No 6, June 2003, pp 958-965 97 [13] Honglei Wu and Yong Ping Xu, “A 1V 2.3uW Biomedical Signal Acquisition IC,” 2006 IEEE International Solid-State Circuits Conference, pp 58-59 and 637 [14] Mikko E Waltari, Kari A.I Halonen, Circuit Techniques for Low-Voltage and High-Speed A/D Converters, Netherlands: Kluwer Academic Publishers, 2002 [15] J Sauerbrey, D Schmitt-Landsiedel, R Thewes, “A 0.5V, 1µ W Successive Approximation ADC,” Proc 28th ESSCIRC, Sept 2002, pp 247-250 [16] T Yoshida, et al., “A 1V Supply Successive Approximation ADC with Rail-toRail Input Voltage Range,” Proc ISCAS, May 2005, pp 192-195 [17] Behzad Razavi, Design of Analog CMOS Integration Circuits, International Edition Singapore: McGraw-Hill International, 2001 [18] Y Tsividis, Operation and Modeling of the MOS Transistor, 2nd Edition Boston, MA: McGraw-Hill, 1998 [19] C Jakobson, I Bloom, Y Nemirovsky, “1/f Noise in CMOS Transistors for Analog Applications from Subthreshold to Saturation”, Solid-State Electron., Vol 42, no 10, 1998, pp 1807-1817 98 [20] M.S.J Steyaert, W.M.C Sansen, C Zhongyuan, “A Micropower Low-Noise Monolithic Instrumentation Amplifier for Medical Purposes,” IEEE Journal of Solid-State Circuits, Vol SC-22, Dec 1987, pp 1163-1168 [21] E.A Vittoz, J Fellrath, “CMOS Analog Integrated Circuits Based on Weak Inversion Operation,” IEEE Journal of Solid-State Circuits, Vol 12, June 1977, pp 224-231 [22] C C Enz, F Krummenacher, E A Vittoz, “An Analytical MOS Transistors Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications,” Analog Integrated Circuits Signal Processing, Vol 8, 1995, pp 83-114 [23] T Delbrük, C.A Mead, “Analog VLSI Adaptive, Logarithmic Wide-Dynamic Range Photoreceptor,” Proc IEEE International Symposium Circuits and Systems, Vol 4, 1994, pp 339-342 [24] P Allen, Douglas R Holberg, CMOS Analog Circuit Design, 2nd edition, New York: Oxford University Press, 2002 [25] Paul R Gray, Robert G Meyer, Analysis and Design of Analog Integrated Circuits, 1993 99 [26] S Sakurai, M Ismail, Low-Voltage CMOS Operational Amplifiers, Boston, MA:Kluwer Academic, 1995 [27] J McCreary, P Gray, “All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques,” IEEE J Solid-State Circuits, Vol SC-10, No 12, Dec 1975, pp 371-379 [28] B P Ginsburg, A P Chandrakasan, “An Energy-Efficient Charge Recycling Approach for a SAR Converter with Capacitive DAC,” Proc IEEE Int Symp Circuits and Systems, vol 1, 2005, pp 184-187 [29] Brian P Ginsburg and Anatha P Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS with Split Capacitor Array DAC,” IEEE Journal of Solid-State Circuits, Vol 42, No 4, April 2007, pp 739-747 [30] R Jacob Baker, CMOS Circuit Design, Layout and Simulation, 2nd Ed., Wiley- IEEE Press, 2004 [31] Alan Hastings, Art of Analog Layout, 2nd Ed., Prentice Hall, 2005 [32] Christopher Saint, Judy Saint, IC Layout Basics: A Practical Guide, 1st Ed., McGraw-Hill Professional, 2001 100 [33] Christopher Saint, Judy Saint, IC Mask Design: Essential Layout Techniques, 1st Ed., McGraw-Hill Professional, 2002 [34] Mark Burns, Gordon W Roberts, An Introduction to Mixed-Signal IC Test and Measurements, USA: Oxford University Press, 2004 101 Appendix A Overall chip layout with pads 102 Appendix B PCB for chip measurement 103 ... art of the states on low power low voltage biosignal acquisition chip As mentioned in chapter 1, overall integrated system in this signal acquisition chip includes a Low Noise Amplifier (LN-AMP)... Overall Chip Architecture The overall ECG signal acquisition chip includes a Low Noise Amplifier (LN-AMP) and a Successive Approximation Analog-to-Digital Converter (SA-ADC) The overall block diagrams... considered are capacitor area and device matching Lower capacitance has a smaller area in layout but larger mismatch between devices Mismatch between C1 and C2 leads to deviation from the designed gain