magma training talus design

® Magma Training Talus ® Design Talus 1.1 December 2010 Magma ® Design Automation Incorporated 1650 Technology Drive San Jose, CA 95110 408.565.7500 Contact: training@magma-da.com Magma Confidential Copyright © 1997–2010 Magma Design Automation Inc. All rights reserved. Magma Training : Talus Design, Talus 1.1 This document, as well as the software described in it, are furnished under license and can be used or copied only in accordance with the terms of such license. The content of this document is furnished for information use only, is subject to change without notice, and should not be construed as a commitment by Magma Design Automation Inc. Magma Design Automation Inc. assumes no responsibility or liability for any errors, omissions, or inaccuracies that might appear in this book. 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Magma Talus Design Training Agenda Timing Analysis, Placement, and Timing Optimization Import Lib and RTL - Reading in Library Volcanos - Reading in HDL fix rtl - High-Level Synthesis - Data Path Generation fix netlist - Area Optimization - Initial HyperCell Mapping LAB: RTL Import fix netlist Magma Timing Constraints fix time - Timing-Driven Optimization Static Timing Analysis - Timing Analysis and Debug in Magma - Check Timing and Reporting/Timing Viewer LAB: Fix Time DFT - Scan Constraints - Scan FF Insertion - DFT Violation Checks LAB: DFT Semi-Automatic Planning and Placement for Front-End Designers - Floorplanning - Placement - Physical Opt - fix plan - fix power - fix cell LAB: Floorplanning and Placement 1 Import Library and RTL Import lib & RTL Agenda • Import libraries • Set variables • Cfi ti • C on fi gura ti ons • Analyze and elaborate Magma Confidential - 2 1 Import lib & RTL Magma Design Flow RTL Optimization RTL Import Area Optimization Ti i O ti i ti You are here fix rtl fix netlist fi i Iterate as Needed Develop Constraints DFT Insertion Ti m i ng O p ti m i za ti on Floorplanning HyperCell Domain Real Cell Domain fi x t i me fix plan fix cell (early CTS) Physical Synthesis Clock Tree Synth. fix clock (opto CTS) Needed Report Analysis Magma Confidential - 3 fix optimize fix wire Detailed Routing Global mode optimization Final mode optimization fix optimize Talus COre TM Technology Concurrent timing optimization throughout the flow Import lib & RTL Importing the Library • Import previously prepared library Volcano database import volcano stdcell_lib_name.volcano -object $l • After importing the technology Volcano set $l if you haven ’ t After importing the technology Volcano , set $l , if you haven t already set l /stdcell_lib_name • Set the target library configuration • Set the RTL search path F V il 2000 d i bl t Magma Confidential - 4 • F or V er il og 2000 d es i gns, ena bl e suppor t 2 Import lib & RTL Setup Variables • For ease of use, set some variables: set m /work/demod_multi/demod_multi set l /cl013lv set lr /ram_lib • By convention: • m is the top-level model name • l is the name of the standard cell library • l r is the name of the RAM librar y Magma Confidential - 5 y • You can use any name for the secondary libraries. Talus Design assumes that $l points to your standard cell library • These variables are used by almost every Magma command. It is important to define this early in the flow. Import lib & RTL Compatible RTL Coding • Magma RTL synthesis is • Completely compatible with industry-standard coding style • Talus Design fully supports the Synopsys coding style, commonly used pragmas, instantiated DesignWare components, and hard macros. • Magma does not support design constraints as pragmas (dont_touch, dont_use, and so forth) • Language-neutral for Verilog and VHDL • Mix both VHDL and Verilog blocks within a single design anywhere in the hierarchy. • Verilog 95/2000 and VHDL - 87/93 System Verilog 2005 support Magma Confidential - 6 Verilog 95/2000 and VHDL 87/93 System Verilog 2005 support 3 Import lib & RTL Pragma Support • Talus Design interprets the commonly used Synopsys pragmas (directives) for both VHDL and Verilog. • Translate_off/on c ase (Sel) //synopsys full _ case • Full/parallel case • Function map to module • Asynchronous set and reset • The following syntax is supported: • -pragma or -synopsys for VHDL designs _ 2'b00 : D_Out = A; 2'b01 : D_Out = B; 2'b10 : D_Out = C; endcase Magma Confidential - 7 • //synthesis or //synopsys for Verilog designs • You can also use config rtl directive to specify compiler directives Import lib & RTL Third Party Module Support • Talus Design supports direct instantiation of the commonly used Synopsys DesignWare components DW01_add, DW01_sub, DW01_addsub, DW01_csa, DW_square, DW01_dec, DW01_inc, DW01_absval, DW01_incdec, DW01_ash, DW01_bsh, DW shifter DW01 cmp2 DW01 cmp6 DW01 decode DW01 binenc DW_shifter , DW01_cmp2 , DW01_cmp6 , DW01_decode , DW01_binenc , DW01_prienc, DW01_mux_any, DW01_satrnd, DW02_prod_sum, DW02_sum, DW02_mult_2_stage, DW02_mult_3_stage, DW02_mult_4_stage, DW02_mult_5_stage, DW02_mult_6_stage, DW02_mult, DW02_div_rem, DW02_divide, DW02_rem, DW02_mac, DW03_bict_dcnto, DW03_bict_scnto, DW03_updn_ctr, DW03_bictr_decode ….the list is constantly growing… See Appendix slide in this module for current component list • DW01_add #(8,8) U1 (.A (in1), .B (in2), .CI (cin), .SUM (sum), .CO (co t)) Magma Confidential - 8 (co u t)) ; • Initially, all components assigned minimum area architectures • During the constraint-driven optimization phase, architectures are reselected to meet timing constraints 4 Import lib & RTL Importing RTL Into Talus • Use the following command to import RTL into Talus: import rtl -analyze [-vhdl|-verilog] -include directory_name file_list Analyzes the RTL file but does not perform elaboration Indicates that RTL files are Verilog -analyze verilog Indicates that RTL files are Verilog Defines `ifdef variable names in Verilog Specifies the name of the directory with any include files referenced in the Verilog RTL Indicates the RTL files are VHDL For VHDL designs, allows source files to be specified in any order Specifies to use VHDL-87 mode rather than VHDL-93 (VHDL-93 is the default) Selects the default architecture that will be chosen for arithmetic o p erators - verilog -define -include dir_name -vhdl -sort -87 -arithmetic Magma Confidential - 9 import rtl -analyze –verilog \ -include ./include_dir chip.v cntr.v interface.v p Specifies the work library. The default is work Specifies a list of all the RTL files to import -lib file_list Import lib & RTL run rtl elaborate -vhdl -verilog [-parameters param_name] \ -architecture arch_name -lib -add_dc -case top_model_name Elaborating the Design • After analyzing the RTL, elaborate the design. -verilog -lib -arithmetic -parameters -vhdl -architecture -case Performs elaboration on a Verilog design Specifies the library. The default is work Specifies default architectures for datapath elements. (auto, small, fast) Overrides default parameters or generic values of the module Performs elaboration on a VHDL design Specifies an architecture for VHDL designs Handles how the case of names are translated for VHDL designs (upper,lower, preserve) Magma Confidential - 10 • During elaboration, the design is loaded into the Talus /work library unless you specify the -lib option • Example: run rtl elaborate chip (upper,lower, preserve) 5 Import lib & RTL Useful Configuration Settings • Set the target library configuration config rtl targetlib $l • For designs that contain macros within the RTL, this is necessary to resolve and bind all cells; otherwise you will have unresolved references and bind all cells; otherwise , you will have unresolved references • Set the RTL search path config rtl searchpath • For designs that contain extensive directory structures, this makes scripts much cleaner. (You do not need to specify the full path for each RTL file) • Enable Verilog 2000 support fi l il 2000 Magma Confidential - 11 con fi g rt l ver il og 2000 on • If the design contains Verilog 2000 constructs, you must set this to parse the RTL. Import lib & RTL Importing RTL: Resulting Directories • After import rtl, two Talus libraries called /work and /macro_lib are created • The Talus library /work contains the design data after elaboration • The Talus /macro_lib library contains the basic architecture for data path components • A UNIX directory called ./work is created under the directory where Talus was started • The work directory contains intermediate binary files (.mod for Verilog modules, .ent, .pkg, and .cnf for VHDL) created after import rtl Magma Confidential - 12 modules, .ent, .pkg, and .cnf for VHDL) created after import rtl • These binaries are loaded into the Talus work library /work during elaboration 6 [...]... state.v run rtl elaborate -verilog -case preserve chip Match the language to the top-level design Elaborate the design from the top Magma Confidential - 13 Summary Import lib & RTL • Import libraries • Set variables • C fi Configurations ti • Analyze and elaborate Magma Confidential - 14 7 Supported DW Components – Talus Design Appendix Supported DW Components Import lib & RTL • • • • • • • • • • • • • •... [OPcache_reg[0]] Magma Confidential - 20 18 Summary fix rtl • High-level optimization • • • • Clockgating Data-path optimization p p Autoflattening Creating domains Magma Confidential - 21 19 20 1 fix netlist Agenda fix netlist • Optimization settings • • • • Prerequisites Scan considerations QOR considerations Hierarchy • Parallel running • Appendix: Literals Magma Confidential - 2 21 Magma Design Flow... DW_ram_r_w_s_dff • DW_shifter • DW_square • DW_squarep • DW_stack • DW_stackctl • DW_tap • DW_minmax • DW_8b10b_dec Magma Confidential - 16 8 fix rtl Agenda fix rtl • High-level optimization • • • • Clockgating Data-path optimization p p Autoflattening Creating domains Magma Confidential - 2 9 Magma Design Flow fix rtl RTL Import You are here RTL Optimization Develop Constraints fix rtl Area Optimization fix... optimize fix wire Talus COreTM Technology Concurrent timing optimization throughout the flow fix optimize Magma Confidential - 3 Area Optimization Overview fix netlist fix netlist model library [-scan] \ [-effort low | medium | high] [-parallel launch_spec] • Boolean logic area optimization • Final product is a netlist of HyperCell abstracts for a design with the least possible area Magma Confidential... module use force maintain /work/moduleB/moduleB • If design is timing critical, override area optimization steps, f which create more levels of logic: force gate opt_mode object delay/area -hier • This can be done for the whole design or part of it Magma Confidential - 6 23 Area Optimization Settings: QOR Considerations (contd) fix netlist • For custom-designed blocks (such as data paths or control logic),... connection close Magma Confidential - 9 Summary fix netlist • Optimization settings • • • • Prerequisites Scan considerations QOR considerations Hierarchy • Parallel running Magma Confidential - 10 25 Lab 1: RTL Import, Area Optimization fix netlist • In this lab, you will: • Import Verilog HDL • Elaborate the design g • Perform area-based HyperCell optimization • Expected time: 30 – 60 mins Magma Confidential... (5-1)+(3-1)+(3-1)+(3-1)=10 3 3 3 factor tree of a node Magma Confidential - 13 27 28 1 Constraints for Timing Optimization Agenda Timing Constraints • Define paths • Define clock domains • Latency and Margin • Define I/O timing • Define constants • Constant propagation • Define timing exceptions • Appendix: PLL Constraints & Multi-Mode Analysis Magma Confidential - 2 29 Magma Design Flow Timing Constraints RTL Import... are provided by the library vendor din D Q dout din D Q dout latch EN Test D G ICG Q EN Test D ECK clk CLK clk Magma Confidential - 8 12 RTL Opt Settings: Data-Path Optimization fix rtl • Talus optimizes arithmetic components by using derived function + M MUX dataout +/- - dataout rd rd • Talus can reorder data path to reduce components Y = A + B + C + D; Z = A + C; then Y = Z + B + D • This can be... Wallace tree + + out out • Formal tool might need advance features to verify it • To control it, use config rtl merging on | off Magma Confidential - 10 13 RTL Opt Settings: Data Path Architectures fix rtl • Talus creates and selects data-path components from a wide range available in Magma; you can also control the selection • While elaborating run rtl elaborate object [-arithmetic auto|fast|small] • To... partitioning • For precompiled blocks, area optimization can be skipped force keep /work/precompiled/precompiled -content • Use the strategy that is best suited for your design Magma Confidential - 7 Area Optimization Settings: Hierarchy fix netlist • Talus provides control over preserving cells and hierarchy in the flow • Preserve specific instance that might be used later in flow p g (defining clock, scan control, . Contact: training @magma- da.com Magma Confidential Copyright © 1997–2010 Magma Design Automation Inc. All rights reserved. Magma Training : Talus Design, Talus 1.1 This document,. Magma Training Talus ® Design Talus 1.1 December 2010 Magma ® Design Automation Incorporated 1650 Technology Drive San Jose, CA 95110 408.565.7500 Contact: training @magma- da.com. property rights that Magma Design Automation Inc. has established in any of its product, feature, or service names or logos. Registered Trademarks Magma, the Magma logo, Magma Design Automation,