Performance Evaluation and Comparison 379 mance is shown in Figure 9.38 for and in Figure 9.39 for . With SEs the Shuffleout switch gives the best performance owing to its shortest path routing which is more effective than the simple bit self-routing applied in the Shuffle Self-Routing and Rerouting switch. With the more complex SEs the Shuffleout SEs still perform the best, with the Shuffle Self-Routing giving a rather close performance especially for large networks. The Dual Shuffle switch gives a significantly higher loss probability for the same network stages. We would like to conclude this loss performance review, by comparing the number of stages K required for a variable network size to guarantee a loss performance of for the six architectures based on deflection routing just considered: the results are given in Figure 9.40, respectively. All the curves grow almost linearly with the logarithmic switch size. Therefore we can conclude that minimum complexity of the order of characterizes not only the Dual Shuffle switch, as pointed out in [Lie94], but all the other architectures based on deflection routing. It can be shown that this property applies also to the Tandem Ban- yan switch. With this feature established, we need to look at the gradient and the stage number for a minimum size switch in order to identify the real optimum architecture. According to our previous considerations, Shuffleout requires the minimum amount of hardware in the interconnection network to attain a given loss figure, whereas the Shuffle Self-Routing (Dual Shuffle) needs the maximum amount of hardware with ( ) SEs. The conclusions to draw from these figures are that Shuffleout gives the best cost/performance ratio at the expense of implementing shortest-path routing. If bit-by-bit routing is preferred, Shuffle Self- Routing and Rerouting with extended routing provide the best solution with and SEs. Analogous results have been obtained for a different loss probability target. Figure 9.37. Loss performance comparison for different architectures 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 0 20 40 60 80 100 120 N=1024, p=1.0 Sh_SR TBSF, Kd=1 TBSF, Kd=2 TBSF, Kd=3 BRBN Network cell loss probability, π n Number of stages, K N 16= N 1024= 24× 46× 10 6– NN 2 log 24× 46× 24× 46× defl_net Page 379 Tuesday, November 18, 1997 4:14 pm 382 ATM Switching with Arbitrary-Depth Blocking Networks 9.4.7. Overall switch performance After analyzing the loss performance occurring in the interconnection network due to the finite number of network stages, attention is now given to the other two components where cell loss can take place, that is the output concentrator and the output queue. Recall that in general concentrators are not equipped in the Tandem Banyan switch owing to the small num- ber of lines feeding each output queue. The average load offered to the concentrator is given by . Following [Yeh87], we assume that all the local outlets feeding the concentrator carry the same load and are independent of one another, so that the packet loss probability in the concentrator is given by (9.16) Figure 9.41 shows the loss performance of a concentrator with output lines for a variable offered load level and three values of the number of its inlets, , which also represent the number of switching stages in the interconnection network. It is observed that the performance improves as the number of sources decreases for a given offered load as a larger set of sources with lower individual load always represents a statistically worse situation. In any case the number of concentrator outlets can be easily selected so as to provide the target loss performance once the stage number and the desired load level are known. Alternatively if and C are preassigned, a suitable maximum load level can be suitably selected according to the performance target. Figure 9.41. Loss performance in the concentrator p c p c p 1 π n –()= K b π c 1 p c iC–() K b i p c K b i iC1+= K b ∑ = 1 p c K b – K b i– C 9= K b 16 32 64,,= K b 10 -10 10 -9 10 -8 10 -7 0.70 0.75 0.80 0.85 0.90 0.95 1.00 Concentrator - C=9 Cell loss probability, π c Offered load, p c K=16 K=32 K=64 defl_net Page 382 Tuesday, November 18, 1997 4:14 pm Performance Evaluation and Comparison 383 The average load offered to the output queue is given by ; apparently in the Tandem Banyan switch which does not employ concentrators. Each output queue is fed by L links, where for all the architectures with output concentrators and for the Tandem Banyan switch. So the cell arrival process at the queue has a binomial distribution, that is the probability of i cells received in a slot is The server of the queue transmits one packet per slot, therefore the output queue can be classified as discrete-time , where B o (cells) is the output queue capacity. By solving numerically this queue (see Appendix), the results in Figure 9.42 are obtained for different load levels ranging from to when the concentrator feeding the queue is equipped with output lines. As one might intuitively expect, limiting the offered load level is mandatory to satisfy a given loss performance target. Observe that the above evaluations of the cell loss in the concentrator and in the output queue are based on the assumption that all the traffic sources generate the same traffic. This is clearly an approximation since the lines feeding each concentrator give a load that decreases from 1 to (the load carried by the network stages decreases due to the earlier network exits). Nevertheless, our analysis is conservative since it gives pessimistic results compared to reality: assuming homogeneous arrivals always corresponds to the worst case compared to any type of heterogeneous arrivals with the same load [Yeh87]. The total packet loss probability given by Equation 9.1 is plotted in Figure 9.43 for the Shuffleout switch with size , output lines per concentrator and output queues with a capacity of cells each under an offered load . The Figure 9.42. Loss performance in the output queue p q p q p c 1 π c –()= p q p c = LC= LK b = L i p q L i 1 p q L – Li– Geom L()D 1 B o ⁄⁄⁄ p q 0.5= p q 0.99= C 9= 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 1 10 100 Output queue - C=9 Cell loss probability, π q p q =0.5 0.6 0.7 0.8 0.9 0.95 Output queue size, B o 0.99 K b K b π t N 256= C 9= B o 64= p 0.7 0.8 0.9,,= defl_net Page 383 Tuesday, November 18, 1997 4:14 pm Switch Architectures with Parallel Switching Planes 385 parallel planes is shown in Figure 9.44 where each plane includes switching blocks. There- fore each output queue is fed now by links. As with the basic architectures based on deflection routing, one switching block consists of one switching stage with the Shuffleout, Shuffle Self-Routing and Rerouting switch, whereas it includes a banyan network with stages with the Tandem Banyan switch. Therefore the SEs have now the same size as in the respective basic architectures. In the case of the Dual Shuffle switch, two planes already exist in the basic version, which under the traffic sharing operation includes also the splitters. Considering the parallel architecture in the Dual Shuffle switch means that each SE in a plane has its own local outlets to the output queues. Therefore once we merge the SEs in the same stage and row into a single SE, whose internal “core” structure is either crossbar or ban- yan, the basic SE of the single resulting plane now has the size . The performance of architectures using parallel planes is now evaluated using computer simulation. The loss performance of the parallel Shuffleout switch is compared in Figure 9.45 with the corresponding data for the basic architecture under maximum load. It is noted that using two planes reduces the number of stages compared to the single plane case by a factor in the range 10–20%; larger networks enable the largest saving. For example a loss target of requires 47 stages in the basic architecture and 39 stages in the parallel one for . Nevertheless, the parallel architecture is altogether more complex, since its total number of stages (and hence the number of links to each output queue) is . Similar com- ments apply using interstage bridging and extended routing, when applicable, in all the versions of the three architectures Shuffleout, Shuffle Self-Routing and Rerouting. Table 9.2 gives the number of stages required to guarantee a network packet loss probability smaller than Figure 9.44. Model of ATM switch architecture with deflection routing and parallel planes K b 2K b N 2 log 44× 48× 21K b 0 1 N-2 N-1 C C C C Interblock connection pattern Interblock connection pattern Interblock connection pattern Switching block Switching block Switching block 0 1 N-2 N-1 10 8– N 1024= 39 2⋅ 78= defl_net Page 385 Tuesday, November 18, 1997 4:14 pm 388 ATM Switching with Arbitrary-Depth Blocking Networks and to the Shuffle-Self-Routing switch have been described in [Dec91b], Zar93b, respectively. The analysis of Shuffleout with SEs of generic size is described in [Bas94]. The traffic performance of deflection-based architectures has been evaluated based on the random and uniform traffic assumption. It is worth pointing out that traffic correlation has no impact on the dimensioning of the number of stages in ATM switches with arbitrary-depth networks. In fact the interconnection network is internally unbuffered and the only queueing takes place at the output interfaces. Therefore the correlation of traffic patterns just affects the dimensioning of the output queues of the structure. This kind of engineering problem has been studied for example in [Hou89]. Non-uniformity in the traffic pattern, that is unbal- anced in the output side, has been studied in [Bas92] for the Shuffleout architecture. Non- uniform traffic patterns in the Shuffleout switch have been studied in [Gia96]. 9.7. References [Awd94] R.Y. Awdeh, H.T. Mouftah, “Design and performance analysis of an output-buffering ATM switch with complexity of O(Nlog2N)”, Proc. of ICC 94, New Orleans, LA, May 1994, pp. 420-424. [Bas92] S. Bassi, M. Decina, A. Pattavina, “Performance analysis of the ATM Shuffleout switching architecture under non-uniform traffic patterns”, Proc. of INFOCOM 92, Florence, Italy, May 1992, pp. 734-742. Figure 9.47. Loss performance of Dual Shuffle with parallel planes 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 0 5 10 15 20 25 30 35 40 Dual Shuffle Crossbar - p=1.0 4x8 4x6 - sharing Network cell loss probability, π n Number of network stages, K N=16 N=64 N=256 N=1024 b 2b× defl_net Page 388 Tuesday, November 18, 1997 4:14 pm References 389 [Bas94] S. Bassi, M. Decina, P. Giacomazzi, A. Pattavina, “Multistage shuffle networks with shortest path and deflection routing: the open-loop Shuffleout”, IEEE Trans. on Commun., Vol. 42, No. 10, Oct. 1994, pp. 2881-2889. [Dec91a] M. Decina, P. Giacomazzi, A. Pattavina, “Shuffle interconnection networks with deflection routing for ATM switching: the Open-Loop Shuffleout”, Proc. of 13th Int. Teletraffic Con- gress, Copenhagen, Denmark, June 1991, pp. 27-34. [Dec91b] M. Decina, P. Giacomazzi, A. Pattavina, “Shuffle interconnection networks with deflection routing for ATM switching: the Closed-Loop Shuffleout”, Proc. of INFOCOM 91, Bal Harbour, FL, Apr. 1991, pp. 1254-1263. [Dec92] M. Decina, F. Masetti, A. Pattavina, C. Sironi, “Shuffleout architectures for ATM switch- ing”, Proc. of Int. Switching Symp., Yokohama, Japan, Oct. 1992, Vol. 2, pp. 176-180. [Gia96] P. Giacomazzi, A. Pattavina, “Performance analysis of the ATM Shuffleout switch under arbitrary non-uniform traffic patterns”, IEEE Trans. on Commun., Vol. 44, No.11, Nov. 1996. [Hou89] T C. Hou, “Buffer sizing for synchronous self-routing broadband packet switches with bursty traffic”, Int. J. of Digital and Analog Commun. Systems, Vol. 2, Oct Dec. 1989, pp. 253-260. [Lie94] S.C. Liew, T.T. Lee, “N log N dual shuffle-exchange network with error correcting rout- ing”, IEEE Trans. on Commun., Vol. 42, No. 2-4, Feb Apr. 1994, pp. 754-766. [Mas92] F. Masetti, A. Pattavina, C. Sironi, “The ATM Shuffleout switching fabric: design and implementation issues”, European Trans. on Telecommun. and Related Technol., Vol. 3, No. 2, Mar Apr. 1992, pp. 157-165. [Tob91] F.A. Tobagi, T. Kwok, F.M. Chiussi, “Architecture, performance and implementation of the tandem banyan fast packet switch”, IEEE J. on Selected Areas in Commun., Vol. 9, No. 8, Oct. 1991, pp. 1173-1193. [Uru91] S. Urushidani, “A high performance self-routing switch for broadband ISDN”, IEEE J. on Selected Areas in Commun., Vol. 9, No. 8, Oct. 1991, pp. 1194-1204. [Wid91] I. Widjaja, “Tandem banyan switching fabric with dilation”, Electronics Letters, Vol. 27, No. 19, Sept. 1991, pp.1770-1772. [Yeh87] Y.S. Yeh, M.G. Hluchyj, A.S. Acampora, “The knockout switch: a simple, modular architec- ture for high-performance packet switching”, IEEE J. on Selected Areas in Commun., Vol. SAC-5, No. 8, Oct. 1987, pp. 1274-1283. [Zar93a] R. Zarour, H.T. Mouftah, “Bridged shuffle-exchange network: a high performance self- routing ATM switch”, Proc. of ICC 93, Geneva, CH, June 1993, pp. 696-700. [Zar93b] R. Zarour, H.T. Mouftah, “The closed bridged shuffle-exchange network: a high perfor- mance self-routing ATM switch”, Proc. of GLOBECOM 93, Houston, TX, Nov. 1993, pp. 1164-1168. defl_net Page 389 Tuesday, November 18, 1997 4:14 pm 390 ATM Switching with Arbitrary-Depth Blocking Networks 9.8. Problems 9.1 Find the routing algorithm for an ATM switch using deflection routing derived from the Rerouting switch. The interconnection network of this switch is built cascading Baseline networks rather than reverse SW-banyan networks with last and first stages of two cascaded networks merged, as in Rerouting. 9.2 Derive the modification to be applied to the analytical models developed in Section 9.4 to account for the availability of multiple planes. 9.3 Use the models derived in Problem 9.2 to compute the packet loss probability of different switch architectures and verify how the analytical results match those given by computer simulation reported in Figure 9.45 and Table 9.2. 9.4 Extend the analytical model of Shuffleout to account for the availability of bridges. 9.5 Extend the analytical model of Shuffle Self-Routing to account for the availability of bridges. 9.6 Verify that Equations 9.3, 9.4 and 9.6 of Shuffleout simplify into Equations 9.9 and 9.11 of Shuffle Self-Routing. 9.7 Find the minimum number of stages in the Shuffleout switch that makes null the packet loss probability in the interconnection network. 9.8 Repeat Problem 9.7 for the Rerouting switch. 9.9 Repeat Problem 9.7 for the Tandem Banyan switch. 16 16× defl_net Page 390 Tuesday, November 18, 1997 4:14 pm Appendix Synchronous Queues A characteristic common to all the queues considered here is their synchronous behavior, mean- ing that customers join and leave a queue only at discrete epochs nt that are integer multiples of the basic time interval t that we call a slot . Furthermore, starts and ends of service can only occur at slot boundaries. For the sake of convenience we adopt the slot dura- tion as the basic time unit by expressing all the time measures in slots, so that state transitions can take place only at times n . Unless specified otherwise the queue discipline is assumed to be first-in–first-out (FIFO). The main random variables characterizing the queue are: • A : arrival size , that is number of service requests offered to the queue in a given time period; • W : waiting line size , that is number of customers in the queue waiting for the server avail- ability; • Q : queue size , that is total number of customers in the queue; • θ : service time , that is amount of service requested to the queue by the customer; • η : waiting time , that is time spent in the queue by a customer before its service starts; • δ : queueing time , that is the total time spent by a customer in the queue (waiting time + ser- vice time). In the following λ will denote the average arrival rate to the queue, which for a synchro- nous queue will be indicated by p expressing the probability that a service request is received in a slot by the queue. Two other parameters specifying the behavior of a queue other than the moments of the above random variables can be defined: • ρ : server utilization factor , that is the time fraction in which each server in the queue is busy; • π : loss probability , that is probability that a new customer is not accepted by the queue. n 12…,,=() n 12…,,=() This document was created with FrameMaker 4.0.4 app_que Page 391 Monday, November 10, 1997 8:55 pm Switching Theory: Architecture and Performance in Broadband ATM Networks Achille Pattavina Copyright © 1998 John Wiley & Sons Ltd ISBNs: 0-471-96338-0 (Hardback); 0-470-84191-5 (Electronic) 392 Synchronous Queues A.1. Synchronous Single-server Queues In this section synchronous queues with one server are studied. Queues with deterministic ser- vice time are examined first, in the case of both Poisson and geometric arrival processes. Then queues with general distribution of the service time are considered with infinite or finite wait- ing line. A.1.1. The M / D /1 queue We are interested here in the evaluation of the synchronous queue in which the cus- tomer arrivals occur only at discrete time epochs and the arrival process is Poisson. We are going to show that this queueing system has a close relationship with the ( asynchronous ) in which arrivals and starts of service can take place at any epoch of a continuous time axis. We assume that a queue is asynchronous if not specified otherwise. Since the study of the queue relies on the analysis of an queue (see, e.g. [Gro85]), we will briefly examine this latter queue. A.1.1.1. The asynchronous M/G/1 queue In an queue the customers join the queue according to a Poisson process with aver- age arrival rate λ and the service times are independent and identically distributed (IID) with an arbitrary probability distribution. Although in general such a queue is not a Markov process, it is possible to identify a set of “renewal” epochs in which the Markov property of the system holds. Through this technique an imbedded Markov chain can be identified that enables us to study the properties characterizing the system at these epochs. These renewal epochs are the times at which customers complete the service in the queue and thus leave the system. The number of customers left behind by the n -th departing customer who leaves the system at epoch n is then described by (A.1) in which is the number of arrivals during the service time of the n -th customer. The evolution of the system can be described by defining: • the transition probability matrix in which ; • the distribution of arrivals in a service time We assume that a steady state is achievable (the necessary conditions are specified in any queueing theory book, see e.g. [Gro85]) and thus omit the index n , so that MD1⁄⁄ MD1⁄⁄ MD1⁄⁄ MG1⁄⁄ MG1⁄⁄ Q n n 0>() Q n max 0 Q n 1– 1–,{}A n += A n p n p ij, n []= p ij, n Pr Q n jQ n 1– i==[]= a i n Pr A n i=[]= app_que Page 392 Monday, November 10, 1997 8:55 pm 393 The state probability vector at departure epochs , in which , is then given by or equivalently (A.2) It can be shown that the steady-state probability distribution of the queue size obtained through Equation A.2 together with the boundary condition at the departure epochs is the same at any arbitrary time epoch (see [Gro85]). Thus, in particular, also gives the probability distribution we are interested in, that is at customer arrival epochs. Let us define now the probability generating function (PGF) of the queue size Q and of the customer arrivals A After some algebraic manipulation, including application of L’Hôpital’s rule, and recalling that , , where , we finally obtain the Pollaczek– Khinchin (P–K) transform equation (A.3) The average number of customers in the system is then given by , which after some algebraic computations results in the well-known Pollaczek–Khinchin (P–K) mean- value formula p a 0 a 1 a 2 … a 0 a 1 a 2 … 0 a 0 a 1 … 00a 0 … . . . … = q q i []= q i Pr Qi=[]= qqp= q i q 0 a i q j a ij– 1+ j 1= i 1+ ∑ += i 0≥() q Σ i q i 1= q Π z() Π z() q i z i i 0= ∞ ∑ = z 1≤() Az() a i z i i 0= ∞ ∑ = z 1≤() Π 1() 1= A 1() 1= A' 1() ρ= ρλE θ[]= Π z() 1 ρ–()1 z–()Az() Az() z– = EQ[] Π' 1() EQ[] ρ λ 2 E θ 2 [] 21 ρ–() += app_que Page 393 Monday, November 10, 1997 8:55 pm [...]... distributions for one line with Poisson input, general holding times, and various service orders”, Bell System Tech J.,Vol 42, March 1963, pp 487-503 book_all_IX Page 409 Tuesday, November 18, 1997 4:13 pm Switching Theory: Architecture and Performance in Broadband ATM Networks Achille Pattavina Copyright © 1998 John Wiley & Sons Ltd ISBNs: 0-471-96338-0 (Hardback); 0-470-84191-5 (Electronic) Index A acknowledgment... 131, 152 Clos theorem 129 CM sequence 115, 121, 293 combinatorial power 73 combined input-output queueing 212, 241, 275, 283, 284, 315, 332, 333 combined input-shared queueing 283, 324, 325, 332 combined shared-output queueing 283, 317 combiner 60, 103 , 107 , 144, 150, 172, 204, 326 common channel signalling 8 communication services 1 ABR 17 burstiness factor 3 capacities 2 CBR 16 UBR 17 VBR 17 concentration... correspondent PGF Π ( z ) In particular, by differentiating Π ( z ) with respect to z and taking the limit as z → 1 , we obtain the average number of customers in the queue, which immediately gives the average time spent in the queue E [ δ ] , that is E [ Q] p E [ δ ] = = -p 2 ( 1 – p) It is very interesting but not surprising that the average queueing time in the S-ES M ⁄ D ⁄ 1 queue... number of customer in the system is again given by Equation A.3 in which now ∞ A ( z) = ∑ ( 1 – p + pz) θi i i=0 By applying twice L’Hôpital’s rule and considering that A' ( 1 ) = pE [ θ ] = ρ 2 A'' ( 1 ) = p E [ θ ( θ – 1 ) ] we finally obtain 2 p E [ θ ( θ – 1) ] E [ Q ] = pE [ θ ] + -2 ( 1 – pE [ θ ] ) The average queueing time and waiting time are obtained applying Little’s formula:... connection set 100 complete 100 incomplete 100 size 100 constrained reachability property 70, 137 contention cycle 256 contention elements 259 contention resolution 229, 235, 243, 284, 316 correlated traffic 221, 276, 333 book_all_IX Page 411 Tuesday, November 18, 1997 4:13 pm Index 411 cost function 62, 109 , 119, 120, 121, 123, 136, 142, 148, 152 cost index 55, 60, 61, 85, 94, 100 , 102 , 106 , 117, 128,... BB integrated transport 10 NB integrated access 7 segregated transport 7 network permutation 55, 64 non-blocking network 53, 54, 63, 73, 91, 116, 127, 128, 129, 130, 136, 139, 143, 144, 150, 153 non-blocking networks multiple-queueing 281 single-queueing 227 non-FIFO 251 non-uniform traffic 222, 276, 333, 388 normalized utilization factor 110 O odd-even merge sorting 76, 83, 86 Ofman theorem 97, 107 ... = 1, k k k≤C j > 1, k ≤ C k>C The probability s k that the tagged customer arrives in the queue so that k customers in total compete for the servers is obtained considering the current queue status and all the possible combination of arrivals resulting in k customers in the system waiting for service That is min { k + C – 1, B } 1 s k = ( 1 ≤ k < B) qi Γ 1–π i=0 B N–1 1 s = ... ⁄ B queue, in which the queue first accepts as many customer as possible, so as to occupy the B locations in the waiting line and the C server positions, then moves C of the customers (if available) to the servers and stores the remaining customers (up to B) in the queue The system evolution is described by Q n = min { max { 0, Q n – 1 – C + A n } , B } app_que Page 406 Monday, November 10, 1997 8:55... non-blocking 54 single queueing 164 strict-sense non-blocking 54 taxonomy 165 wide-sense non-blocking 54 internal conflicts 117, 160, 168, 177, 227, 235, 259, 317 internal speed-up 324, 333, 339 interstage bridging 355, 384 IOQ Three-Phase switch 287, 288, 292 ISDN 7 B channel 8 D channel 8 H channel 8 isomorphic networks 58, 73, 213 isomorphism 58, 72, 149 K Knockout switch 259 K-non-blocking network... D ⁄ C ⁄ B queue, first removes the customers in service (at most C) and then stores the new customers in the currently idle positions of the queue The system evolution is described by Q n = min { max { 0, Q n – 1 – C } + A n, B } in which Q n and A n represent the customers in the queue and the new customers requesting service, respectively, at the beginning of slot n Thus the balance equations for . – Li– Geom L()D 1 B o ⁄⁄⁄ p q 0.5= p q 0.99= C 9= 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 1 10 100 Output queue - C=9 Cell loss probability, π q p q =0.5. FrameMaker 4.0.4 app_que Page 391 Monday, November 10, 1997 8:55 pm Switching Theory: Architecture and Performance in Broadband ATM Networks Achille Pattavina Copyright © 1998 John Wiley & Sons Ltd ISBNs:. pm 390 ATM Switching with Arbitrary-Depth Blocking Networks 9.8. Problems 9.1 Find the routing algorithm for an ATM switch using deflection routing derived from the Rerouting switch. The interconnection