Switching Theory: Architecture and Performance in Broadband ATM Networks phần 4 docx

116 Rearrangeable Networks Equation 3.11 enables us to write the following inequalities: (3.13) (3.14) which applied into Equation 3.12 give the result . Therefore the assumption that a–b and a'–b' share the interstage link at stage k can never be verified and the two I/O paths are link independent, so proving the non-blocking condition of the Omega network for a CM sequence. Let us consider now the case of a CCM sequence, in which . Now due to the cyclic compactness (modulo N) of the non-empty elements in the sequence, Equation 3.12 becomes (3.15) The inequality to be used now for the first member is (3.16) Equations 3.14 and 3.16 used in Equation 3.15 lead to the same inequality so that the non-blocking condition of the Omega network is finally proven for a CCM sequence. ❏ It is worth observing that this non-blocking condition applies also to the n-cube network which performs the same permutations as the Omega network. Figure 3.22. Interstage link labels in an Omega network 01010111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0101011101010111 01010111 01010111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 a' a– a' n 1– …a' 0 a n 1– …a 0 – 2 nk– a' n 1– …a' nk– a n 1– …a nk– –()2 nk– ≥== b' b– b' n 1– …b' 0 b n 1– …b 0 – b' nk– 1– …b' 0 b nk– 1– …b 0 – 2 nk– 1–≤== 01–≤ a' a< a' a–()modNb' b–≤ a' a–()modNNa' a–+ 1a' n 1– …a' 0 0a n 1– …a 0 –== 2 nk– 1a' n 1– …a' nk– 0a n 1– …a nk– –()2 nk– ≥= 01–≤ net_th_rear Page 116 Tuesday, November 18, 1997 4:37 pm Partial-connection Multistage Networks 117 Now we are able to construct a fully self-routing rearrangeable network, using the concept introduced so far. A sorting network is able to sort up to N packets received in an arbi- trary configuration and its output turns out to be a CM sequence, either increasing or decreasing, depending of the sorting order of the network. Thus, based on the preceding theo- rem, the cascade of a sorting network and an Omega network is a non-blocking structure, that based on the operation of the sorting elements and routing elements in the two networks is self-routing at all stages. As far as the sorting network is concerned we will always refer to the Batcher bitonic sort- ing operations described in Section 2.3.2. In fact having the same “length” for all the I/O paths through the network is such an important feature for easing the packet alignment for comparison purposes in each stage that the non-minimum number of sorting elements of the structure becomes irrelevant. Figure 3.23 shows the block scheme of a non-blocking network, in which sorting and routing functions are implemented by a Batcher network and an n-cube (or Omega) network. This non-blocking network includes an overall number s of sorting/ routing stages: with a total number of sorting/switching elements equal to and a cost index Thus a Batcher–banyan network includes 20 stages with a total number of 320 ele- ments, whereas 33,280 elements compose a 1,024 × 1,024 network distributed in 55 stages. We point out that such a Batcher-banyan network guarantees the absence of internal conflicts for interstage links between different I/O paths. Thus, in a packet environment we have to guarantee that the packet configuration offered to the rearrangeable network is free from exter- nal conflicts, that is each network outlet is addressed by at most one of the packets received at the network inputs. An example of switching operated by a Batcher-banyan network for without external conflicts is given in Figure 3.24. Figure 3.23. Depth of interconnection network based on sorting-routing NN× s 1 2 N 2 log N 2 log 1+()N 2 log+ 1 2 N 2 2 log 3 2 N 2 log+== sN2⁄() CN N 2 2 log 3 N 2 log+[]= 32 32× Batcher sorting network Banyan routing network a 0 a 1 a N-2 a N-1 c 0 c 1 c N-2 c N-1 n(n+1)/2 n N 8= net_th_rear Page 117 Tuesday, November 18, 1997 4:37 pm Partial-connection Multistage Networks 119 environment, in which we are more interested in view of ATM applications, the rate on the network inlets and outlets is usually the same, given that we provide a queueing capability in the output multiplexers to store K packets that can be received at the same time. As in the case of rearrangeable networks without output speed-up, the sorting network is usually implemented as a Batcher bitonic sorting network. Unless specified otherwise, each packet is given a self-routing tag that is the juxtaposition of the network destination address (DA) and of a routing index (RI). Both fields RI and DA carry an integer, the former in the interval and coded by bits, the latter in the interval and coded by bits. Packets with the same DA are given different RIs. The most simple implementation (implementation a) of the routing network is an banyan structure where (Figure 3.26). So, when K is a power of 2, . In such a banyan network, only the first N out of inlets are used. Owing to the EGS connection pattern between the banyan network outlets and the N multiplexers each with K inlets, only the first outlets of the routing network are used. Packet self-routing in this routing network can still be accomplished given that each packet is preceded by a self- routing tag (RI,DA), that is the juxtaposition of the routing index RI (the most significant bits of the routing tag) and destination address (or network outlet) DA (the least significant bits of the routing tag). The packets with the same DA are at most K and all carry a different RI. It is rather easy to verify that such cell tagging provides the desired conflict-free self-routing in the banyan network, given that it receives a cyclically compact and monotone (CCM) sequence of packets (see Section 3.2.2) that is guaranteed by the sorting network. Owing to the EGS pat- tern up to K packets can be received by the generic multiplexer i , each packet carrying a different RI coupled with , and therefore the overall network is K- rearrangeable. The cost function of such a K-rearrangeable network is Figure 3.25. General structure of K-rearrangeable network 0 N-1 K K Multi plexer Multi plexer 0 N-1 N X NKN X N Sorting network Routing network K X 1 0 K 1–,[] k' K' 2 log= 0 N 1–,[] nN 2 log= NK' NK'× K' 2 K 2 log = K' K= NK' NK i 0 … N 1–,,= DA i= C 4 N 2 nn 1+() 2 4 NK' 2 nk'+()+ NN 2 2 log 2K' 1+()N 2 log 2K' K' 2 log++[]== net_th_rear Page 119 Tuesday, November 18, 1997 4:37 pm Partial-connection Multistage Networks 121 each. The conceptual structure of an interconnection network of Figure 3.28 is thus obtained. It includes a Batcher bitonic sorting network , K n-cube banyan net- works , each feeding the N multiplexers, and N expanders , the j-th of which interfaces the outlet j of the sorting network with the inlet j of the K banyan networks. It can be shown that if the expanders are implemented as binary trees with k’ stages of switch- ing elements (analogously to the crossbar binary tree described in Section 2.1.2), then the interconnection network is K-rearrangeable and fully self-routing by means of a self-routing tag (RI,DA) preceding each packet. Field RI would be used in the k'-stage binary trees and field DA in the banyan networks. In fact the packets addressing the same banyan network emerge on adjacent sorting network outlets (they have the same RI) and their addresses are all different (packets with the same DA have been given different RIs). Therefore each banyan network will receive a set of packets on adjacent lines with increasing DAs, that is a CM sequence, by virtue of the operation performed by the upstream sorting network. The cost function of this implementation of a K-rearrangeable network is The network of Figure 3.28 can be simplified for an arbitrary integer value of K into the structure of Figure 3.29 (implementation c'), by replacing the expanders with an EGS pattern to interconnect the sorting network with the K banyan networks. In this example, K is assumed to be a power of two, so that the last inlets are idle in each banyan network. If (i integer) then the idle inlets of the banyan networks are still the last ones, but their number is not the same in all the networks. In this implementation the self-routing tag of each packet only includes the field DA, so that at most K adjacent packets with the same DA can emerge from the sorting network. Theorem. The multistage interconnection network of Figure 3.29 is K-rearrangeable. Proof. For the proof we will refer to an ATM packet-switching environment in which the information units are the packets, even if the proof holds for circuit switching as well. In gen- Figure 3.27. Implementation b of K-rearrangeable network 0 N-1 0 N-1 1 0 K-1 0 K-1 0 K-1 0 (N-1)K'+K-1 (N-1)K' K-1 K' K'+K-1 K X 1NK' X NK' NN× NN× NN× NN× 1 K× 12× C 4 N 2 nn 1+() 2 2 K' 1–()N 4K N 2 n++NN 2 2 log 2K 1+()N 2 log 2K' 2–++[]== NNK⁄– K 2 i ≠ net_th_rear Page 121 Tuesday, November 18, 1997 4:37 pm Bounds on the Network Cost Function 123 free from internal conflicts, and thus the overall network is K-rearrangeable since it can switch up to K packets to the same network. ❏ For example, if , , the sequence of packets (3,0,4,3,4,6,e,3) offered to the network (e means empty packet) is sorted as (0,3,3,3,4,4,6,e) and the banyan networks #1, #2 and #3 receive the CM sequences (0,3,6), (3,4,e) and (3,4), respectively. It is therefore clear that such implementation c' does not require any additional routing index other than the des- tination address DA to be fully self-routing. The cost function of this K-rearrangeable network is which is thus the smallest among the three different solutions presented. 3.3. Bounds on the Network Cost Function The existence of upper bounds on the cost function of rearrangeable multistage networks is now investigated, where the network cost is again only determined by the number of cross- points required in the network (for simplicity only squared networks are considered with ). We have already shown that the cost function is of the type with : in fact the cost function of both the Benes and Waksman networks is Pippenger [Pip78] proved that using basic matrices, rather than matrices as in the Benes and Waksman network, gives a a slight reduction of the coefficient α with a cost function equal to (3.17) where the equality has been used. The same asymptotic bound was earlier reported in [Ben65]. The cost function of various rearrangeable networks for a wide range of network sizes is shown in Figure 3.30. The cost of the Benes and Waksman networks is basically the smallest one for any network size and their value is practically the same as the bound provided by Pip- penger (Equation 3.17). The three-stage Slepian–Duguid network is characterized by a cost very close to the minimum for small network sizes, say up to , whereas it becomes more expensive than the previous ones for larger network sizes. The Batcher-banyan network, which is even more expensive than the crossbar network for , has a lower cost than the Slepian–Duguid network for . N 8= K 3= C 4 N 2 nn 1+() 2 4K N 2 n+ NN 2 2 log 2K 1+()N 2 log+[]== NN× N 2 n = αNN 2 log() β β 1= CNN,()4NN 2 log ON()+≤ 33× 22× CNN,()6NN 3 log ON N 2 log() 12⁄ ()+≤ 3.79NN 2 log ON N 2 log() 12⁄ ()+= N b log N 2 log() b 2 log()⁄= N 128= N 32≤ N 4096≥ net_th_rear Page 123 Tuesday, November 18, 1997 4:37 pm References 125 [Hui90] J.Y. Hui, Switching and Traffic Theory for Integrated Broadband Networks, Kluwer Academic Press, Norwell, MA, 1990. [Kim92] H.S. Kim, A. Leon-Garcia, “Nonblocking property of reverse banyan networks”, IEEE Trans. on Commun., Vol. 40, No. 3, Mar. 1992, pp. 472-476. [Law75] D.H. Lawrie, “Access and alignment of data in an array processor”, IEEE Trans. on Comput., Vol. C-24, No. 12, Dec. 1975, pp. 1145-1155. [Lea90] C T. Lea, “Multi-log 2 N networks and their applications in high-speed electronic and pho- tonic switching systems, IEEE Trans. on Commun., Vol. 38, No. 10, Oct. 1990, pp. 1740- 1749. [Lea91] C T. Lea, D J. Shyy, “Tradeoff of horizontal decomposition versus vertical stacking in rear- rangeable nonblocking networks”, IEEE Trans. on Commun., Vol. 39, No. 6, June 1991, pp. 899-904. [Lee88] T.T. Lee, “Nonblocking copy networks for multicast packet switching”, IEEE Trans. on Commun., Vol. 6, No. 9, Dec. 1988, pp. 1455-1467. [Lie89] S.C. Liew, K.W. Lu, “A three-stage architecture for very large packet switches”, Int. J. of Digital and Analog Cabled Systems, Vol. 2, No. 4, Oct Dec. 1989, pp. 303-316. [Nar88] M.J. Narasimha, “The Batcher-banyan self-routing network: universality and simplifica- tion”, IEEE Trans. on Commun., Vol. 36, No. 10, Oct. 1988, pp. 1175-1178. [Ofm67] J.P. Ofman, “A universal automaton”, Trans. Moscow Mathematical Society, Vol. 14, 1965; trans- lation published by American Mathematical Society, Providence, RI, 1967, pp. 200-215. [Opf71] D.C. Opferman, N.T. Tsao-Wu, “On a class of rearrangeable switching networks - Part I: control algorithms”, Bell System Tech. J., Vol. 50, No 5, May-June 1971, pp. 1579-1600. [Par80] D.S. Parker, “Notes on shuffle/exchange-type switching networks”, IEEE Trans. on Com- put., Vol C-29, Mar. 1980, No. 3, pp. 213-222. [Pau62] M.C. Paull, “Reswitching of connection networks”, Bell System Tech. J., Vol. 41, No. 3, May 1962, pp. 833-855. [Pip78] N. Pippenger, “On rearrangeable and non-blocking switching networks”, J. of Comput. and System Science, Vol. 17, No. 4, Sept. 1978, pp.145-162. [Rag87] C.S. Raghavendra, A. Varma, “Rearrangeability of the five-stage shuffle/exchange network for N=8”, IEEE Trans. on Commun., Vol. 35, No. 8, Aug. 198, pp. 808-812. [Sha50] C.E. Shannon, “Memory requirements in a telephone exchange”, Bell System Tech. J., Vol. 29, July 1950, pp. 343-349. [Sle52] D. Slepian, “Two theorems on a particular crossbar switching network”, unpublished manu- script, 1952. [Sov83] F. Sovis, “Uniform theory of the shuffle-exchange type permutation networks”, Proc. of 10- th Annual Symp. on Comput. Architecture, 1983, pp.185-191. [Sto71] H.S. Stone, “Parallel processing with the perfect shuffle”, IEEE Trans on Comput., Vol. C-20, No. 2, Feb. 1971, pp.153-161. [Var88] A. Varma, C.S. Raghavendra, “Rearrangeability of multistage shuffle/exchange networks”, IEEE Trans. on Commun., Vol. 36, No. 10, Oct. 1988, pp. 1138-1147. [Wak68] A. Waksman, “A permutation network”, J. of ACM, Vol. 15, No. 1, Jan, 1968, pp. 159-163. [Wu81] C-L. Wu, T-Y. Feng, “The universality of the shuffle-exchange network”, IEEE Trans. on Comput., Vol. C-30, No. 5, May 1981, pp. 324-332. net_th_rear Page 125 Tuesday, November 18, 1997 4:37 pm 126 Rearrangeable Networks 3.5. Problems 3.1 Without relying on the formal arguments shown in the proof of the Slepian–Duguid theorem, prove by simply using Figure 3.3 that the chain of symbols in the Paull matrix never ends on row i and column j. 3.2 By relying on the banyan network properties, prove that a Baseline EBN with additional stages is rearrangeable. 3.3 Find a network state that sets up the permutation 0-4, 1-12, 2-5, 3-8, 4-13, 5-0, 6-6, 7-15, 8-1, 9-7, 10-10, 11-2, 12-14, 13-3, 14-9, 15-11 in a Benes network with ; determine the number of different network states that realize the requested permutation. 3.4 Repeat Problem 3.3 for a Waksman network. 3.5 Count the number of different network states that enable to set up the incomplete connection set for in a Benes network with . 3.6 Repeat Problem 3.5 for a Waksman network. 3.7 Compute the cost of a rearrangeable VR/HE banyan network with m additional stages in which the replication factor is applied to the central subnetworks of size with . 3.8 Draw the channel graph for an RBN with and as well as for a VR/HE banyan network with , and by determining whether the necessary condition for network rearrangeability based on the NUF parameter is satisfied. 3.9 Provide an intuitive explanation based on the channel graph and associated NUF values for the minor asymptotic cost of a rearrangeable network based on the HE technique rather than on the VR technique. 3.10 Prove the non-blocking condition of an n-cube network for a CCM sequence of size N using the bitonic merging principle. Extend the proof to CCM sequences of arbitrary size . 3.11 Draw a four-stage interconnection network with interstage FC pattern in which the first stage includes 25 splitters and the last stage 16 combiners by determining if such network is rearrangeable. n 1– N 16= ii8+()– i 01… 7,, ,= N 16= mn1–≤() 2 nm–()2⁄ N 2 mh– ⁄ N 2 mh– ⁄× 0 hm≤≤ N 32= K 6= N 32= m 1= K 4= mN≤ 14× 31× net_th_rear Page 126 Tuesday, November 18, 1997 4:37 pm Chapter 4 Non-blocking Networks The class of strict-sense non-blocking networks is here investigated, that is those networks in which it is always possible to set up a new connection between an idle inlet and an idle outlet independently of the network permutation at the set-up time. As with rearrangeable networks described in Chapter 3, the class of non-blocking networks will be described starting from the basic properties discovered more than thirty years ago (consider the Clos network) and going through all the most recent findings on network non-blocking mainly referred to banyan- based interconnection networks. Section 4.1 describes three-stage non-blocking networks with interstage full connection (FC) and the recursive application of this principle to building non-blocking networks with an odd number of stages. Networks with partial connection (PC) having the property of non- blocking are investigated in Section 4.2, whereas Section 4.3 provides a comparison of the dif- ferent structures of partially connected non-blocking networks. Bounds on the network cost function are finally discussed in Section 4.4. 4.1. Full-connection Multistage Networks We investigate here how the basic FC network including two or three stages of small crossbar matrices can be made non-blocking. The study is then extended to networks built by recursive construction and thus including more than three stages. 4.1.1. Two-stage network The model of two-stage FC network, represented in Figure 2.11, includes matrices at the first stage and matrices at the second stage.This network clearly has full acces- sibility, but is blocking at the same time. In fact, if we select a couple of arbitrary matrices at r 1 nr 2 × r 2 r 1 m× This document was created with FrameMaker 4.0.4 net_th_snb Page 127 Tuesday, November 18, 1997 4:32 pm Switching Theory: Architecture and Performance in Broadband ATM Networks Achille Pattavina Copyright © 1998 John Wiley & Sons Ltd ISBNs: 0-471-96338-0 (Hardback); 0-470-84191-5 (Electronic) 128 Non-blocking Networks the first and second stage, say and , no more than one connection between the n inlets of and the m outlets of can be set up at a given time. Since this limit is due to the single link between matrices, a non-blocking two-stage full-connection network is then easily obtained by properly “dilating” the interstage connection pattern, that is by providing d links between any couple of matrices in the two stages (Figure 4.1). Also such an FC network is a subcase of an EGS network with . The minimum link dilation factor required in a non-blocking network is simply given by since no more than connections can be set up between and at the same time. The network cost for a two-stage non-blocking network is apparently d times the cost of a non-dilated two-stage network. In the case of a squared network using the relation , we obtain a cost index that is the two-stage non-blocking network doubles the crossbar network cost. Thus, the feature of smaller matrices in a two-stage non-blocking FC network compared to a single crossbar network is paid by doubling the cost index, independent of the value selected for the parameter n . 4.1.2. Three-stage network The general scheme of a three-stage network is given in Figure 4.2, in which, as usual, n and m denote the number of inlets and outlets of the first- ( A ) and third- ( C ) stage matrices, respectively. Adopting three stages in a multistage network, compared to a two-stage arrange- ment, introduces a very important feature: different I/O paths are available between any couple of matrices and each engaging a different matrix in the second stage ( B ). Two I/ Figure 4.1. FC two-stage dilated network A i B j A i B j m i dr i 1+ = i 1 … s 1–,,=() d min nm,()= min nm,() A i B j NM n, m r 1 , r 2 r====()Nrn= C ndr 2 r 1 dr 1 mr 2 + 2n 2 r 2 2N 2 === #1 #r 1 #1 #r 2 MN d n x dr 2 dr 1 x m n x dr 2 dr 1 x m AB A i C j net_th_snb Page 128 Tuesday, November 18, 1997 4:32 pm 130 Non-blocking Networks The network cost for a given N thus depends on the number of first-stage matrices, that is on the number of inlets per first-stage matrix since . By taking the first derivative of C with respect to n and setting it to 0, we easily find the solution (4.2) which thus provides the minimum cost of the three-stage SNB network, i.e. (4.3) Unlike a two-stage network, a three-stage SNB network can become cheaper than a cross- bar (one-stage) network. This event occurs for a minimum cost three-stage network when the number of network inlets N satisfies the condition (as is easily obtained by equating the cost of the two networks). Interestingly enough, even only inlets are enough to have a three-stage network cheaper than the crossbar one. By comparing Equations 4.3 and 3.2, giving the cost of an SNB and RNB three-stage network respectively, it is noted that the cost of a non-blocking network is about twice that of a rearrangeable network. 4.1.3. Recursive network construction Networks with more than three stages can be built by iterating the basic three stage construc- tion. Clos showed [Clo53] that a five-stage strict-sense non-blocking network can be recursively built starting from the basic three-stage non-blocking network by designing each matrix of the second-stage as a non-blocking three-stage network. The recursion, which can Figure 4.3. Worst case occupancy in a three-stage network 1 2 n-1 1 2 m-1 n 1 A m 1 C r 1 Nnr 1 = n N 2 ≅ C 42N 3 2 4N–= N 222+> N 24= net_th_snb Page 130 Tuesday, November 18, 1997 4:32 pm [...]... number of inlets in the downstream SEs net_th_snb Page 148 Tuesday, November 18, 1997 4: 32 pm 148 Non-blocking Networks Table 4. 5 Splitter fanout of a non-blocking EGS network N = 8 16 32 64 128 256 512 10 24 s = 1 4 8 16 32 64 128 256 512 2 4 8 16 32 64 128 256 512 3 3 6 12 24 48 96 192 3 84 4 3 5 10 20 40 80 160 320 5 3 4 7 14 28 56 112 2 24 6 4 6 11 22 44 88 176 7 4 5 8 15 30 60 120 8 5 7 12 23 46 92... given in Figure 4. 11 showing the link dilation factor of each stage 2 4 2 2 4 4 2 2 4 8 4 2 2 4 8 8 4 2 2 4 8 16 8 4 N=16 N=32 N= 64 N=128 2 N=256 stage: 1 2 3 4 5 6 7 8 Figure 4. 11 Dilation factor in non-blocking PDBN 4. 2 .4 EGS networks A different approach to obtain a strict-sense non-blocking network that still relies on the use of very simple 2 × 2 SEs has been found recently by Richards relying on... non-blocking or rearrangeable sw_mod Page 157 Tuesday, November 18, 1997 4: 31 pm Switching Theory: Architecture and Performance in Broadband ATM Networks Achille Pattavina Copyright © 1998 John Wiley & Sons Ltd ISBNs: 0 -47 1-96338-0 (Hardback); 0 -47 0- 841 91-5 (Electronic) Chapter 5 The ATM Switch Model The B-ISDN envisioned by ITU-T is expected to support a heterogeneous set of narrowband and broadband services... cost function C 2t + 1 given in Equations 4. 6, 4. 7, 4. 8 and found in Problem 4. 2 for the fact that the minimum cost of the recursive Clos network is given by a number of stages that increases with the network size N 4. 4 Compute the cost of a five-stage non-blocking minimum-cost Clos network and derive Equation 4. 4 providing the values for n 1 and n 2 in a minimum-cost network 4. 5 Derive the expression... tagged link of stage 1 is shared by one conflicting I/O path originating from the other SE inlet (the inlet 1), the tagged link of stage 2 is shared by two other conflicting paths originated from inlets not accounted for (the inlets 2 and 3), and the tagged link of stage ( n – 2 ) ⁄ 2 (the last ( n – 2) ⁄ 2 – 1 tagged link of the upper inlet subtree) is shared by 2 conflicting paths originated from inlets... I/O path (0-0 in Figure 4. 14) can be counted with reference to only one generic tagged path originating at stage 1 and terminating at stage s In this case the number of 1 Here the buddy property, originally defined for a network including only 2 × 2 SEs, must be applied by straightforward extension considering that the two adjacent stages (0 and 1, s and s + 1 ) interface to each other having upstream... non-blocking) For example for N = 512 a fanout F = 8 provides a non-blocking EGS network, whereas the better result given by Table 4. 5 is F = 9 A useful insight in the equivalence between EGS networks and other networks can be obtained by Figures 4. 15 and 4. 16, showing an EGS and a VR/HE banyan network 8 × 8 net_th_snb Page 151 Tuesday, November 18, 1997 4: 32 pm 151 Comparison of Non-blocking Networks. .. rearrangeable and non-blocking switching networks , J of Computer and System Science,Vol 17, No 4, Sep 1978, pp. 145 -162 [Ric93] G.W Richards, “Theoretical aspects of multi-stage networks for broadband networks , Tutorial presentation at INFOCOM 93, San Francisco, Apr.-May 1993 [Shy91] D.-J Shyy, C.-T Lea, “Log2(N,m,p) strictly nonblocking networks , IEEE Trans on Commun.,Vol 39, No 10, Oct 1991, pp 1502-1510 4. 6... × N includes N splitters 1 × F , s stages of NF ⁄ 2 SEs of size 2 × 2 and N combiners F × 1 , mutually interconnected by EGS patterns (see Figure 4. 12) We say that such a network has s + 2 stages where switching takes place, numbered 0 through s + 1 , so that splitters and combiners accomplish the switching in stage 0 and s + 1 , respectively, whereas the traditional switching net_th_snb Page 146 Tuesday,... links outgoing from stage 1 are shared by the tagged inlet and by only one other inlet (inlet 1 in our example), which, upon becoming busy, makes unavailable m–1 2 paths for the I/O pair 0-0 (see also the channel graph of the example) The four tagged links of the tagged paths outgoing from stage 2 are shared by four network inlets in total, owing to the buddy property In fact the two SEs originating . traditional switching Figure 4. 11. Dilation factor in non-blocking PDBN 64 64 K d 8= C N 2 N 2 log 2 2 n 2 ⋅ 2 = N 2 N 2 log K d u= N 16 256–= 244 2 242 248 42 248 842 248 16 842 N=16 N=32 N= 64 N=128 N=256 12 345 678stage: 22× NN× 1. 1997 4: 32 pm Switching Theory: Architecture and Performance in Broadband ATM Networks Achille Pattavina Copyright © 1998 John Wiley & Sons Ltd ISBNs: 0 -47 1-96338-0 (Hardback); 0 -47 0- 841 91-5. originated from inlets not accounted for (the inlets 2 and 3), and the tagged link of stage (the last tagged link of the upper inlet subtree) is shared by conflicting paths originated from inlets