Broadband Circuits for Optical Fiber Communication phần 5 potx

168 MAIN AMPLIFIERS For example, if the output rms noise voltage of an MA with 40-dB gain and 12-GHz noise bandwidth is 20 mV, we conclude that the available input-referred rms noise voltage is 20 mV/100 = 200 pV, the input-referred rms noise voltage is twice that, 2 x 200 pV = 400 pV, and the rms noise voltage of the source resistance is 98 pV; thus, the noise figure is 10 log(400 pV/98 PV)~ = 12.2 dB. Unfortunately, there is yet another difficulty that is related to the differential inputs of the MA. If we drive the amplifier single endedly as shown in Fig. 6.4, the noise voltage of the source resistance is that of a single 5042 resistor, the noise of the termination resistor at the other input counts as amplifier noise. However, if we drive the amplifier differentially, the noise voltage of the source ,resistance is that of two 5042 resistors. Thus, the differential noise figure is 3 dB lower than the single-ended noise figure. (The total noise power is the same, but the noise power due to the source resistance has doubled.) Most noise-figure test sets measure only the single-ended noise figure, and thus the noise figure specified in MA data sheets usually is the single-ended one. What about the outputs of a fully differential MA? Do we also have to distinguish between a single-ended and a differential measurement? Fortunately, there is almost no difference because the multistage topology, which typically is used for MAS, causes the noise voltages at the two outputs to be highly anticomelated (Vn.op = -u~~.oN). (Remember that the noise voltages at the two outputs of a differential TIA usually are not highly anticorrelated; cf. Section 5.1.4.) If we measure the differential rms output noise voltage of an MA, we find twice the single-ended output noise voltage, but we also have twice the gain; thus, the input-referred rms noise voltage and the noise figure remain the same. Power Penalty Now let's calculate the power penalty caused by the MA noise. The total mean-square noise current referred back to the input of the TIA can be written as - - - 2 - .2 2 in.arnp - 'n.TIA + (6.17) - - where i:,TIA is the familiar input-referred noise current of the TL4 and i:.MA is the noise of the MA referred all the way back to the input of the TIA. Thus, when adding our noisy MA to the receiver, the input-referred rms noise current goes up from to & and, according to Eq. (4.20), we need to increase the received optical power by the same amount to maintain a constant BER. Therefore, the power penalty due to the MA noise is (6.18) The noise of the MA referred back to the TIA input can be expressed in terms of the MA's noise figure F and the TIA's transimpedance RT. We start with the input-referred mean-square noise voltage of the MA, Remember that this noise voltage includes the noise voltage of the source resistance, u;,~, so we have - - MA SPECIFICATIONS 169 to subtract it out. Then, we divide this result by four to obtain the available input- referred mean-square noise voltage due to the MA only. Again dividing this result by the squared transimpedance, R;, is giving us the desired input-referred mean-square noise current. Finally, we can express the input-referred noise voltage in terms of the noise figure using Eq. (6.15): (6.19) Combining Eqs. (6.18) and (6.19), we find the power penalty due to the MA noise to be (F - 1) . V,.s (6.20) Solving this equation for F yields the maximum permissible noise figure (6.21) From this equation, we can conclude that a high transimpedance helps to relax the noise-figure requirements for the MA. Furthermore, a low-noise TIA also requires a low-noise MA to keep the power penalty low. Typical Values. Next, we calculate some typical numbers based on a 0.05-dB power penalty (PP = 1.0116), and a noise bandwidth BW,, = 1.2B. For a typical 2.5-Gb/s system (RT = 3 kQ, iim&A = 380 nA), we obtain the numerical value = 17.1 dB. 4 . (3 kS2)2 . (380 nA)' (49.0 PV)~ FI lf0.023 (6.22) And for a typical 1 0-Gb/s system ( RT = 1 kQ, iLm+IA = 1,400 nA), we get = 13.0dB. (6.23) 4.(1l~$2)~.(1,400nA)~ (98.0 PV)~ F 5 1 + 0.023 . - From a wireless designer's perspective, these noise figures are very large compared with what's typical for a low-noise amplifier (LNA). However, low noise figures are harder to achieve for a broadband amplifier and care must be taken to meet these numbers. 6.2.4 input Dynamic Range Definition. The input dynamic range of the MA describes the minimum and maxi- mum input signal for which the MA performs a useful function, for example, for which the BER is sufficiently low. The minimum input signal (lower end of the dynamic 170 MAIN AMPLIFIERS range) is given by the MA's sensitivity. Similar to the receiver sensitivity definition in Section 4.3, the MA sensitivity is the minimum peak-to-peak signal voltage at the input of the MA necessary to achieve a specified BER (g,ns = 4' @ BER). Because it is the available input-referred rms noise voltage, uLyhA,av, that adds to the input signal voltage, us, the sensitivity is given by gins = 2& . uThA,av. Expressed in terms of the input-referred rms noise voltage (using Eq. (6.13)), the MA sensitivity is Gins = Q * u;mhA, (6.24) and rewritten in terms of the noise figure (using Eq. (6.15)), it is Ugns = Q . Jq. (6.25) For example, given the input-referred rms noise voltage of 400 pV from the previous example and a required BER of lo-'*, the sensitivity of the MA is 2.8 mV. The definition of the maximum input signal (upper end of the dynamic range) depends on the type of amplifier. An AGC amplifier is supposed to operate linearly, and therefore the maximum input signal swing, I,(:, is reached when the amplifier starts to limit or distort otherwise. A commonly used criterion is the I-dB compression point, that is, the signal swing for which the gain drops by 1 dB below its small-signal value. In analog CATV/HFC applications, harmonic and intermodulation distortions are of great significance, and hence I,(! is defined such that these distortions remain small (cf. Section 4.8). Obviously, these definitions cannot be applied to an LA because it is operated in the nonlinear (limiting) regime on purpose. Thus for the LA, the maximum input signal swing, also called the input overload voltage, u$, is reached when the amplifier produces so much pulse-width distortion and jitter that the specified BER cannot be maintained. For example, in BJT implementations, a large input signal can cause the base-collector diodes to become forward biased, leading to such distortions [38]. Power Penalty Next, we find the power penalty caused by a finite MA sensitivity and then we determine the MA sensitivity required to keep this power penalty below a given value. We already know the power penalty due to the MA noise from Eq. (6.20), which we can easily convert into the power penalty due to the MA sensitivity by using Eq. (6.25). Assuming that the noise figure is much larger than one (F >> I), we find that (6.26) Solving this equation for reveals the required MA sensitivity This result has an interesting interpretation: the term after the square root is the input voltage swing into the MA when the receiver operates at the sensitivity limit, that is, MA SPECIFICATIONS 171 the quantity that we have called 4Lin in Eq. (6.3). Thus, the square-root term tells us how much smaller we have to make the MA sensitivity compared with the minimum input signal into the MA. For example, for a 0.05-dB power penalty (PP = 1.01 16), the MA sensitivity must be made 6.6~ smaller than the minimum input signal into the MA. Typical Values. Next, we calculate some typical MA sensitivity numbers based on a 0.05-dB power penalty (PP = 1.0116), a noise bandwidth BW, = 1.2B, and BER = (Q = 7.035). For a typical 2.5-Gb/s system (RT = 3 kS2, i?hA = 380nA), we obtain the numerical value t$& 5 7.035 . J0.023 .4 . (3 kS2)2 . (380nA)2 + (49.0 FV)~ ='2.5 mV. (6.28) And for a typical IO-Gb/s system (RT = 1 kS2, ir!IA = 1,40OnA), we get t$&s 5 7.035 .J0.023 .4 . (1 kS2)2 . (1,400 nA)2 + (98.0 PV)~ = 3. I mV. (6.29) The requirements for the upper end of the input dynamic range depend on the max- imum output signal from the TIA and can be several volts. A typical input dynamic range for an MA is t$Cns . e:, = 2m~. . .2~. (6.30) 6.2.5 Input Offset Voltage Definition. The input offset voltage, VOS, is the input voltage for which the output voltage of the MA becomes zero. If the bandwidth of the MA extends all the way down to DC, a DC input voltage can be applied and VOS is the voltage, which forces the output voltage to zero. However, if the gain rolls off at low frequencies (cf. Sec- tion 6.2.6), an AC signal must be applied to the input, and Vos is the amplitude of this signal that causes the output signal just to touch the zero level. Alternatively, if the input offset voltage is small, that is, if the offset voltage does not drive the amplifier into the compressive regime. we also can determine the input offset voltage by taking the output offset voltage and dividing iit by the midband voltage gain. A nonzero offset voltage in an LA results in a slice-level error, which in turn causes (i) more bit errors, because it becomes more likely that the noisy signal crosses the off-center slice level, and (ii) pulse-width distortions, because of the finite rise and fall times of the received signal. A small offset voltage in an AGC amplifier is less severe because it can be compensated at the output of the amplifier. In particular, if slice-level steering is used after the AGC amplifier, the offset voltage is eliminated automatically. Power Penalty Next, we derive the power penalty caused by an input offset voltage in the LA and then we determine how much offset voltage can be tolerated. In the presence of the input offset voltage VCIS, we need to increase the input signal swing, LJI", by nearly 2Vos to restore the BlER to fhe value without offset. Figure 6.5 172 MAIN AMPLIFIERS illustrates the steps leading up to this conclusion. The horizontal line in the figure indicates the level at which the signal is sliced. Thus, the power penalty is (6.31) This, of course, is the same result that we have already found in Eq. (4.52) when we first introduced the concept of power penalty. We see from this equation that the penalty is worst for small input signals. The smallest meaningful input signal to the MA, Gymin, has already been stated in Eq. (6.3). Inserting this result into Eq. (6.31) yields the worst-case power penalty: (6.32) Solving this equation for V0.y reveals the largest permissible input offset voltage Vos 5 (PP - 1) . '2. RT . ir&A. (6.33) From this equation, we can conclude that a high transimpedance helps to relax the offset requirements for the MA. Once again, a high transimpedance simplifies the MA design! Fig. 6.5 Effect of an input offset voltage in the LA: (a) without offset, (b) with offset, and (c) with offset and increased signal swing to restore the original bit-error rate. Typical Values. Next, we calculate some typical numbers based on a 0.05-dB power penalty (PP = 1.0116) and BER = lo-'* (& = 7.035). For a typical 2.5-Gb/s system (RT = 3 kQ, iLm&A = 380 nA), we obtain the numerical value VOS 5 0.01 16 .7.035 .3 kQ .380nA = 0.093 mV. (6.34) And for a typical 10-Gb/s system (RT = 1 kQ, iLm+lA = 1,40OnA), we get VOS 5 0.0116.7.035. 1 kQ. 1,400nA = 0.114mV. (6.35) In conclusion, an LA should have an input offset voltage of less than about 0.1 mV. This is a fairly low offset voltage, even for bipolar implementations. For this reason, MAS typically make use of offset compensation techniques, as we discuss further in Section 6.3.3. MA SPECIFICATIONS 173 6.2.6 Low-Frequency Cutoff Definition. The low-frequency cutoff; fLF, is defined as the lower frequency at which the small-signal gain IA(f)l dropped by 3 dB below its midband value, as illustrated in Fig. 6.6. A low-frequency cutoff in the receiver response can be caused by a coupling capacitor (AC coupling) between the TIA and the MA or by some types of offset-compensation circuits used in the MA (cf. Section 6.3.3). lAg’ I rz!T -3 dB I I *f ~LF 5WWB (250 kHz) (12 GHz) Fig. 6.6 Frequency response iof an MA with a low-frequency cutoff. When receiving a long string of zeros or ones, the output voltage of the amplifier drifts as a result of the low-frequency cutoff, as shown in Fig. 6.7. This effect also is known as baseline wander. Subsequently, the first few bits after the drift period are sliced with an offset error. Thus, a nonzero low-frequency cutoff has similar effects as a nonzero offset voltage. Specifically, the low-frequency cutoff causes (i) an increase in BER, which varies with the baseline movement and (ii) pulse-width distortions, which also vary with the baseline, that is, data-dependent jitter. PRBS all “1“s PRBS Fig. 6.7 Effect of a low-frequency cutoff: the output signal drifts during a long string of ones and subsequently causes a slice-level error. Power Penalty Next, we derive the power penalty caused by the low-frequency cutoff and then determine how low we have to make f,~. What is the longest string of zeros or ones that we will encounter in a data stream? In SONET/SDH systems, which use scrambling as a line code, the run length potentially is unlimited. However, SONET/SDH equipment is tested with a particular bit sequence that puts the system under stress: the so-called “consecutive identical digit immunity measurement” [5 13. This sequence consists of a long pseudorandom bit sequence (PRBS) with more than 2.000 bits and 50% mark density followed by 72 consecutive bits of zero; then again, more than 2,000 bits of PRBS followed by 72 bits of one. So it is reasonable to 174 MAIN AMPLIFIERS design a SONETBDH system for the maximum run length r = 72. In Gigabit Ethernet systems, which use 8B10B encoding, the runs of zeros or ones are strictly limited to r = 5. Assuming a linear system with a single-pole, high-pass transfer function, we can calculate the drift of the output voltage caused by r consecutive zeros or ones: where 4’ is the output signals swing and B is the bit rate. The approximation on the right-hand side holds if the time constant 1 /(2n fLF) is much larger than the drift time, r/B. Similar to the offset voltage, discussed in Section 6.2.5, the drift voltage causes the power penalty 2 VDRIFT PP=l+ v? Inserting the approximation for VDRI~ in Eq. (6.36) into Eq. (6.37) yields (6.37) (6.38) Solving Eq. (6.38) for fLF reveals the highest permissible low-frequency cutoff: (6.39) From this equation, we can conclude that the longer the runs are, the lower fLF must be made. [-+ Problem 6.31 Typical Values. Next, we calculate some typical numbers based on a 0.05-dB power penalty (PP = 1.0116). For a 2.5-Gb/s SONET system (r = 72), we obtain the numerical value 2.5 Gb/s fLF 5 0.01 16. ___ - - 64 kHz. 6.28 .72 And for a 10-Gb/s SONET system we get 10Gb/s fLF 5 0.0116. - = 257kHz. 6.28 .72 (6.40) (6.41) In conclusion, the low-frequency cutoff for a SONET system should be about 40,000~ lower than the bit rate (fLF < B/40,000). It the case of a Gigabit Ethernet or Fiber Channel system with r = 5, the low-frequency cutoff specification can be relaxed to fLF < B/2,700, in accordance with [107, p.701. In practice, the low-frequency cutoff often is set even lower than the numbers de- rived above (e.g., 2.5 kHz for 2.5 Gb/s and 25 kHz for I0 Gb/s). The cutoff frequency usually is set by an external capacitor, for example, a coupling capacitor (DC block) or a capacitor part of an offset compensation circuit, such as CI and C; in Fig. 6.28. In this case, there is little cost involved in making this capacitor larger to protect against longer than 72-bit runs and reducing the power penalty to less than 0.05 dB. MA SPECIFICATIONS 175 6.2.7 AM-to-PM Conversion There are a variety of effects in the optical fiber that can cause a rapid amplitude modulation (AM) of the received signal. For example, the combination of self-phase modulation (SPM) and chromatic dispersion can cause intensity overshoots at the beginning and the end of the optical pulses. Furthermore, stimulated Raman scatter- ing (SRS) in a system that carries multiple wavelength in a single fiber (a WDM or DWDM system) also can cause an amplitude modulation. The SRS effect transfers optical energy from channels with shorter wavelengths to channels with longer wave- lengths, as illustrated in Fig. 6.8. Thus, if two one bits are transmitted simultaneously over two different channels, the one in the longer-wavelength channel (hi) grows in amplitude as it propagates through the fiber, whereas the one in the shorter-wavelength channel (hz) shrinks. However, if a one and a zero bit are transmitted simultaneously over the same two channels, no such effect occurs. The result is a rapid amplitude modulation of the received signal, as shown on the right-hand side of Fig. 6.8. For more information on SPM and SRS, see [5, 1361. Fig. 6.8 Amplitude modulation in a WDM system caused by SRS. Now, if the MA (or the TIA) exhibits an amplitude-dependent propagation delay, then these amplitude variations are transformed into delay or phase variation. In other words, the amplifier may produce an unwanted phase modulation (PM). In particular, an LA may exhibit a significant amount of delay variation when it transitions from the linear regime into the limiting regime. A phase modulation of the output signal is nothing else but jitter. As we know, excessive jitter can cause bit errors and interferes with the clock and data recovery process. Therefore, it is necessary to limit the AM-to-PM conversion occurring in the MA. Definition. AM-to-PM conversion of an MA usually is specified in terms of the maximum delay variation, A TAM, observed when varying the input-signal swing over the entire dynamic range. Because the: actual signal swing vanes less than that, the AM-to-PM-induced jitter must be less than ATAM. Typical Values. period (rtO.1 UI) is required to limit the generation of jitter. This corresponds to Typically, a delay variation, ATAM, of less than f10% of the bit (6.42) (6.43) 176 MAIN AMPLIFIERS 6.3 MA CIRCUIT CONCEPTS In the following, we discuss MA circuit concepts in a general and, as much as pos- sible, technology-independent manner. This includes the multistage architecture, techniques for broadband stages, offset compensation, and automatic gain control. 6.3.1 Multistage Amplifier From the discussion in the previous section, we can conclude that the gain-bandwidth product (GBW) required for multigigabit MAS is in excess of 100 GHz. For example, a 2.5-Gb/s MA with 30-dB gain and 3-GHz bandwidth requires a GBW of about 100 GHz, similarly, a lO-Gb/s MA with 30-dB gain and 12-GHz bandwidth requires a GBW of about 400 GHz. These GBW numbers are much larger than the fr of most technologies! Is it possible to build an amplifier with a gain-bandwidth product that is much larger than fT? Yes, if we use a multistage architecture. Contrary to op amps, which typically are required to be stable under unity feedback conditions, there is no such stability requirement for MAS. MAS typically are run without feedback across the stages, except for the offset compensation loop, which is so slow that its stability is easy to ensure. For this reason, we don’t have to worry about a single dominant pole, and we can cascade multiple stages, as shown in Fig. 6.9. Multiple amplifier stages can boost the gain-bandwidth product of the amplifier (GBW,,,) way beyond that of a single stage (GBWs). How does this work? Let’s start with a simple example to develop our intuition. All stages in our sample amplifier are identical and have a brick-wall, low-pass frequency response with a bandwidth of 3 GHz. If we put these stages together, the total gain increases, but the bandwidth remains at 3 GHz. Now, our goal is to build an amplifier with a total gain At,, = 30dB (31.6~) and a bandwidth of 3GHz, which means that our total gain-bandwidth product must be GBWtOt = 3 1.6 x 3 GHz = 95 GHz. Consider these two approaches: 0 Single-stage architecture (n = 1). In this case, the GBW of the stage is equal to the GBW of the total amplifier: GBWs = GBWtot = 95 GHz. 0 Three-stage architecture (n = 3). In this case, each stage needs a gain of only lOdB (3.16x), and thus the gain-bandwidth per stage is GBWs = 3.16 x 3 GHz = 9.5 GHz. In conclusion, the three-stage design requires lox less GBW per stage! We also could say that cascading three stages gave us a gain-bandwidth extension GBWt,t/GBWs of lox. How far can we push this? Could we build our sample amplifier from stages with GBWs = 0.95 GHz? No! As we cascade more and more stages, the GBW require- ment per stage is reduced, but even with an infinite number of stages, we still need a stage gain of slightly more than 1 .O to ever reach the 30-dB total gain. and thus a mini- mum GBWs of slightly more than 3 GHz is required. We thus conclude that, in our ex- ample, the maximum possible gain-bandwidth extension is 95 GHz/3 GHz = 3 1.6~. MA CIRCUIT CONCEPTS 177 Fig- 6.9 An n-stage amplifier with overall gain-bandwidth product GBWto, and stage gain- bandwidth product GBWs. We can easily generalize the above example for an arbitrary number of stages, n, and an arbitrary total gain, Atot. In this case, the stage gain is A,, , and thus the GBW extension becomes Iln This function is plotted in Fig. 6.10 for Atot = 30 dB and is labeled “Brick Wall.” We can see from Eq. (6.44) with n + 00 that the maximum GBW extension that can be achieved with a multistage amplifier is given by Atot. 15 t- lS‘ Order 1 Atot=30dB Ot 0 1 2 3 4 5 6 7 0 9101112 Number of Stages n Fig. 6.70 Gain-bandwidth extension as a function of the number of stages. Real amplifier stages don’t have a brick-wall frequency response; they are more likely to have a first- or second-order response. A simple transistor stage with an R-C load has a first-order response, whereas il more complex stage with local feedback or inductive load has a second-order response. The gain-bandwidth extensions for these two cases also are plotted in Fig. 6.10 (for Atot = 30dB). For these cases, the GBW extension is less dramatic than for the ideal brick-wall case, but we can still boost the gain-bandwidth product by a respectable 6x or 12x. The reason for this reduced GBW extension is that the total amplifier bandwidth shrinks as we cascade more and more stages with a slow (non-brick-wall) frequency rolloff. Furthermore, we can see from the plots that there is an optimum number of stages for which GBWtot/GBWs reaches the maximum. . t$& 5 7.0 35 . J0.023 .4 . (3 kS2)2 . (380nA)2 + (49.0 FV)~ ='2 .5 mV. (6.28) And for a typical IO-Gb/s system (RT = 1 kS2, ir!IA = 1,40OnA), we get t$&s 5 7.0 35 .J0.023. on a 0. 05- dB power penalty (PP = 1.0116). For a 2 .5- Gb/s SONET system (r = 72), we obtain the numerical value 2 .5 Gb/s fLF 5 0.01 16. ___ - - 64 kHz. 6.28 .72 And for a 10-Gb/s. than the numbers de- rived above (e.g., 2 .5 kHz for 2 .5 Gb/s and 25 kHz for I0 Gb/s). The cutoff frequency usually is set by an external capacitor, for example, a coupling capacitor (DC block)