VHDL Programming by Example phần 1 ppsx

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VHDL Programming by Example phần 1 ppsx

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[...]... Chapter One In 19 86, VHDL was proposed as an IEEE standard It went through a number of revisions and changes until it was adopted as the IEEE 10 76 standard in December 19 87 The IEEE 10 76 -19 87 standard VHDL is the VHDL used in this book (Appendix D contains a brief description of VHDL 10 76 -19 93.) All the examples have been described in IEEE 10 76 VHDL, and compiled and simulated with the VHDL simulation... inverter PORT(in1 : IN BIT; x : OUT BIT); END COMPONENT; COMPONENT orgate PORT(a, b, c, d : IN bit; x : OUT BIT); END COMPONENT; SIGNAL s0_inv, s1_inv, x1, x2, x3, x4 : BIT; BEGIN U1 : inverter(s0, s0_inv); U2 : inverter(s1, s1_inv); U3 : andgate(a, s0_inv, s1_inv, x1); U4 : andgate(b, s0, s1_inv, x2); U5 : andgate(c, s0_inv, s1, x3); U6 : andgate(d, s0, s1, x4); U7 : orgate(x2 => b, x1 => a, x4 => d,... Waveform Display Set Watchpoint Complex Triggers Chapter 18 369 Place and Route Process Placing and Routing the Device Setting up a project Chapter 17 Place and Route 4 01 4 01 4 01 402 403 403 404 405 405 406 406 408 408 409 410 Appendix A Standard Logic Package 413 Appendix B VHDL Reference Tables 435 Appendix C Reading VHDL BNF 445 Contents xi Appendix D VHDL9 3 Updates Alias Attribute Changes Bit String Literal... Bridges2Silicon CHAPTER 1 Introduction to VHDL The VHSIC Hardware Description Language is an industry standard language used to describe hardware from the abstract to the concrete level VHDL resulted from work done in the ’70s and early ’80s by the U.S Department of Defense Its roots are in the ADA language, as will be seen by the overall structure of VHDL as well as other VHDL statements VHDL usage has risen... sequential, as shown in the following: ARCHITECTURE sequential OF mux IS (a, b, c, d, s0, s1 ) VARIABLE sel : INTEGER; BEGIN IF s0 = ‘0’ and s1 = ‘0’ THEN sel := 0; ELSIF s0 = 1 and s1 = ‘0’ THEN sel := 1; ELSIF s0 = ‘0’ and s1 = ‘0’ THEN sel := 2; ELSE sel := 3; END IF; CASE sel IS Introduction to VHDL 9 WHEN 0 => x x x x . Types 10 2 File Type Caveats 10 5 Subtypes 10 5 Chapter 5 Subprograms and Packages 10 9 Subprograms 11 0 Function 11 0 Contents vi Conversion Functions 11 3 Resolution Functions 11 9 Procedures 13 3 Packages. Execution 10 Sequential Statements 10 Architecture Selection 11 Configuration Statements 11 Power of Configurations 12 Chapter 2 Behavioral Modeling 15 Introduction to Behavioral Modeling 16 Transport. Attributes 14 7 Value Block Attributes 14 9 Function Kind Attributes 15 1 Function Type Attributes 15 1 Function Array Attributes 15 4 Function Signal Attributes 15 6 Attributes ’EVENT and ’LAST_VALUE 15 7 Attribute

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