Compact Summary of VHDL phần 6 pptx

E'INSTANCE_NAME is a string containing the design hierarchy including E. E'PATH_NAME is a string containing the design hierarchy of E to design root. Other Links VHDL help page● Hamburg VHDL Archive (the best set of links I have seen!)● RASSP Project VHDL Tools● VHDL Organization Home Page● gnu GPL VHDL for Linux, under development● More information on Exploration/VHDL from FTL Systems.● Go to top Go to VHDL index VHDL Predefined Attributes http://www.csee.umbc.edu/help/VHDL/attribute.html (2 of 2) [22/12/2001 15:23:42] |Summary |Design Units |Sequential Statements |Concurrent Statements |Predefined Types |Declarations | |Resolution and Signatures |Reserved Words |Operators |Predefined Attributes |Standard Packages | Standard VHDL Packages VHDL standard packages and types The following packages should be installed along with the VHDL compiler and simulator. The packages that you need, except for "standard", must be specifically accessed by each of your source files with statements such as: library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_textio.all; use IEEE.std_logic_arith.all; use IEEE.numeric_bit.all; use IEEE.numeric_std.all; use IEEE.std_logic_signed.all; use IEEE.std_logic_unsigned.all; use IEEE.math_real.all; use IEEE.math_complex.all; library STD; use STD.textio; A version of these packages, declaration and body, are in this directory The package standard is predefined in the compiler. Types defined include: bit bit_vector typical signals integer natural positive typical variables boolean string character typical variables real time delay_length typical variables Click on standard to see the functions defined Note: This package must be provided with compiler, do not use this one. The package textio provides user input/output Types defined include: line text side width Functions defined include: readline read writeline write endline Click on textio to see how to call the functions The package std_logic_1164 provides enhanced signal types Types defined include: std_ulogic std_ulogic_vector std_logic std_logic_vector Click on std_logic_1164 to see available functions The package std_logic_textio provides input/output for 1164 types Functions defined include: readline read Standard VHDL Packages http://www.csee.umbc.edu/help/VHDL/stdpkg.html (1 of 3) [22/12/2001 15:23:43] writeline write endline Click on std_logic_textio to see how to call the functions The package std_logic_arith provides numerical computation This package name unfortunately seams to have several definitions: std_logic_arith_syn.vhd defines types signed and unsigned and has arithmetic functions that operate on signal types signed and unsigned and std_logic_vector and std_ulogic_vector, but adding A to B of std_logic_vector type, needs unsigned(A) + unsigned(B). Click on std_logic_arith_syn to see the functions defined std_logic_arith_ex.vhd has arithmetic functions that operate on signal types std_logic_vector and std_ulogic_vector Click on std_logic_arith_ex to see the functions defined The package numeric_bit provides numerical computation Types defined include: unsigned signed arrays of type bit for signals Click on numeric_bit to see the functions defined The package numeric_std provides numerical computation Types defined include: unsigned signed arrays of type std_logic for signals Click on numeric_std to see the functions defined The package std_logic_signed provides signed numerical computation on type std_logic_vector Click on std_logic_signed to see the functions defined The package std_logic_unsigned provides unsigned numerical computation on type std_logic_vector Click on std_logic_unsigned to see the functions defined The package math_real provides numerical computation on type real Click on math_real to see the functions defined This declaration and body are in mathpack The package math_complex provides numerical computation Types defined include: complex, complex_vector, complex_polar Click on math_complex to see the functions defined This declaration and body are in mathpack Standard VHDL Packages http://www.csee.umbc.edu/help/VHDL/stdpkg.html (2 of 3) [22/12/2001 15:23:43] Other Links VHDL help page● Hamburg VHDL Archive (the best set of links I have seen!)● RASSP Project VHDL Tools● VHDL Organization Home Page● gnu GPL VHDL for Linux, under development● More information on Exploration/VHDL from FTL Systems.● Go to top Go to VHDL index Standard VHDL Packages http://www.csee.umbc.edu/help/VHDL/stdpkg.html (3 of 3) [22/12/2001 15:23:43] VHDL reference material Contents Using Cadence VHDL on CSEE machines● Using FTL Systems Exploration VHDL● Compact Summary of VHDL● Printable Compact Summary of VHDL● Sample VHDL code● VHDL Cookbook in PostScript● Download free VHDL compiler and simulator● VHDL intro by Francis Bruno in PostScript● VHDL project by Francis Bruno in PostScript● VCOMP/VSIM from University of Pittsburgh● VHDL standard packages and types● FPGA and other CAD information● Draft of IEEE Standard VHDL Language● Other Links● Using Cadence VHDL on CSEE machines First: You must have an account on a CSEE machine because the Cadence software is licensed to this specific machine. This is in addition to your gl account but may be the same user id. Use ssh cadence1.cs.umbc.edu or ssh cadence2.cs.umbc.edu You can copy many sample files to your working directory using: cp /web/www/help/VHDL/samples/add32b.vhdl . # many available Next: Follow instructions exactly or you figure out a variation. 1) Get this tar file into your home directory (on cadence1 or 2) cs411.tar and then type commands: tar -xvf cs411.tar cd vhdl tcsh source vhdl_cshrc make more ctest1.out make clean # saves a lot of disk quota Then do your own thing with Makefile for other VHDL files 2) The manual, step by step method (same results as above) Be in your home directory. mkdir vhdl # for your source code .vhdl .vhd cd vhdl mkdir vhdl_lib # your WORK library, keep hands off You now need to get the following 6 files into you vhdl directory: VHDL reference material http://www.csee.umbc.edu/help/VHDL/index.shtml (1 of 5) [22/12/2001 15:23:44] vhdl_cshrc cds.lib change $HOME to your path if needed hdl.var Makefile.cadence for first test ctest1.vhdl for first test ctest1.run for first test Make the following modification to cds.lib : Edit and replace $HOME with the specific path to your home if needed directory. e.g. /home/grad4/auser12 mv Makefile.cadence Makefile # Run the test run: tcsh source vhdl_cshrc make # should be no error messages more ctest1.out # it should have VHDL simulation output make clean You are on your own to write VHDL and modify the Makefile. Remember each time you log on: cd vhdl tcsh source vhdl_cshrc make # or do your own thing. The above is the latest generation Cadence "ldv" "ncvhdl, nceval, ncsim" Using FTL Systems Exploration VHDL First: Read Appendix H of Ashenden's book, p723 The steps are: load the CD, make a registration file, EMail the file, get back a license file, download the VHDL analyzer/compiler and simulator. Then: Follow the Quick Start Guide on page 728. VHDL Cookbook (PostScript files) The following eight PostScript files provide an introduction to VHDL Contents● Chapter 1● Chapter 2● Chapter 3● Chapter 4● Chapter 5● Chapter 6● Chapter 7● VHDL reference material http://www.csee.umbc.edu/help/VHDL/index.shtml (2 of 5) [22/12/2001 15:23:44] BNF for VHDL 93, plain text● The above is by Peter Ashenden who now has an updated version out as books: "The Student's Guide to VHDL" ISBN 1-55860-520-7 and "The Designer's Guide to VHDL" second edition ISBN 1-55860-674-2 Examples of VHDL from Ashenden's Designer's Guide are here Download free VHDL compiler and simulator This is how I downloaded and installed a free VHDL compiler and simulator on a Linux system. It is not a full VHDL and has some bugs, but it works on many circuits and features. Using browser: ftp://poppy.snu.ac.kr/pub/vhdl Save link as: on files newivsim_linux.tar.gz vdt-2.8_linux_1.tar.gz Using command line FTP: ftp poppy.snu.ac.kr anonymous you@your.mail.address binary get newivsim_linux.tar.gz get vdt-2.8_linux_1.tar.gz quit Then: in some directory your-dir gunzip newivsim_linux.tar.gz tar -xvf newivsim_linux.tar gunzip vdt-2.8_linux_1.tar.gz tar -xvf vdt-2.8_linux_1.tar Now, in .bashrc or whatever startup file you use, put: ( "your-dir" should be the full path ) IVSIM=your-dir/ivsim-1.2 export IVSIM VDT=your-dir/vdt-2.8 export VDT PATH=$PATH:$IVSIM/bin:$VDT/bin export PATH Now, make a directory where you will have your VHDL source files, e.g. in your-dir mkdir src cd src Create a file named .vdtrc with the lines: library IEEE $IVSIM/lib/IEEE library WORK ./WORK Make a WORK subdirectory, mkdir WORK (needed by compiler) Now, in your VHDL source directory compile files with VHDL reference material http://www.csee.umbc.edu/help/VHDL/index.shtml (3 of 5) [22/12/2001 15:23:44] van your-vhdl-file.vhd Now, simulate your VHDL design with ivc -a top-design-unit-name you may have as many -c design-unit clauses as necessary the top-design-unit-name is NOT the file name If all went well, your simulation runs (without controls!) Use ^C to stop a run-a-way simulation. Create an xxx.run file that contains run 100 quit and execute TOP-DESIGN-UNIT-NAME -f xxx.run Yes, the executable file is in all upper case. You need the C, C++ development stuff installed on Linux because the compiler/simulator generate, compile and link using gcc. OK, I am just giving a simple example of what is in the manual, go read Inspire Manual (txt) or better yet, print Inspire Manual (PostScript) The compiler 'van' and elaborator/simulator 'ivc' are working on linux.gl.umbc.edu from directory /afs/umbc.edu/users/s/q/squire/pub/linux/ with subdirectories vdt-2.8/bin and ivsim-1.2/bin The IEEE subdirectory is ivsim-1.2/lib/IEEE for your .vdtrc file. More linux.gl specific information in van.doc VHDL intro by Francis Bruno (PostScript files) The following four PostScript files provide Francis Bruno's introduction to VHDL Title Page● Table of Contents● Body● Appendix● VHDL project by Francis Bruno (PostScript files) The following four PostScript files plus index and .tar.gz files provide Francis Bruno's VHDL project. Title Page● Table of contents● Body● Appendix● VHDL reference material http://www.csee.umbc.edu/help/VHDL/index.shtml (4 of 5) [22/12/2001 15:23:44] Bruno index to models● VHDL source code as .tar.gz● VCOMP/VSIM from PITT (PostScript file) The following PostScript file provides an introduction to VHDL and instructions for compiling and simulating using vcomp/vsim. VSIM manual● FPGA and other CAD information You can get working chips from VHDL using synthesis tools. One of the quickest ways to get chips is to use FPGA's, Field Programmable Gate Arrays. The two companies listed below provide the software and the foundry for you to design your own integrated circuit chips: www.altera.com www.xilinx.com Complete Computer Aided Design, CAD, packages are available from companies such as Cadence, Mentor Graphics and Synopsis. Draft of IEEE Standard VHDL Language Draft 2000/D3 HERE Other Links Hamburg VHDL Archive (the best set of links I have seen!)● RASSP Project VHDL Tools● VHDL Organization Home Page● gnu GPL VHDL for Linux, under development● More information on Exploration/VHDL from FTL Systems● Go to top Last updated 10/15/01 VHDL reference material http://www.csee.umbc.edu/help/VHDL/index.shtml (5 of 5) [22/12/2001 15:23:44] . Packages http://www.csee.umbc.edu/help /VHDL/ stdpkg.html (3 of 3) [22/12/2001 15:23:43] VHDL reference material Contents Using Cadence VHDL on CSEE machines● Using FTL Systems Exploration VHDL Compact Summary of VHDL Printable. VHDL Printable Compact Summary of VHDL Sample VHDL code● VHDL Cookbook in PostScript● Download free VHDL compiler and simulator● VHDL intro by Francis Bruno in PostScript● VHDL project by. directory. mkdir vhdl # for your source code .vhdl .vhd cd vhdl mkdir vhdl_ lib # your WORK library, keep hands off You now need to get the following 6 files into you vhdl directory: VHDL reference