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5/1 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Course contents • Digital design • Combinatorial circuits: without status • Sequential circuits: with status • FSMD design: hardwired processors  Language based HW design: VHDL 5/2 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Language based HW design: a VHDL primer • Introduction • A first look at VHDL • Signals and data types • VHDL operators • Concurrent versus sequential statements • Sequential construction statements • Higher performance, less portability: e.g. synthesis issues for Xilinx 5/3 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Language based HW design: a VHDL primer  Introduction • A first look at VHDL • Signals and data types • VHDL operators • Concurrent versus sequential statements • Sequential construction statements • Higher performance, less portability: e.g. synthesis issues for Xilinx 5/4 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL VHDL primer: Introduction • Acronym:  VHDL = VHSIC Hardware Description Language  VHSIC = Very High Speed Integrated Circuit • What is VHDL?  A programming language for describing the behavior of digital systems  Design entry language, used for  Unambiguous specification at behavioral and RTL level  Simulation (executable specification…)  Synthesis  Documentation • Standardisation: IEEE 1076  First version: 1986  Second version: 1993  New version about to appear 5/5 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL VHDL primer: Introduction • When to use VHDL instead of schematics?  Drawbacks:  VHDL is easy to learn but hard to master (semantics are quite different from software languages)  VHDL has a difficult syntax (Language sensitive editors with templates for all language constructs)  VHDL is very ‘wordy’: lots of code to type for just a few simple things  A list of instructions is less intuitive to understand than a block diagram for a human being  VHDL is designed to make simulation efficient: contains aspects that have hardly anything to do with hardware behavior, but is useful to speed-up event driven simulation 5/6 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL VHDL primer: Introduction • When to use VHDL instead of schematics?  Easier to capture complex circuits: higher level of abstraction with automated synthesis  you specify ‘add’ instead of jotting down a specific type of adder: the synthesis tool will instantiate the best type of adder under timing, area & power constraints  easy to parametrise (e.g. word length, queue depth)  easy to specify arrays of components  Portable across many tools for simulation, synthesis, analysis, verification, … of different vendors (e.g. Synopsys, Mentor Graphics, …) 5/7 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL VHDL primer: Introduction • Limitations of VHDL  The standard only describes syntax and semantics, but not the coding style  you can specify the same behavior (e.g. MUX) in an almost unlimited number of ways  each leading to a completely different implementation (e.g. Multiplexor or tri-state bus)  which is synthesis tool dependent.  You should do lots of experimentation with style- tool combinations to be able to predict how the hardware will look like that will be synthesised. Is prediction necessary? You also do not predict the ASM generated by C; C is less efficient than ASM but faster to write. Currently, it is hard to tolerate the inefficiency caused by the higher level specification for hardware.  Note: for DSP processors programmed in C, we do predict ASM and have to experiment with style- compiler combinations for efficiency reasons!! 5/8 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL VHDL primer: Introduction • Limitations of VHDL (ctud)  Only a subset of VHDL can be automatically synthesised; each vendor supports a different subset  Only digital; special extension (not yet widely adopted) for analog: VHDL-AMS (acronym for VHDL Analog and Mixed Signal)  IEEE standard 1076.1-1999  is a super-set of the full IEEE VHDL 1076-1993 standard for digital design 5/9 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL VHDL primer: Introduction • Abstraction levels  Behavioral  Interconnected functions  Only info on functions or algorithms (what)  Only timing needed to let the function work correctly  OK for VHDL  Behavioral synthesisers immature; used for high level executable specification in top-down design and manual synthesis into RTL 5/10 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL VHDL primer: Introduction • Abstraction levels  RTL  Interconnected registers and combinatorial units  Info on function (what) and architecture (how)  Cycle accurate  No technology dependent timing info  OK for VHDL  Good synthesisers  Gate level  Interconnected gates and flip-flops  Info on function and architecture  Info on technology dependent timing (gate delays)  Layout  Info on layout on silicon  Continuous timing  Analog effects [...]... Struct1 of Test is component Comparator is Two instantiations port( X,Y: in bit_vector(0 to 7); of the same component Z: out bit); ‘Comparator’ with its end component Comparator; signal binding begin Compare1: component Comparator port map (In1,In2,Out1); Compare2: component Comparator port map (In1,In3,Out2); end architecture Struct1; Notes: - The two ‘comparator’ components work concurrently!!! - This... R.Lauwereins Imec 20 01 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL • Declare a 3-input AND gate A B C Y 3-input AND gate entity AND3 is port ( A,B,C: in bit; Y: out bit); end entity AND3; architecture RTL of AND3 is begin Y In1) 5/23 © R.Lauwereins Imec 20 01 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 5/24 A First look at VHDL: Syntax... circuit Compare Sequential circuits FSMD design A A[0] B[0] A [1] VHDL B [1] B A[7] B[7] 5 /16 XNOR AND EQ EQ © R.Lauwereins Imec 20 01 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 5 /17 A First look at VHDL: Entity and Architecture • Declaration of the ‘Compare’ design entity: ‘Entity’ specifies Eight bit comparator -entity Compare is port( A,B: in bit_vector(0 to 7); EQ: out... Two calls to the function ‘Compare’ with its argument binding Out1 = Compare(In1, In2); Out2 = Compare(In1, In3); } Notes: - The two ‘compare’ function calls are executed sequentially 5/20 - This main program is executed once and stops In VHDL, all components describe relations that are valid continuously and forever © R.Lauwereins Imec 20 01 Digital design A First look at VHDL: Configuration • When an... architecture Behav of MUX 21 is begin Y . VHDL-AMS (acronym for VHDL Analog and Mixed Signal)  IEEE standard 10 76. 1- 1 999  is a super-set of the full IEEE VHDL 10 7 6 -1 993 standard for digital design 5/9 © R.Lauwereins Imec 20 01 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL VHDL. program */ main() { int In1, In2, In3; int Out1, Out2; Out1 = Compare(In1, In2); Out2 = Compare(In1, In3); } Two calls to the function ‘Compare’ with its argument binding Notes: - The two ‘compare’. ‘Test’ with 3 8-bit inputs (In1, In2, In3) and two boolean outputs (Out1, Out2). The first output equals 1 when the first and second input are equal; the second output equals 1 when the