Thiết kế và thực hiện hệ thống VLSI - 02 pot

Design and Implementation of VLSI Systems Lecture 02 Thuan Nguyen Faculty of Electronics and Telecommunications, University of Science, VNU HCMUS Spring 2011 1 LECTURE 2: CMOS CIRCUIT 2 MOS Transistor 1 CMOS Logic 2 LECTURE 2: CMOS CIRCUIT 3 MOS Transistor 1 CMOS Logic 2 IMPACT OF DOPING ON SILICON RESISTIVITY dope with phosphorous or arsenic  n-type dope with boron  p-type silicon 4.99510 22 atoms in cm 3 Resistivity 3.2  10 5 Ωcm 1 atom in billion  88.6 Ωcm 1 atom in million  0.114 Ωcm 1 atom in thousand  0.00174 Ωcm 1 atom in billion  266.14 Ωcm 1 atom in million  0.344 Ωcm 1 atom in thousand  0.00233 Ωcm  Electrons are more mobile/faster than holes MOS TRANSISTOR 4 WHAT HAPPENS IF WE SANDWICH P & N TYPES? n p A B Al One-dimensional representation  In equilibrium, the drift and diffusion components of current are balanced; therefore the net current flowing across the junction is zero. 5 WHAT HAPPENS IF WE SANDWICH P & N TYPES? 6 PN-JUNCTION REGIONS OF OPERATION In reverse bias, the width of the depletion region increases. The diode acts as voltage-controlled capacitor. A forward bias decreases the potential drop across the junction. As a result, the magnitude of the electric field decreases and the width of the depletion region narrows. 7 NMOS AND PMOS TRANSISTORS nMOS transistor pMOS transistor Each transistor consists of a stack of a conducting gate, an insulating layer of silicon dioxide and a semiconductor substrate (body or bulk) Body is typically grounded Body is typically at supply voltage 8 NMOS TRANSISTOR n+ p GateSource Drain bulk Si SiO 2 Polysilicon n+ g=0: When the gate is at a low voltage (V GS < V TN ):  p-type body is at low voltage  source and drain-junctions diodes are OFF  transistor is OFF, no current flows g=1: When the gate is at a high voltage (V GS ≥ V TN ):  negative charge attracted to body  inverts a channel under gate to n-type  transistor ON, current flows, transistor can be viewed as a resistor 9 NMOS PASS ‘0’ MORE STRONGLY THAN ‘1’ n+ p GateSource Drain bulk Si SiO 2 Polysilicon n+ • Why does ‘1’ pass degraded? 10 [...]... transparent latch or level-sensitive latch CLK D Latch  CLK D Q Q 28 D LATCH DESIGN  Multiplexer chooses D or old Q CLK D 1 CLK Q Q Q D Q 0 CLK CLK CLK 29 D LATCH OPERATION Q D CLK = 1 Q Q D Q CLK = 0 CLK D Q 30 D FLIP-FLOP When CLK rises, D is copied to Q  At all other times, Q holds its value  a.k.a positive edge-triggered flip-flop, masterslave flip-flop  CLK CLK D Flop D Q Q 31 D FLIP-FLOP DESIGN  Built... CMOS LOGIC VDD A Y A Y GND pMOS + nMOS = CMOS An nMOS and pMOS make up an inverter 14 MORE CMOS GATES Y What is this gate function? A B 15 3-INPUT NANDS pMOS pull-up network inputs output nMOS pull-down network What are the advantages of CMOS circuit style? 16 SERIES-PARALLEL COMBINATIONS     nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON Parallel: either can be ON a a a a 0 g2 0 1 1 0 g1 1 0 1... down 20 WHAT ARE THE TRANSISTOR SCHEMATICS OF THE NOR GATE? 21 AND-OR-INVERTER (AOI) GATE A C A C B D B D (a) A (b) B C C A D (c) D B (d) C D A B A B C D Y A C B D (e) (f) Y 22 TRANSMISSION GATE Input g = 0, gb = 1 a b b gb b gb g = 1, gb = 0 strong 1 1 g g a g = 1, gb = 0 0 strong 0 g = 1, gb = 0 a b g a Output a g b gb a b gb 23 TRI-STATE INVERTER A A A EN Y Y Y EN = 0 Y = 'Z' EN = 1 Y=A EN 24 2:1... TRANSISTOR THE NOR GATE? SCHEMATICS OF A B Y 1:00 1:01 1 :02 1:03 1:04 1:05 1:06 1:07 1:08 1:09 1:10 1:12 1:13 1:14 1:15 1:16 1:17 1:18 1:19 1:20 1:21 1:22 1:23 1:24 1:25 1:26 1:27 1:28 1:29 1:30 1:31 1:32 1:33 1:34 1:35 1:36 1:37 1:38 1:39 1:40 1:41 1:42 1:43 1:44 1:45 1:46 1:47 1:48 1:49 1:50 1:51 1:52 1:53 1:54 1:55 1:56 1:57 1:58 1:59 2:00 0:01 0 :02 0:03 0:04 0:05 0:06 0:07 0:08 0:09 0:10 0:12 0:13...PMOS TRANSISTOR Source Gate Drain Polysilicon SiO2 p+ p+ n bulk Si g=0: When the gate is at a low voltage (VGS < VTP):  positive charge attracted to body  inverts a channel under gate to p-type  transistor ON, current flows g=1: When the gate is at a high voltage (VGS ≥ VTP):  negative charge attracted to body  source and drain junctions are OFF  transistor OFF, no current flows 11... edge-triggered flip-flop, masterslave flip-flop  CLK CLK D Flop D Q Q 31 D FLIP-FLOP DESIGN  Built from master and slave D latches CLK CLK CLK QM D CLK QM Latch D Latch CLK CLK Q CLK CLK Q CLK CLK 32 D FLIP-FLOP OPERATION D QM Q CLK = 0 D QM Q CLK = 1 CLK D Q 33 HOMEWORKS Homework Assignment #1 View  Submit your answer in the next week  34 Q&A 35 . this gate function? 15 A B Y 3-INPUT NANDS What are the advantages of CMOS circuit style? 16 pMOS pull-up network output inputs nMOS pull-down network SERIES-PARALLEL COMBINATIONS 17  nMOS:. TYPES? 6 PN-JUNCTION REGIONS OF OPERATION In reverse bias, the width of the depletion region increases. The diode acts as voltage-controlled capacitor. A forward bias decreases the potential. 1 atom in thousand  0. 0023 3 Ωcm  Electrons are more mobile/faster than holes MOS TRANSISTOR 4 WHAT HAPPENS IF WE SANDWICH P & N TYPES? n p A B Al One-dimensional representation