Điện Tử - Cơ Sở Thiết Kế Mạch - Design Trên Máy Tính (Phân 2) part 2 ppt

begin end component component Al'!D2_GATE purt ( 10. II , in IllT; 0; uut lllT ); end component: U L XOICGATE port map ( Ill. I I. S ); \]2, AND2JiATE port map (IO.lI. CO); end STRUC[URE; Moi thimh ph.'in cua tlwc the' neu tren co the xu)' dl!ng tu cae th~rc the kh,\c m6 1,'1 de chue nang ella cluing. Vi dl,l phiin tt'r XOR_.GATE etl the dll'9\: m6 t:1 theo h:mh vi nh\1 sau. entity XOR-GATE~ port ( 10. 1\ , in BIT; S. CO ; out fliT ); end XOR_GATE; architecture BEHAVIOR of XOR_GATE is hcgin 0<= 10 xor 1\ arfer \0 ns: end BEflA Y[OR; Bicu dicn e:'lu true cua Gte phii.ll cap thiel 1<.6 <'mh hu'ong tai qua trlnh phan tach thiet kc·. Di6u n£1.),' XUi!1 phat tu e{le d~tc diem ella b~ Ih6ng ctlfl)'e thiet kc. 6 tn('11 tnue phan dlp b[il k)l, h~ thong c1u'ge dlu t'.IO bdi de lien ke't ella nhCrng Ih111lh phfin 6 mue dang xc\. Bi6u elien cUu true ella kicn true ehu'a danh siich cae h('1p (kn. 6 Illt:l'e thfip nh[it ella qu,i trlnh phall t{lch. ta ph:li 1110 la h:l1lh vi Clla cae ph fin It'r nam trang thiet kc c'5 muc nay. Qm\. Irlnh phan cap co the bieu oien dU'oi d'.ll1g cay phan .~ , M6 hinh hoa hanh vi Hinh 6.9 ely p\l,ln dp L"~U dlC11 kic'n Inle ella JllO hl11h tl11CI kt'. c:t'p ( hinh 5.9 ). T'.li mue Ihap nhfit ella phan cap, ta phli 1116 hi hi1l1h vi ella cae th~t'e the thea trinh tl! ma 1116 hinh lTIi.ICh , ,e dU\1C mo ph('mg. 149 3. Cae g6i thiet kc M~le dfch ehfnh ella cae g<11 la 1(lp h\1p cae phan tll' C<1 the dllllg chung giiJa hal llOZIC nhicu c10n vi thiel kc. Mt)t goi bao gom hai th~ll1h phan: ph{in khai h,io goi va ph[in Ih[lll goi. Ph[in khai bao g6i chua tXt ca cac khai hao cua mqi tcn. (\;"hLrng len nily .'ie dm/c cae don vi thiet kc dung den khi SLf dung g6i. Tht'mg tlnii'mg: ph[\n khai h<'lo chua m(lt so ki~u clt11i¢u chung, ceie ht1ng \"~11ll6 1;1 ella dc chVtmg tdnb COil. Ph:ill lh,tn gai baa gom eac ph,ill th,in CU<.I cac cilu'tmg trlnh CO]) ilia t,i trong ph[in khai hao goi. Phan thfm n~IY 1~1 :in d6i \'oi hen ngo~li. Phi\n than ella goi khong bftt hut)c ph,li co n6u khong e(l ehvOIlg trlllh con dU\1C 1116 1:1 trong g(li. Vi cll.t, ta co khai bao g6i nhu sau. Cioi nay khaJ hilO 111~'it StS ki~u. hic'n, h,lng V,I chunng trinh con. pllckage EX_PKG is subtype INT8 is INTEGER range 0 to 255 constant ?ERO : INT8 :=0 : (.'onstant MAX : INT8 := 100; procedure Increemcnt ( variable count: inout Il'\T8 ) end EX-PKG. Do trong khai h'\.o co thu lL.lc Inen:cll1cnt nell 1<1 dn phili e6 th{lll ellil g()i tuong ling v6i khaJ hilO ~oi trcn. 1,0 package body EX-PKU is procedure lnercemcnt ( v41riable Dala: inout INT8 ) is begin end if if ( Count >= MAX) then Count := ZERO: else Count := Coullt + 1· end Incrccm :nt; end EX-PKCJ: 4. C{lC cau hlnh M{)t tlwe the co the: co mot Y(li kicn tnk. Trong qu,i trlnh thle"1 k0", la co the" dn phai Iht1 nghi¢m llH)1 \"ll.i bicn the elld Ihict kc btmg deh slr d~ll1g «te kien true kh{le nhau. Ciu hinh 1& thtmh phtin cd b:m ella dan V! thiet kl:". elll hlnh eho phep gtm de phien ban eua thl!C the yito nhCrng kicn Ink kh,\c nhau. Glu hlnh el"mg eo the duc.~e Sli" dung de thay the" me)t deh nhanh ch6ng de ph;\n Ill' ella thlle the trong bicu Jicn cau trlK ella thic"t kc'. CU ph,ip ella 1116 ta eAu 1Il11h: C()nfi~unltion '(;/I_cditldll/l of f(;/I_1Iu/C_lh(;" is \ pltci"ll_ khoi -'h/O _Clio _ uilt-'u'nh \ fOI' title ,(/ oi(l kh()"i \ m(lIlr_d(use I { ((ic_pllltll 1/1 (11(1 C{]II-'Iillh I end for; Vi tu pillin Jlul/Ju/o _ Clia __ c(/'lI_hillil eho phep du hlnh Slr dl!ng de phfil1 tll trong de goi vii de tlnl'vicn. Vi tv dlk rd Cli(/JI/()I" X<.lc d(nh cau hioh eho hin Irl\C eoa Ihue Ih~. Vi d~1 Configuration FADD_CONFIG of FULL_ADDER is [or STRUCHJRE for HAl. HAL HALF_ADDER use entity WORK.HALF _ADDER(STRlICTURE) [or ORI: OR_GATE usc entity WORK.lJRJiATE; end for end FADD_CONFIG; hung cau hlnh nay, chung ta thay: STRUcnJRE ehi to'i kien true eoa thl!c Ih6 FULL_ADDER dUde (Ut cau hlnh. HA 1 V:l HAl: Iii cae t1we the gan voi thl!C the HALF _ADER ella kicn tn.k STRUCTURE Hong thu \'i~n WORK. 151 Phltn ban OR I gtlt1 \'6'i tlu,l'c IhJ OICGATE lrong tilu Yi¢n WORK. Ph:lt1 Itch VIIDL Ii'! qu{t Irlllh kicll1 Ira Ihi':t kc' VHDL eho dllllg Cll ph<.ip <I nglf nghTa. Sau khi phtlt1 Itch VHDL, d.e don \'! thiet kC' sc dUQ'c luu giu' trotH! C{tC thu vitn de sU: dun" sau n~IY. Tim \'len thiet kc co the chefa nilu"llo ~ . ' c _, c phein tLr tilu \'i¢n sau: Goi : i:'lllhlrng m() ta, khai b,io clU'0e clung chung. Tiwe the: Iii nhling me) ta thic'l kc dU\K dung chung. Kic'n true: nhlrng thie1 k( chi tic't dlfqc dLlng chung. C\u hinh : [;1 nhu'ng phien b,in ella thlle thc du(}"c dllng chung. eic don vj tilu' \'ien Iii dIe e<.'iu true YHDL co the dUQ'e ph,ln tfeh rieng r0 thco trlnh 11,1' nh[11 d!nh. Vi dl.l, tlwc the ph,ii dUQ'e ph,ln tfeh truCic kil'"n true eua chung: dc gOI phai dU\1C ph:111 tich truCK khi UU\K dan v1 thiet kc su' clL,mg. Trong ngon ngiJ' VIIDL co 11m vi~n Ihie't kc' d,~c hi';l eo tcn IZI "WORK". Khi chung la hien d!ch m61 cillwng Ir'inh viel tren ngt'm ngli VHDL nhung khong chi r6 thlf vi~n dtch, chucmg trlnh nilY sc dU\K bien d!ch Vi:I eh(ra vilO 11m vi¢n "WORK". Vi d~l, knh \iC My-Design.vhd sc ki~lll tra eu phap cillrung trinh ntun trong t¢p "My-Dcsign.vhd", d1eh L _B~9~p~h~a_n~1 -+ tfch _ [ j library-1 [IEEE - [ STD - WORK Thllv,en [ - omop ong VHDL 9 tong ap VHDL lIinh 6.10 So lui hie'll rlicn qllli lrinh bi':n dich va m6 phon12 Ili' cillt(/l1g trinh lhimh e<ic lhlr \'i~1l ella ngon ngfr VHDL. sal! d{) nle t!m "icil ~L: dU'(ie dli'<t \'ilO!J': me) p!JClIlS_ cillf(mg trlnh clo r()i ehlb vilo thu vi¢n "WORK". Illnh 6.10 chi ra de phU'o)lg thue slr cll;lllg cae Ihu' \'i~n thiet k~ trong ngon ngiI VHDL. l\gon llgU VHDL c6 ba di,mg d6i 1Lf9'llg: bien, tfn h~¢u \'il hi\ng, Phfl!l khai lxio lrung C{lC du truc ng6n ngCi so: h~t ke cac deli tWl'ng s2 Sif (iL,mg. CiIC klCll ella dc d6i IU'0ng do \'J. giii tri ban d:iu mil Ch(lllg sC nh(lll lrong qua trlnh I1H1 phcmg. 1. Cae d6i tut,mg du li~u Trong ngon ngCf VHDL nglf0i 1<1 p\},ln hi¢1 ha loai d6i 1lH,:ing dCi li~u: htlllg. hi~n \'~I tin hi¢u. Cac d6i 1L1l)'ng du'C)'c c1[\C 1<.1 dl,ra V:IO C<IC tlf kllOa. NhCing ILl kho{1 n:l)' rh~li xufit hi¢n 0 rhfln (HIU eua rlhin khai bao cloi tL19'ng. a. Han~ Htlllg b el6i Ilf9'ng dl!9'c khc)'i tao btl11g nhCing gia tr! nhfit djnh khi dl!0'C 1' 10 ntn trong qu<i Irinh thve hi~ll va sau d6 gi,i lri clla h,\ng khong lhay (h~i. Htlllg co the dL10c khai b{1O trong cUc gai. timc Ihe, kie'n truc, cillf(mg lrinh con. khoi Va qu'.l trlnh. Cll ph<.ip kiwi bao hung: constant {ell hiing . fhl hlillg I: kic'll 1;-::: i ;/(i fr! J: Vf d~l, constant CIIAR7 : BIT _ VECfOR ( 4 downtu 0) :-::: "00 III "; constant MSB: I~TEGER;::= 5; b. Bien Bien HI d6i tU(Jng du' li¢u dung d~ clitIa nhCfng kc', qU~l trung gian. Bien chi c6 the dm!c kiwi o.io ben Irong cac qua Idnh hO~lc chuang trinh con. Bien \uon eli doi \'6i kiC:u. do d6 bien rh,'ti dlt'(K kiwi baa kiC:u. xac d!nh khOi.lng gi{)'i h~lI1 hO~lc gia Ir~ kh{)'i I~\{) ban dall. M0t d.ch m~le d!nh, gi,i Ir! kh(')'j 1:,10 eLla hic'n El gicl trj thiip nhiit trang cae gici. trj thu(lC mit:n x.;ie dPlh ella ki6u. BiC:'ll eo Cli pllclP khai belo nhu sau. Vi d~l, Co Tin hiell variable Temp: ilIT_ VECTOR ( g duwnto 0 ) variahle Delay: INTEGER ran~e 0 to 15 :=0: Tin hieu l~l dtii w0ng du li¢u dung de ke't n6i gii!":l cae qua trlnh ho<)C d6ng b<,') de qu,i trinh. Khai 1xio tin hi¢u :0.13 1<.10 tin hi¢u 1116i c{) GIC gi l tl"! ella ki6u x.ie djnh. Tin hi¢ll c6 thc duqc khai b.lo tfOng ph,\n khai b,IO g6i ( khl d6 tin hi¢ll sc Iii tin hi~u tO~IJl Cl.IC ). khai b,io tlll!e th6 ( khi do tin hi¢u b tin hi~Ll toan CL.lc eLla tht!c the l. khai hao kicn tnk ( tin hi¢u sc 1;1 tin hl¢U tO~1l1 clie ella ki6n true) V;:I trung khai. Cae tin hi¢u c6 thc dU\K SLf dung nlurng k.h6ng the (ILrqe khai bao trong c:ic qu.i Idnh \';1 dc chu()'ng trlnh con. Co the gi,:ll thieh dieu n;IY nhu sau. dc qua trlnh va chuaHg trlnh con 1:1 Gte thanh ph.i]) e0 sa eua m6 hinh \'il. dU0e coi 1<'1 e.:ie hl)p den. Cite tin hi¢u -;c \;ic ch)ng V;IO c.ie ht)p elen do tv ben ngoi:li. Cae d.ip ung Cll.1 hl)p den SC (ll1h hU'l'mg de'll dlrCil1g tin hieu fa. Cic tin hieu c{l Cll phci.p k.hai b.io nhu' sau. signal Ikcp: BIT:= '0'; signal Res: INTEGER range 0 to Ion: 2. elK kiClI dj1 Ii~u M9i dai tut:mg dfr li¢u trong ng6n ngfr VHDL deu ph 'll dm:c d!llh nghia boi c le kicu di}' Ii¢u. Ng6n ngiJ VHDL eho phcp sir dYllg CilC kicll co sO de t, l0 ncn de doi tLr0ng pi1(fe t' lp han. 154 KiC;u ph<.ll du\1C khai h,ia tmoe khi Slr dl.lOg. Khai h<to kie'u x<tc c1inh t(:11 kitu vi\ mi6n x,\c dinh eua kieu. Cae khai baa kicu e6 the n:111l troug plHin khai b{lo cLla g6i. khai b,\o Ilmc th( klUli hell) kicn true. khai h,IO ehuD'llg !rlnh con vii kiwi b,.lO dc qu<.i trinh. Cae kicu dCr iL~u ehinh trong ngon ngCi: VHDL: Kicu ki¢1 kt. Kieu so nguyen Kicu du'CJe djnh nghia tru6c eua VHDL Kicu lm'tng K ieu h,in ghi Ki~u STD_LOGIC. SIGNED va UNSIGNED. Ck h~u con. a. Kicu Ij~t kc Kieu li¢t ke dmJe dPlh nghia hilllg c{IC!1 li¢t ke t[{1 Cli cae gia !rj e{) the e6 clla kicu. CeK gi<.t !rj nilY do nguoi Slr dl,lng x.ic dmil \'a c6 tile la c;ic kn hO;lc nhung ky' q.J'. OJ ph<.ip clla klCU li¢1 ke Trong ngon ngCi: VHDL kit'll li¢1 kt co (h~le diem kh;ie \,{1i kieu li('\ k0 eLlil de ngon ngiJ 1(lp trlnh khae. M{)i gi,i tri trong thimh ph[in ella kicu e6 tile xuii! hi¢n trong hai ho~\C nhicu hon kicu li¢t kt. Vi d~l, type Color is (Red, Orange, Ydlmv. Green, niue, Purple): type Light is ( Red, Y cllow, Green ): t~pc STD_LOOIC is CU', 'X', '0', '1', 'z', 'W', 'L', 'If, '.'J: yariahle X: Color: si~nal Y: STD_LOGIC: Tron o cae n"(ll1 l1"illap trlnh !ruven thOll", cae liet kc khong dU(1C phcp eo e e .• e . ~. ch(Ta nhCfng phan \\i gi6ng nhall. Trong VI dl,l tren, tmng cac ng6n ngiJ I,)p 1:')5 . iC My -Design. vhd sc ki~lll tra eu phap cillrung trinh ntun trong t¢p "My-Dcsign.vhd", d1eh L _B~9~p~h~a_n~1 -+ tfch _ [ j library-1 [IEEE - [ STD - WORK Thllv,en [ - omop. f(;/I_1Iu/C_lh(;" is pltci"ll_ khoi -& apos;h/O _Clio _ uilt-'u'nh fOI' title ,(/ oi(l kh()"i m(lIlr_d(use I { ((ic_pllltll 1/1 (11(1 C{]II-'Iillh I end for; Vi. component component Al'!D2_GATE purt ( 10. II , in IllT; 0; uut lllT ); end component: U L XOICGATE port map ( Ill. I I. S ); ]2, AND2JiATE port map (IO.lI. CO);