Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C024 Finals Page 502 9-10-2008 #17 502 Handbook of Algorithms for Physical Design Automation For example, the tree produced by the DBS group Steiner algorithm above (Figures 24.12 and 24.13) can be utilized as the starting point in the bounded-radius bounded-cost construction of Ref. [87]. For an arbitrary instance of the group Steiner problem (with k groups), this combination yields a routing tree with simultaneous provably good bounds for both tree radius and tree cost. In particular, the tree resulting from this merger will have radius (1 + ) times the optimal radius, and total cost (1+ 2 )·2·(2+ln k 2 )· √ k times the optimal cost, for any user-specified radius-cost trade-off parameter >0. 24.5.6 EMPIRICAL PERFORMANCE OF THE GROUP STEINER HEURISTIC The group Steiner heuristic above compares favorably with the RW heuristic proposed by Reich and Widmayer [80]. The RW group Steiner heuristic begins by first finding the MST T for the entire set of nodes of all the groups. If a leaf node is not the last member of its group in the tree T ,thenitmay be removed. The RW heuristic then repeatedly deletes such a leaf node that is incident to the longest edge among all such nodes. On random uniformly distributed pointsets with varying predetermined group areas, the DBS group Steiner algorithm described above significantly outperforms the RW algorithm, especially as the group sizes and the group areas increase [78,79]. 24.6 OTHER STEINER TREE METHODS Once it became known [48,49] that MST-improvement-based Steiner heuristics having worst-case performance bounds no better than the MST itself (i.e., 3 2 in the rectilinear plane), other rectilinear Steiner heuristics with average performance approaching that of I1S were subsequently proposed [88–94]. While it is generally difficult to analytically quantify the solution quality of heuristics, the I1S method was later proven to be the earliest Steiner approximation with a nontrivial performance ratio in quasi-bipartite graphs [55,56]. In 2003, Kahng et al. developed a highly scalable heuristic for computing n ear-optimal Steiner trees, based on the B1S approach [95]. This batched greedy algorithm (BGA) achieves its speed by combining greedy triple contraction [52,95] with a new linear size data structure for finding bottleneck edges [97]. The BGA can route in grap h-based uniform orientatio n geometries, in the presence of obstacles,andunder varyingviacosts, requiring onlyO(n) space and O(n log 2 n) time for n terminals. BGA can route noncritical nets with thousands of terminals within seconds of CPU time while maintaining h igh- solution quality (i.e., on par with that of B1S, about 11 percent improvement over MST cost for random instances). More recently, Ref. [98] developed an O(n log n)-time octilinear Steiner tree heuristic based on spannin g graphs, with performance and runtime similar to that of BGA. On another front, exact Steiner tree algorithms have also evolved r apidly in recent years [32,65], enabling exact solutions of large instances (u p to severalthousand points) within reasonable runtimes. However, the faster exact methods typically work only in two-dimensional geometric versions of the Steiner problem, where the underlying geometry can be carefully analyzed and h eavily exploited to reduce the size of the search space. Nevertheless, exact Steiner algorithms for the rectilinear plane have been optimized to the point of actually becoming practical for use on small pointsets in commercial applications. 24.7 IMPROVING THE THEORETICAL BOUNDS Berman and Ramaiyer [70] and Zelikovsky et al. [51,61,96] have developed several SMT heuristics similar to I1S, with approxima tion ratios substantially less than 3 2 . These methods were derived from the pioneering technique developed by Zelikovsky for the Steiner problem in graphs [52]. In particular, an algorithm with an approxim ation ratio of 11 8 in the rectilinear plane was given in Ref. [51]. These series of results have settled in the affirmative the longstanding open question of Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C024 Finals Page 503 9-10-2008 #18 Minimum Steiner Tree Construction 503 whether there exists a polynomial-time rectilinear Steiner heuristic with approximation ratio better than 3 2 . Subsequent work by Fößmeier et al. [96] has improved on the O(n 3.5 ) time complexity and 11 8 approximation bound of Ref. [51], with an O(n 1.5 ) implementation, where only a linear number of triples n eeds to be considered. The authors of Ref. [61] have shown that Zelikovsky’s algorithm has performance ratio between 1.3 and 1.3125, and that Berman and Ramaiyer’s algorithm has performance ratio at most 1.271; the latter algorithm can also be implemented to run in O(n log 2 n) time. A subsequen t algorithm achieved a rectilinear performance ratio of 1.267 time optimal within O(n log 2 n) time [72]. In a 1996 landmark result, Arora has established that Euclidean and rectilinear minimum-cost Steiner trees can be approximated arbitrarily close to optimal within polynomial time [99], set- tling the longstanding open question whether this is indeed possible. Arora’s methods also yield polynomial-time approximation schemes arbitrarily close to optimal for other combinatorial opti- mization problems, such as the Euclidean traveling salesman problem. Arora’s techniques were also used to achieve a polynomial-time approximation scheme for the rectilinear arborescence problem, with a performance bound arbitrarily close to optimal [100]. The performance bound of the g roup Steiner algorithm described above [78] was significantly improved in Ref. [79]. This was achieved by using d-stars rather than 2-stars, which improves the √ k factors in all the bounds of Section 24.5 to d · d √ k. Thus, the performance ratio of the DBS group Steiner algorithm (Figures 24.12 and 24.13) improved to O(k ) for arbitrarily small >0. In particular, a group Steiner tree with cost at most 2d ·[2 +ln(2k)] d−1 · d √ k time optimal is computed by this more general d-star-based group Steiner algorithm within O[τ + (|V|·k) d ] time, where τ is the time complexity of computing all-p airs shortest paths [79], k is the number of groups, and d is a user-selectable parameter that trades-off runtime against solution quality. A group Steiner heuristic with a polylogarithmic performance bound was more recently given in Ref. [101]. 24.8 STEINER TREE HEURISTICS IN PRACTICE While Steiner heuristics such as the I1S approach [19,58] yield highly accurate (i.e., near-optimal) solutions, industrial CAD applications sometime demand high runtime speed over solution quality. This is especially true, e.g., inside the inner loop of modern placement tools, where fast wirelength estimators are repeatedly invoked during the construction of timing-driven placements. In such sce- narios therefore, more accurate heuristics (e.g., the I1S approach) may be useful when the number of pins in a net is small (say, less than ten). On the other hand, when the number of pins grows into dozens or hundreds, more efficient heuristics such as those of Ref. [11] or [89] are more likely to deliver faster execution speeds. This motivated the recent development of progressively faster wirelength estimators such as the FLUTE algorithm of Ref. [102], whose speed derives from pre- computed table lookup. However,faster execution speeds typically come at a price, such as degraded solution quality, limitations on net sizes, restriction to specific metrics, etc. Careful empirical testing can determine which Steiner heuristics best suit a particular practical scenario and design regime. 24.9 FUTURE DIRECTIONS F OR THE S TEINER PROBLEM Chief among future research directions for the Steiner problem is finding general graph Steiner heuristics with improved performance bounds, i.e., smaller than the currently best-known bound of 1 + ln 3 2 ≈ 1.5493 times optimal of the loss-contracting algorithm (LCA) [55,56]. Steady improve- ments in this upper bound over the last 25 years progressed at an average rate of about 2 percent per year. Other special cases of the Steiner problem for special metrics, specific cost functions, and particular graph types may be explored separately, where it may be possible to exploit the underlying geometry to further improve the performance bounds. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C024 Finals Page 504 9-10-2008 #19 504 Handbook of Algorithms for Physical Design Automation Interestingly, the LCA algorithm is the first (and so far only) heuristic that works p rovably well for all of the special graph types discussed above. It would also be of interest to find a minimum α, such that for any β>α, there exists polynomial-time β-approximation of the general graph Steiner problem, as well as to improve the nonapproximability lower bounds, the best of which is currently 96 95 for general weighted graphs [75]. Group Steiner heuristics with improved approximation ratio are also of significant interest. It would be interesting to generalize Hwang’s theorem to high e r rectilinear dimensions [6]. It is known that Hwang’s ratio in any rectilinear dimension d is bounded from below by 2 − 1 d [49], and is also bounded from above by 2 for arbitrary metrics (including all rectilinear d dimensions). This leaves an open gap of size 1 d for Hwang’s spanning-to-Steiner ratio in rectilinear d dimensions. Generalizing Hanan’s theorem to λ-geometries seems to be more difficult than for th e rectilinear metric [42]. Mo reover, relatively little is known regarding generalization s of Hwang’s theorem to arbitrary λ-geometries (one unusual result along these lines is that the Steiner ratio in λ-geometries is not monotonic in the parameter λ [6]). More research is also needed to tighten both the upper and lower bounds for minimum-cost arborescences in graphs. Similarly, almost nothing is known about arborescences in three-dimensional rectilinearspace (or in any higher dimensions or alternative geometries). From a practical perspective, for any given fixed performance bound it would be useful to minimize the running times of the associated heuristics, and to quantify and explore various trade- offs between runtimes and solution quality. That a heuristic has a provably good performance bound does not automatically imply that its solutions are necessarily superior to those of a heuristic with a worse (or no) bound (because in practice, actual solutions of the various heuristics are rarely as bad as the theoretical bound would suggest; in fact, solutions produced by most reasonable Steiner heuristics are on average within a few percent of optimal for most random instances). Thus, it would be very useful to undertake research that would bring theory into closer alignment with practice. Along similar lines, additional research is needed to implement various heuristics (e.g., Arora’s algorithm [ 99]) and benchmark their practical runtime and emp irical solution quality. The fast- Steiner code for the BGA scalable implementation of the provably good heuristic of Ref. [61] is freely available from the authors of Refs. [95,97]; it would be interesting to see how future heuristics fare against this method. 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Sze CONTENTS 25.1 Introduction 509 25.2 Wirelength-Radius Trade-Offs 510 25.3 Steiner Arborescences 513 25.4 Elmore Delay-Based Routing Constructions 520 25.5 Non-HananInterconnectSynthesis 522 25.6 Wire sizing 529 25.7 Nontree Routing 529 25.8 Discussion and Future Research Directions 530 Acknowledgment 530 References 530 25.1 INTRODUCTION In this chapter, we address performance-driven interconnect synthesis, which seeks to optimize circuit performance by minimizing signal delays to critical sinks. Timing-driven wiring geometries are in general quite different from optimal-area (i.e., Steiner) in terconnect trees, especially as die sizes continue to grow while feature dimensions steadily shrink. ∗ The exposition below focuses on selected approaches to performance-drivenrouting, and details key historical research developments that helped usher in the era of high-performance interconnect synthesis. For extensive surveys on this subject, see Refs. [19,20]. For a g eneral overview of computer-aided design (CAD) of very large scale integrated (VLSI) circuits, see some of the classical textbooks [21–25]. As transistor sizes continued to dramatically shrink while their switching speeds have increased into the multigigahertz range, the circuit perform ance bottlenecks migrated from the devices them- selves to the wires that interconnect them. Indeed, it was observed in the late 1980s that given the VLSI scaling trends at that time, interconnection delay was already contributing up to 70 percent of the clock cycle in circuits [26–28]. Performance-driven layout design thus started to receive much research attention, especially timing-driven placement, which has a particularly significant effect on signal delays [27–32]. However, during that early era in the evolution of VLSI CAD, routing solutions were typically not available during the placement phase. Performance-driven methods of This work was supported by a Packard Foundation Fellowship, by National Science Foundation Young Investigator Aw ard MIP-9457412, and by NSF grants CCR-9988331, CCF-0429737, and CNS-0716635. ∗ In routing noncritical nets (or sinks), rather than optimize delay we instead seek to minimize ov erall wirelength, an objective that gives rise to variants of the classical Steiner problem [1–10]. On the other hand, modern ultra-deep-submicron VLSI CAD seeks to optimize and trade-off v arious combinations of objectives and criteria, such as delay, ske w, a rea, density, manufacturability, reliability, power, electromigration, parasitics, noise, and signal integrity [11–18]. 509 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C025 Finals Page 510 29-9-2008 #3 510 Handbook of Algorithms for Physical Design Automation the early 1990s therefore used simple (e.g., geometric or linear) estimates of interconnection delay to drive the placement process, sacrificing modeling accuracy in favor of computation al tractab ility. For a given timing-driven placement, a corresponding timing-driven routing seeks to minimize source-to-sink signal delays. To optimize circuit performance, early timing-driven routing methods relied on, e.g., net priorities [22], static timing analysis [33], hierar c hical approaches [34], and A ∗ search [35]. Since the early 1990s, there has b een a steady shift from technology-independent rout- ing methodologies to technology-dependent interconnect synthesis. Analyses of the Elmore delay formula [36] for distributed RC trees [37–39] motivated cost-radius trade-offs that depended on the underlying technology [40–44]. Thus, routing tree constructions that were based on various tech- nology parameters, net criticalities, and other timing or perform ance issues provided improvements over the previous static, technology-oblivious methods [16]. Several early works abandoned the algorithmic convenience and analytic simplicity of classical geometric objectives, and began to address the less tractable but more realistic actual delay. For example, an early sequence of p apers by Boese et al. [12,45–47] proposed new classes of delay objectives, along with improved-perfor mance routing algorithms that directly optimized , e.g., the Elmore delay. These works also established the fidelity of Elmore-based constructions relative to accurate delay simulators (e.g., SPICE) [16]. That is, it was observed that optimizing the Elmore delay tends to also minimize real delay. In parallel with these advances,sink-dependent delay objectives were recognized as more critical than net-dependentdelaym inimization. Becausethetiming-driven placementandrouting designloop usually iterated tightly with static timing estimation, critical-path in formation was often available during routing. Thus, formulations that optimized delays with respect to a set of critical sinks proved more effective than formulations that optimized delays in individual nets while ignoring the critical sinks [16]. The near-optimality of minimum-delay routing heuristics was also quantified empirically, showing, e.g., that certain simple heuristics achieved almost optimal critical sink delays [12,16, 47,48]. Other advances in timing-driven interconnect synthesis for improving circuit performance includedvariousapproaches to wire sizing, non-Hananrouting, nontreetopologies,and arborescence trees. The remainder of this chapter discusses some of these topics and techniques in greater detail. 25.2 WIRELENGTH-RADIUS TRADE-OFFS Researchers in interconnect synthesis observed that while low-wirelength routing trees have smaller capacitance-related delays, low-radius interconnects have shorter pathlength-related signal propa- gation delays [16]. ∗ However, there exists an inherent conflict b etween these two objectives (i.e., minimizing overall tree cost versus minimizing source-to-sink pathlengths), and when one of these two objectives is optimized, the other objective typically suffers (Figure 25.1). Indeed, shortest paths trees (i.e.,those produced by Dijkstra’s classical algorithm [57]) have thebest possiblesource-to-sink pathlengths but usually induce high overall tree cost (Figure 25.1a). On the other hand, minimum spanning trees (i.e., those produced by Prim’s classical algorithm [58]) have optimal tree cost but produce potentially high source-to-sink p athlengths (Figure 25.1b). To simultaneously optimize both the routing tree radius as well as its cost, the f ollowing formulation was proposed [59]: The Bounded-Radius Minimum Routing Tree Problem: Given a parameter ≥ 0 and a signal net with radius R, find a minimum-cost routing tree T with radius(T) ≤ (1 + ) ·R. ∗ We define the radius of a routing tree/topology to be its maximum source-to-sink pathlength, and its cost to be its total wirelength. Similarly, the radius of a net is defined as its farthest source-to-sink distance. Distances and wirelengths are usually measured using the Manhattan/Rectilinear norm, although alternative interconnect architectures with more complicated underlying metrics ha ve recently become popular, such as preferred direction routing and λ-geometries [2,49–56]. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C025 Finals Page 511 29-9-2008 #4 Timing-Driven Interconnect Synthesis 511 (a) (b) (c) FIGURE 25.1 Candidate interconnection trees for the same net, where the signal source pin is located at the center a nd the sinks are located on the circumference of a circle: (a) shortest paths tree, (b) minimum spanning tree, and (c) low-cost low-radius trade-off hybrid tree. The user-specified parameter controls the trade-off between the competing minimum-radius and minimum-cost objectives. Setting = 0 induces a minimum-radius (i.e., shortest paths) tree, while increasing loosens the radius restriction, thus allowing further tree cost optimization. At the other extreme, setting =∞results in a minimum-cost spanning tree. Note that these definitions and formulations easily generalize from spanning trees to Steiner trees (i.e., where new points/vias may be added to further optimize total wirelength). However, in performance-driven layout, where a fast delay estimator is employed in a tight iterative design loop, spanning trees are typically easier to compute than Steiner trees. Moreover, a spanning tree can usually be easily converted into a corresponding Steiner solution (e.g., by edge-overlapping),without disimproving its original radius. The earliest heuristic to solve the Bounded-Radius Minimum Routing Tree (BRMRT) problem was the bounded-Prim (BPRIM) approach of Refs. [43,59], which follows the general structure of Prim’s minimumspanning tree (MST) algorithm [58]. Although simple to implementandeffective in practice over typical inputs, this approach can produce trees with cost arbitrarily larger than optimal in the worst case. Shallow-lighttree constructionsavoid such worst-case scenarios by simultaneously bounding both the worst-case radius and the worst-case cost of the resulting routing tree [41–44]. The basic approach of algorithms such as the bounded-radius bounded-cost (BRBC) method [43] is as follows: (1) traverse a minimum spanning tree in depth-first order, (2) insert additional edges whenever the prescribed radius bound is violated, and (3) return the shortest paths tree over the resulting graph (Figure 25.2). The BRBC algorithm produces a tree with radius at most (1 + ) times optimal, and cost at most (1 + 2 ) times optimal [16,43]. The BRMRT problem formulation and the BRBC algorithm generalize to regimes where we seek a low-radius tree that spans a vertex subset in an underlying graph, while using the remaining graph vertices as potential Steiner points to minimize the overall interco nnection cost. Note that when =∞, the classical graph Steiner problem is a special case of this generalization. A BRBC Steiner analogue first constructs an approximate minimum-cost Steiner tree T that spans the target vertex subset, and then proceeds with the remaining radius-minimization optimization as before. This will yield a routing tree with radius bounded by (1 + ) times optimal, and cost bounded by (1 + 2 ) times the cost of T. Note that the cost of the heuristic Steiner tree T can itself be bounded by a constant times optimal. For example, if we use the best-known general graph Steiner heuristic of Robins and Zelikovsky [10,60] that has an approximation bound of 1 + ln 3 2 ≈ 1.5493 times optimal for arbitrary weighted graphs, then the resulting Steiner-BRBC tree cost bound will be (1 + ln 3 2 ) ·(1 + 2 ) times optimal for general graphs. The underlying geometry can be exploited to further improve the cost bound of Steiner-BRBC to 2 ·(1 + 1 ) times optimal for any metric. In particular, for the Manhattan and Euclidean geometries, this general bound can be further improved to 3 2 · (1 + 1 ) times optimal . Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C024 Finals Page 502 9-10-2008 #17 502 Handbook of Algorithms for Physical Design Automation For example, the tree. improve the performance bounds. Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C024 Finals Page 504 9-10-2008 #19 504 Handbook of Algorithms for Physical Design Automation Interestingly,. [11–18]. 509 Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C025 Finals Page 510 29-9-2008 #3 510 Handbook of Algorithms for Physical Design Automation the early 1990s therefore used