Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C007 Finals Page 132 24-9-2008 #25 132 Handbook of Algorithms for Physical Design Automation 7.5.3 NEW INNOVATIONS IN MULTILEVEL PARTITIONING With increasing design sizes, it is becoming increasingly difficult to place an entire design f lat using one processor. A novel partitioning approach [Ma07] is applied to placement such th a t the computing effort is spread across several processors. The approach consists of a rough initial flat placement, a partitioning step, followed by detailed placement within the partition blocks where each block is assigned to its own processor.The novelty of this technique lies in the way the blocks are determined. Normally, an engineering change in one block will affect all other blocks. However, this is not the case if the block boundary is determined by elements such as latches, flip-flops, or fixed objects. Once these objects are identified,block boundariesthat minimizethe number ofnets runningbetween blocks are determined. Finally, detailed placement is applied to blocks, each block assigned to its own processor. 7.6 CONCLUSION This chap ter has presented a historical survey of partitioning and clustering techniques ranging from move-based methods to multilevel techniques to mathematical formulations including quadratic, linear, and integer programming approaches. Multilevel methods have proven to be the partitioning technique of choice in the VLSI community owing to the quality of results they produce with very small ru ntimes. A consequenc e of which is that par titioning is currently viewed as a solved pro blem. However, as problem sizes continue to increase, multilevel partitions may no longer be near optimal. Recent works [Ma07] revisit the partitioning pro blem and offer new solutions for very large-scale netlists. ACKNOWLEDGMENTS I would like to thank my colleagues, especially Ulrich Finkler and Chuck Alpert for giving their comments and suggestions, and James Ma for helpful discussions regarding new innovations in multilevel p artitioning. REFERENCES [ACKM00] C. J. Alpert, A. E. Caldwell, A. B. Kahng, and I. L. Markov, Hypergraph partitioning with fixed vertices, IEEE Transactions on C o mputer-Aided Design of Circuits and Systems 19(2): 267–272, 2000. [AHK96] C. J. Alpert, L. W. Hagen, and A. B. Kahng, A hybrid multilevel/genetic approach for circuit partitioning, Proceedings of the Physical Design Workshop, 1996, Reston, VA, pp. 100–105. [AHK97] C. J. Alpert, J. -H. Huang, and A. B. Kahng, Multilevel circuit partitioning, Proceedings of the ACM Design Automation Conference, Anaheim, CA, 1997, pp. 530–533. [AK93] C. J. Alpert and A. B. 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Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C007 Finals Page 136 24-9-2008 #29 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_S003 Finals Page 137 24-9-2008 #2 Part III Floorplanning Alpert/Handbook of Algorithms for Physical Design Automation AU7242_S003 Finals Page 138 24-9-2008 #3 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C008 Finals Page 139 29-9-2008 #2 8 Floorplanning: Early Research Susmita Sur-Kolay CONTENTS 8.1 Introduction 139 8.2 Floorplan Topology Generation 140 8.3 Rectangular Duals 141 8.3.1 Dualizability 142 8.3.2 Slicibility of Rectangular Duals 145 8.3.2.1 Four-Cycle Criterion for Slicibility of a Floorplan 146 8.4 Nonslicibile Floorplan Topologies 147 8.4.1 Maximal Rectangular Hierarchy 147 8.4.2 Inherent Nonslicibility 148 8.4.3 Canonical Embedding of Rectangular Duals 149 8.4.4 Dualization with Rectilinear Modules 150 8.5 Hierarchical Floorplanning 151 8.6 Floorplan Sizing Methods 153 8.7 Analytic Sizing 154 8.8 Branch-and-Bound Strategy for Sizing 156 8.9 Knowledge-BasedFloorplanningApproaches 157 8.10 Unified Method for Topology Generation and Sizing 158 Acknowledgments 158 References 158 8.1 INTRODUCTION In physical design, floorplanning determines the topology of the layout, i.e., the relative positions of modules on the chip, based on the interconnection requirements of the circuit and estimates for area. A floorplan can provide a guideline in the detailed design of functional modules or blocks when the aspect ratios and pin positions of some of the modules on the chip are still unconstrained. Thus, floorplanning is important not only for physical design, but even more for choosing design alternatives in the early stages that are likely to produce optimal designs. Placement was originally seen as a special case of floorplanning where the sizes and shapes of all the modules are known. In the history of computer-aided design (CAD) for very large scale integration (VLSI) circuits, the placement problem was addressed both for printed circuit boards as well as large scale integration (LSI) circuits. With the rapid increase in the scale of integration, the role of floorplanning came into the picture, particularly for the custom layout design style with variable width and height of modules. Some of the major techniques that were originally proposed for placement have subsequently been tailored for floorplanning. 139 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C008 Finals Page 140 29-9-2008 #3 140 Handbook of Algorithms for Physical Design Automation The most significant difference between floorplanning and placement is in the modeling of the cells or modules. ∗ The extra degree of freedom in floorplanning, arising from the flexibililty of the interfaceand shapeof modulesthat constitutethe design, enlarges the portion of the chip available for placing the components. The floorplanning algorithm may have to deal with three types of modules: modules from a library with design and interface fixed, modules with known design but flexible layout, and modules with designs not completely known or certain. With respect to the physical design flow, area estimation also has to handle all these three types of modules. Floorplanoptimization has conventionallybeen achieved by twosteps: (1) feasible topology gen- eration and (2) sizing (determining the aspect ratios of the rectangular modules to optimize objective functions such as chip area, total wirelength, etc.). Topology generation focuses on computing the relativelocations of modulesbased on their interconnectionswithout restriction on theirexactshapes; an estimate of the area of each module may however be known. The sizing step then determines the shape, i.e., the aspect ratio of a module in tune with that of its neighbors to attain a globally optimal floorplan solution. This chapter concentrates on the early approaches to the floorplanning phase in the contextoff ull- custom design or semicustom design styles such as building blocks, standard cells, and gate arrays. The early floorplanning methods may be classified into constructive, iterative, and knowledge-based techniques. Constructive algorithms are primarily used for topology generation and are discussed in Sections 8.2 through 8.5. Iterative techniques, on the other hand, mainly tackle the second task of floorplanning, namely sizing, and are discussed in Sections8.6 through 8.8. Knowledge-based approaches [1–4] are considered in Section 8.9 and algorithms for a unified approach to topology generation and sizing are sketched in Section 8.10. 8.2 FLOORPLAN TOPOLOGY GENERATION Some of the commonly used ter ms in floorplanning literature are defined first. For graph-theoretic terminologies used without definition in this chapter, the reader is referred to an appropriate text (e.g., Ref. [5]). A floorplan is a rectangle dissection of an enveloping rectangle by horizontal (parallel to x-axis) and vertical (parallel to y-axis) line segments, termed cuts, into a finite number of indivisible nonoverlapping rectangles (Figure 8.1a and b), which correspond to the modules in the floorplan. If the exact shape of the modules are not considered, then such a rectangledissection depicts a floorplan topology. A floorplan with n cuts has exactly n +1 modules. Conventionally, two perpendicular cuts are allowed to meet to form T-junctions only, but not a cross (+). (a) (b) (c) a b c d e f g h a b c d e f g h a b c d e f g h FIGURE 8.1 (a) Slicible floorplan F s , (b) nonslicible floorplan F n , and (c) both floorplans have the same adjacency graph R. ∗ In the context of this handbook, placement is defined as the narrower problem of placing standard cells (each cell h as the same height) in rows. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C008 Finals Page 141 29-9-2008 #4 Floorplanning: Early Research 141 A floorplan is slicible if its rectangular dissection can be obtained by recursively divid- ing rectangles into smaller rectangles until each nonoverlapping rectangle is indivisible. Slicible floorplans (Figure 8.1a) are also termed slicing structures, or simply slicings. All floorplans may not be slicible (Figure8.1b). A summary of the major approaches to topology generation is presented next. 1. Slicing embedding [6,7]: This is a constructive method generating a special type of flo orplan only. A point embedding is first determined by relying on the netlist information. The relative positions of the modules are depicted in the form of a slicing tree or equivalently a series-parallel polar graph [8]. Then a floorplan is obtained in polynomial time by cutting the embedding into a slicing structure as th e slicing tree is traversed appropriately. The approach neglects the actual building block dimensions. Additional discussions on slicings appear in Chapters 2 and 9. 2. Partitioning and slicing [9–11]: The divide-and-conquerapproach is employed by adapting a mincut approach (details appear in Chapter 15) for the placement of building blocks [9] to the floorp lanning problem. In the Mason system [10], mincut bipartitioning is combined with the slicing tree representation in an effort to ensure routability. Global improvement of a partition is obtained by in-place partitioning based on the slicing tree. A scheme for global channel assignment and I/O pin assignment aids in floorplan evaluation. The system provides an interactive environment and can act as a human designer's assistant. 3. Dual graph method [12–15]: Among the most important floorplanning paradigms, the dual graph method of floorplanning deserves special mention. This is a constructive method based on graph algorithms. The topology of the modules is extracted from the adjacency relationswith respectto circuitinterconnections,givenasa neighborhoodgraph.Atfirst, this graph is planarized by deleting a minimum number of connections and adding crossover vertices. Then the optimal rectangular dual is sought for the planar graph. Rectangular dualization is of particular interest because of its algorithmic efficiency and the fact that the components are guaranteed to have rectangular layout. It emphasizes the proximity of heavily connected modules. A performance-driven version [15] was designed, where a dual is first generated considering routing constraints and then compacted by a linear programming-based heuristic method. A significant amount of research has been carried out on the dual graph method, including extension to rectilinear modules. The next section elaborates on many elegant results on rectangular dual floorplans. 4. Hierarchical enumeration [16]: This method falls into the group of connectivity clustering methods; the basis is circuit connectivity. For clusters of cells, floorplan templates having simplified topologies are used. Recursion is applied to obtain floorplan for large, com- plex circuits. There is a limit on the number of rectangular, arbitrary-sized blocks at each hierarchy level to enable simple pattern enumeration and exhaustive search later on. The novelty of this approach is that information about global routing can be maintained during floorplanning. The details of hierarchical floorplanning appear later in Section 8.5. 8.3 RECTANGULAR DUALS A floorplan generated by rectangular dualization is often referred to as a rectangular dual. Given such a floorplan F, a rectangular graph R = (V, E) representing the adjacency of modules in F has a vertex for each module and an edge (u, v) ∈ E if and only if the modules denoted by vertices u and v are adjacent (i.e., share a common boundary). The graph R is also known as the adjacency or neighborhood graph [12,17]. For a given floorplan, a unique rectangular graph always exists, but the converse is not necessarily true as illustrated in Figure 8.1, where both the floorplans have the same rectangular graph of Figure8.1c. Although there may be exponentially many different rectangular . Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C007 Finals Page 132 24-9-2008 #25 132 Handbook of Algorithms for Physical Design Automation 7.5.3 NEW INNOVATIONS IN MULTILEVEL PARTITIONING With. #29 Alpert /Handbook of Algorithms for Physical Design Automation AU7242_S003 Finals Page 137 24-9-2008 #2 Part III Floorplanning Alpert /Handbook of Algorithms for Physical Design Automation AU7242_S003. 17(11): 219– 229, 1970. Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C007 Finals Page 134 24-9-2008 #27 134 Handbook of Algorithms for Physical Design Automation [HHK97] L. Hagen,