Nicolescu/Model-Based Design for Embedded Systems 67842_C021 Finals Page 706 2009-10-2 706 Model-Based Design for Embedded Systems Y values S (test_acc2_5vl : yacc:a_in) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 EMF (V) Time (s) 2.5 m 2.0 m 1.5 m 1.0 m 0.5 m 0.0 m –0.5 m –1.0 m –1.5 m –2.0 m –2.5 m 0.0 m 10.0 m 20.0 m 30.0 m 40.0 m 50.0 m 60.0 m 70.0 m 80.0 m 90.0 m 100.0 m 110.0 m S (test_acc2_5vl : yacc:v_out) FIGURE 21.7 Simulation of the accelerometer behavioral model. • The mathematical model describes the accelerometer as a mass-spring system. It applies the Newton’s second law, which also deals with the damping force. Again, the constants used have been obtained through experimental measurement and known physical values. This model shows the possibilities of VHDL-AMS of solving differential equations. 21.5.2 Output Circuitry The output circuitry of the accelerometer can be treated separately in two parts. The first one is the signal conditioning circuitry based on Chopper stabilization (CHS), so it amplifies the signal and eliminates the noise. The second part consists of a sample and hold (SH) device and an ADC, and makes possible the connection of the sensor to a digital device. The entire system scheme can be seen in Figure 21.8. First, we address the signal conditioning circuitry. The operation princi- ple in CHS is to avoid low level noise by moving the signal to higher fre- quencies and restoring it to its original frequency once amplified. The output voltage of the accelerometer reaches the first modulator, so it is transferred to the frequency imposed by the oscillator. The next step is to amplify the signal and pass through a band-pass filter, in order to eliminate undesirable signals. Nicolescu/Model-Based Design for Embedded Systems 67842_C021 Finals Page 707 2009-10-2 Smart Sensors Modeling Using VHDL-AMS 707 ADC V out A Oscillator V in Input modulator Pre- amplification Passband filter Output modulator Low pass filter Buffer Sample and hold CHS ×1 FIGURE 21.8 Accelerometer output circuitry. Finally, the second modulator and the low-pass filter restore the original fre- quency signal. The signal conditioning circuitry is composed of two modulators (input/output, which are controlled by an oscillator signal), a preamplifi- cation, a band-pass filter, an oscillator, a low-pass filter (40 dB/decade and 10 kHz Butterworth filter), and a frequency divider. The oscillator is composed of an astable multivibrator (square-wave generator) and a comparator. It was designed to obtain the filter resonance frequency and oscillator frequency as closely as possible. The frequency of oscillation is defined by the relation between R 0 and R 1 (see Figure 21.9) and presents a value of 110 kHz. In spite of developing this model according to its schematic, its simulation has not been successful because it is impossible to define initial conditions on the simulator. For the global system simulation, a behavioral model of the oscillator has been used (Figure 21.10). The modulator is composed of different logic gates (see Figure 21.11) and provides two square signals with the frequency of the oscillator, with a delay of 180˚ between them. The preamplifier presents a gain of 100 dB, and it is composed of a differ- ential amplifier with two amplification stages (see Figure 21.12). The low-pass filter is a differential filter based on a 40 dB/decade But- terworth filter. The cutoff frequency of the filter is 10 kHz, and the model developed and the simulation results of the filter can be seen in Figures 21.9 and 21.10. The band-pass filter is a differential filter based on a narrow band’s band- pass filter (see Figure 21.13). The most important characteristics are the res- onance frequency of 110 kHz, which is the frequency of the oscillator, and a 40 kHz bandwidth. These features can be seen in the results shown in Figure 21.14. For this simulation, the behavioral description of the accelerometer has been used as excitation signal. As can be seen in Figure 21.15, the output signal has a linear relation with the input signal, and amplifies it in two orders of magnitude. Nicolescu/Model-Based Design for Embedded Systems 67842_C021 Finals Page 708 2009-10-2 708 Model-Based Design for Embedded Systems + 3 – 2 V+ 8 V– 4 Out 1 U2A + 3 – 2 V+ 8 V– 4 Out 1 R 0 _1 R1_1 R 1 R 1 R 0 R 0 C 0 C 1 V out 2 V out 1 ref V in + V in – V dd C 1 C 1 FIGURE 21.9 Schematic corresponding to the low-pass filter. Next step is to model the second part of the output circuitry, which con- sists of an SH circuit and an ADC. Between these elements and the amplifier output circuitry simulated before, a simple buffer had to be added to make the offset levels compatible. The SH circuitry is based on a simple design with only one capacitor, where the sample is controlled by a switch and its clock signal. The converter operation is controlled also by a clock signal, which is the clock signal used by the IBIS bus. Its simulation can be seen in Figure 21.16, where the transformation of analog data to digital data is shown. The synchronization between the IBIS and these elements is achieved through an interface, which allows the connection between the digital and the analog parts of this smart sensor. In Figure 21.16 the first signal shown is the excitation signal, followed by the same signal sampled, and finally intermediate signals that synchro- nize both elements. The command signal governs the beginning of the data capture, which finishes when the d out signal takes a value. 21.5.3 IBIS Drivers All the developed IBIS drivers have a similar inside structure. The bus codi- fication is done in Manchester encoding, this allows a better transmission and its synchronization, but has the drawback of making the driver slightly more difficult to develop. The drivers are necessary to connect the slaves with the master of the bus, and they all are formed by different modules that Nicolescu/Model-Based Design for Embedded Systems 67842_C021 Finals Page 709 2009-10-2 Smart Sensors Modeling Using VHDL-AMS 709 0.0 VDB (test_1p : v_out1) VDB (test_1p : v_out2) VP (test_1p : v_out1) VP (test_1p : v_out2) –20.0 –40.0 –60.0 –80.0 –100.0 –120.0 –140.0 –160.0 –180.0 –200.0 –220.0 –50.0 –100.0 –150.0 –200.0 1.0e + 3 Phase (degrees) Magnitude (dB) 1.0e + 4 23456 1.0e + 5 23456 1.0e + 6 Frequency (Hz) 23456 1.0e + 7 23456 1.0e + 8 23456 1.0 23456 200.0 150.0 100.0 50.0 0.0 FIGURE 21.10 Results obtained for the low-pass filter. Nicolescu/Model-Based Design for Embedded Systems 67842_C021 Finals Page 710 2009-10-2 710 Model-Based Design for Embedded Systems NOR2 1 2 3 NOR2 1 2 3 INV 12 INV 1 2 INV 1 2 INV 1 2 INV 1 2 1n C2 1n clk1 clkin clk2 FIGURE 21.11 Schematic corresponding to the modulator. – 2 + 3 V– 11 Out 1 V+ 4 – 2 + 3 V– 11 Out 1 V+ 4 – 2 + 3 V– 11 Out 1 V+ 4 – 2 + 3 V– 11 Out 1 V+ 4 R 5 R 6 R 7 R 8 R 9 R 10 V dd V dd V dd V dd V in – V in + V out – V out + FIGURE 21.12 Schematic corresponding to the preamplifier. comprise different functions, as for example, a fragmentation module, a Manchester encoding module, a Manchester decoding module, a module of frame formation, and all the involved mechanisms for the appropriate bus interaction. Examples of the later are the frequency divider or the intern buffers, to ensure that the data is not lost. Furthermore, the bus, because of its drivers, allows hot plugging and plug and play mode [9,10]. Nicolescu/Model-Based Design for Embedded Systems 67842_C021 Finals Page 711 2009-10-2 Smart Sensors Modeling Using VHDL-AMS 711 R 1 R 2 R 3 R 4 C 3 C 4 C 5 C 6 V out + V in + V out – V in – R 1 R 1 V dd V dd Ref – 2 + 3 V– 11 Out 1 V+ 4 U11A – 2 + 3 V– 11 Out 1 V+ 4 FIGURE 21.13 Schematic corresponding to the band-pass filter. For easier design, all has been included in one single IP. Each device has a physical address programmed in it, and, as it has been said before, an IBIS can have up to 31 slaves. In Figure 21.17 we can observe the structure of a connection between the driver and the master of the bus; the shaded part depicts the IBIS driver. 21.5.4 Interface of the Accelerometer To enable the connection between the digital part IBIS and the sensor, it is necessary to introduce an interface. Its main function is to receive commands from the IBIS and to synchronize the data acquisition according to these com- mands [11]. While not receiving any command or when itreceives the reset command, the state of the system does not change. However, when the IBIS sends a command signal, the interface sends signals to the SH and the ADC to begin the data acquisition. The SH holds the signal while the ADC converts it to digital data. When conversion is finished, the ADC informs the interface and sends the digital data. The interface transmits the data to the IBIS bus and proceeds to wait for new commands. 21.6 Gyroscope Similar to the accelerometer, the assembled gyroscope itself can be consid- ered a smart sensor, since it is prepared to be connected to a digital device Nicolescu/Model-Based Design for Embedded Systems 67842_C021 Finals Page 712 2009-10-2 712 Model-Based Design for Embedded Systems VDB (test_bp : v_outp) VDB (test_bp : v_outn) VP (test_bp : v_outn) VP (test_bp : v_outp) –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 –100.0 160.0 140.0 120.0 100.0 80.0 60.0 40.0 20.0 0.0 –20.0 –40.0 –60.0 –80.0 –100.0 –120.0 –140.0 –160.0 0.0 Magnitude (dB)Phase (degrees) 1.0e + 3 23456 1.0e + 4 23456 1.0e + 5 23456 1.0e + 6 23456 1.0e + 7 23456 1.0e + 8 1.0 23456 Frequency (Hz) FIGURE 21.14 Results obtained for the band-pass filter. Nicolescu/Model-Based Design for Embedded Systems 67842_C021 Finals Page 713 2009-10-2 Smart Sensors Modeling Using VHDL-AMS 713 2.5 m 2.0 m 1.5 m 1.0 m 0.5 m 0.0 m –0.5 m –1.0 m –1.5 m –2.0 m –2.5 m 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 EMF (V) EMF (V) S (test_sha: ylmea :out1: vindif)S (test_shad : ylmea:out1: voutacc) 0.0 m 2.0 m 4.0 m 6.0 m 8.0 m 10.0 m 12.0 m 14.0 m 16.0 m 18.0 m 20.0 m 22.0 m 24.0 m 2 Time (s) FIGURE 21.15 Simulation results obtained for the output circuitry. without the need to solve compatibility issues. Its structure is similar to the accelerometer, except that instead of the CHS amplification, the signal pro- cessing circuitry recommended by the manufacturer has been utilized. The smart sensor schematic is shown in Figure 21.18. The sensor employed is a gyroscope based on piezoelectric effects. It con- tains a ceramic bimorph vibrating unit, whose operating principle consists of the detection of the rotational motion from the generated Coriolis force. The ceramic material makes the bar vibrate, so when a rotational motion takes place, a Coriolis force is generated perpendicular to the original direction of vibration. This force is detected by other piezoelectric ceramics. The conditioning signal circuitry contains a high-pass filter with a cutoff frequency of 0.3 Hz, and a low-pass filter with a cutoff frequency of approx- imately 1 kHz. To adapt this signal to the SH and ADC devices, a condition- ing module has been added whose main objective is to amplify the signal to the range admitted by the ADC, and to make the offset levels compatible. This is achieved by means of a Zener diode and an operational amplifier. Its schematic can be seen in Figure 21.19. In order to connect the gyroscope to the IBIS bus, the same interface developed for the accelerometers has been used. The only difference between the interfaces is the address of which the sensor begins the acquisition. Nicolescu/Model-Based Design for Embedded Systems 67842_C021 Finals Page 714 2009-10-2 714 Model-Based Design for Embedded Systems V (test_shad : ylmea :v3) 3.2240 3.2235 3.2230 3.2225 3.2220 3.2215 3.2210 3.2205 3.2200 3.2195 3.2190 3.2185 (a) (b) EMF (V) V (test_shad : ylmea :v4) 3.2240 3.2235 3.2230 3.2225 3.2220 3.2215 3.2210 3.2205 3.2200 3.2195 3.2190 3.2185 EMF (V) 0 xxxx 000 + + + + + + + + + + + + + + + + + + + + + + 49.27 m 49.28 m 49.29 m 49.30 m 49.31 m 49.32 m Times (s) 49.33 m 49.34 m 49.35 m 49.36 m test_shad: ylmea: command test_shad: ylmea: start test_shad: ylmea: eoc test_shad: ylmea: dout test_shad: ylmea: clk2 (c) FIGURE 21.16 Simulation of the signal capture. Sensor Analog interface Converter Bus interface Controller Bus FIGURE 21.17 Structure: Sensor + IBIS driver + controller. 21.7 Smart Sensor Simulation 21.7.1 IBIS Drivers in Sensors All the sensors and actuators need a specific driver to function properly, while the driver also implements the interface function with the dedicated Nicolescu/Model-Based Design for Embedded Systems 67842_C021 Finals Page 715 2009-10-2 Smart Sensors Modeling Using VHDL-AMS 715 S&H + ADC Output circuitry Gyroscope Signal processing circuitry Interface IBIS FIGURE 21.18 Gyroscope smart sensor schematic. V in V ref High-pass filter Low-pass filter Amplifier Amplifier stage Sample and hold ADC V out FIGURE 21.19 Gyroscope output circuitry. bus sensors by containing the communication protocol. The implementation of the drivers has been developed in VHDL. The result has been validated in an FPGA, and the resulting IP model will be used in future developments based on the same bus sensor application. Two parts compose each driver: (a) the one for the specific communication with the sensor or actuator and its additional signal processing circuitry (this part is specific for each sensor, because it depends on the nature of it), and (b) the one that implements the communication bus protocol itself. These drivers are necessary to connect the slaves with the master of the bus and they are composed of different modules such as a fragmentation module, a Manchester encoding module, a Manchester decoding module, a module of frame formation, and all the involved mechanisms for a good operation of the bus. As an example we can mention the frequency divider or the intern buffers, to ensure that the data is not lost. As a result, the bus, because of its drivers, allows hot plugging and plug and play mode. 21.7.2 Interface of the Gyroscope The connection between the digital part of the IBIS bus and the sensor has been realized with the addition of an interface. Its main function is to receive commands from the IBIS and to synchronize the data acquisition according to these commands. . 8 23456 1.0 23456 200.0 150.0 100.0 50.0 0.0 FIGURE 21.10 Results obtained for the low-pass filter. Nicolescu /Model-Based Design for Embedded Systems 67842_C021 Finals Page 710 2009-10-2 710 Model-Based Design for Embedded Systems NOR2 1 2 3 NOR2 1 2 3 INV 12 INV 1. amplifies it in two orders of magnitude. Nicolescu /Model-Based Design for Embedded Systems 67842_C021 Finals Page 708 2009-10-2 708 Model-Based Design for Embedded Systems + 3 – 2 V+ 8 V– 4 Out 1 U2A + 3 – 2 V+ 8 V– 4 Out 1 R 0 _1 R1_1 R 1 R 1 R 0 R 0 C 0 C 1 V out 2 V out 1 ref V in + V in – V dd C 1 C 1 FIGURE. Nicolescu /Model-Based Design for Embedded Systems 67842_C021 Finals Page 706 2009-10-2 706 Model-Based Design for Embedded Systems Y values S (test_acc2_5vl :