Nicolescu/Model-Based Design for Embedded Systems 67842_C019 Finals Page 636 2009-10-14 636 Model-Based Design for Embedded Systems 2.5 5 7.5 10 12.5 15 17.5 20 BPT 32 S 1 – 1.1μm pitch BPT 45 S 1 – 1.1μm pitch BPT 65 S 1 – 1.1μm pitch BPT 32 S 2 – 1.1μm pitch BPT 45 S 2 – 1.1μm pitch BPT 65 S 2 – 1.1μm pitch Static power (mW) vs. interconnect length—optical link Link length (mm)(a) (b) 30 25 20 15 10 5 0 1.4E – 02 1.2E – 02 1.0E – 02 8.0E – 03 6.0E – 03 4.0E – 03 2.0E – 03 0.0E + 00 2.5 5 7.5 10 12.5 15 17.5 20 BPT 32 S 1 – 1.1μm pitch BPT 45 S 1 – 1.1μm pitch BPT 65 S 1 – 1.1μm pitch BPT 32 S 2 – 1.1μm pitch BPT 45 S 2 – 1.1μm pitch BPT 65 S 2 – 1.1μm pitch Dynamic power (W) vs. interconnect length—optical link Link length (mm) FIGURE 19.13 Power vs. interconnect length for BPT 65, 45, and 32 nm technologies (a) Average static power (in mW). (b) Average dynamic power (in W). and to lower detector capacitance, which lowers the receiver circuit quiescent current. Dynamic power reductions between S 1 and S 2 , of the order of 2–4, are observed. This is attributed mainly to lower transistor capacitances because of lower bias current in the driver (due to the reduction in source threshold current) and because of lower modulation currents in the driver (due to the increase in source efficiency and detector responsivity). Nicolescu/Model-Based Design for Embedded Systems 67842_C019 Finals Page 637 2009-10-14 Platform for Model-Based Design of Integrated Multi-Technology Systems 637 45 40 35 30 25 20 15 10 5 0 2.5 5 7.5 10 Link length (mm)(a) (b) Total power (mW) vs. interconnect length—optical link 12.5 15 17.5 20 BPT 32 S 1 –1.1μm pitch BPT 45 S 1 –1.1μm pitch BPT 65 S 1 –1.1μm pitch BPT 32 S 2 –1.1μm pitch BPT 45 S 2 –1.1μm pitch BPT 65 S 2 –1.1μm pitch BPT 65 S 1 –1.1μm pitch BPT 45 S 1 –1.1μm pitch BPT 32 S 1 –1.1μm pitch BPT 65 S 2 –1.1μm pitch BPT 45 S 2 –1.1μm pitch BPT 32 S 2 –1.1μm pitch 10 9 8 7 6 5 4 3 2 1 0 Link length (mm) Power reduction factor vs interconnect length 0 5 10 15 20 25 FIGURE 19.14 (a) Total power (in mW) vs. interconnect length for BPT 65, 45, and 32 nm technologies. (b) Average total power comparison for varying interconnect length and technologies at 1.1 μm pitch: reduction factor. Using static and dynamic power information, the total energy can be cal- culated (Figure 19.14). The overall power is shown to be reduced between S 1 and S 2 by fac- tors of between 2 and 4. The greatest reduction is achieved at higher link lengths, which is the expected context for the use of such optical links. For Nicolescu/Model-Based Design for Embedded Systems 67842_C019 Finals Page 638 2009-10-14 638 Model-Based Design for Embedded Systems S 2 , power reduction can be considered to be a major argument in favor of optical interconnect. For S 1 , it is clear that the static power comparison is the weak point for optical interconnect, because of continuous biasing of the source (avoiding turn-on times to achieve the required bit rate) and of the receiver circuit (the circuit bandwidth is directly related to quiescent bias current). The reduction in source threshold current and in detector capaci- tance in S 2 has a significant impact on both these factors, to the extent that the static power in optical links, while still higher than that of electrical intercon- nect, is no longer dominant. Dynamic power in optical interconnect is further reduced with the smaller overall circuit transistors used in this analysis. The total power comparison shows power reduction factors between 5x and 10x for link lengths above 10 mm and for the two most advanced technology nodes. It is likely that comparisons using technologies with transistor gate lengths below 32 nm will further improve this comparison since on the elec- trical side the static power dissipation will increase with leakage current. We can thus consider that the optical device improvements constitute the main path to the solution to the following recommendation: “Power, and partic- ularly static power, is a key performance metric to optimize during explo- ration of optical interconnect device specifications.” This is an illustration of the type of feedback our approach can give to photonic device engineers. 19.5 Conclusions and Ideas for the Future In this chapter, we have looked at several aspects of heterogeneous design methods in the context of increasing diversification of integration technolo- gies. The rationale and analysis of the situation in terms of technological evo- lution and severe gaps in design technology show a clear need for advances in this domain. The experimental Rune II heterogeneous design platform addresses some of these needs—in particular we have shown how design processes can be formalized over multiple abstraction levels and multiple domains using a common model for design knowledge formulation called AMS/MT IP. To address the need to represent this knowledge at higher abstraction levels in order to retain compatibility with system-level design methods, we have demonstrated the feasibility of the use of UML and estab- lished parallels between the UML concepts and widely used concepts in AMS/MT descriptions. We have successfully used these concepts to build class diagrams for functional and structural models of integrated optical link component libraries, and implemented a synthesis scenario to explore, in a quite detailed way, the available design space over a number of very different dimension types. This design method and technology is partic- ularly useful for the repetitive design of fixed optical link structures sub- ject to varying design constraints, technology parameters, and performance Nicolescu/Model-Based Design for Embedded Systems 67842_C019 Finals Page 639 2009-10-14 Platform for Model-Based Design of Integrated Multi-Technology Systems 639 requirements. We have illustrated the direct application of our approach for optical link synthesis and technology performance characterization by ana- lyzing optical link performance for two sets of photonic component parame- ters and three CMOS technology generations. Importantly for technological development, the results of such analyses can generate useful feedback from system designers to component designers. In our view, the next major step in technological evolution for SoC con- cerns 3D integration. This approach, exploiting the vertical dimension, pro- vides an opportunity to continue to achieve the performance levels predicted by the extrapolation of Moore’s law, but using a different technological approach. The main impact is to enable the construction of highly complex systems (e.g., multiple core data-processing systems with multiple memory banks in close spatial proximity; highly heterogeneous systems using mul- tiple technologies for specific functional layers) while reducing the cost of communication by several orders of magnitude. The direct consequences of this approach are to (1) improve isochronous signal coverage and (2) allow evolution toward modular integrated systems. Such an approach should also in the long term enable novel vertical interconnect solutions (e.g., embedded repeaters, vertical switches, etc.). While by no means technologically simple, it does represent a major design paradigm shift away from the conventional approach of traditional Moore’s law scaling toward “equivalent scaling” and “functional diversity” through unconventional approaches. In this context, several tradeoff situations can be clearly shown to require heterogeneous design methods, which cannot as yet be processed by existing tools. Some examples are given here. • Tradeoffs for data-processing systems using, for example, 45 nm CMOS for processor cores and a specific technology (Flash–DRAM) for memory. While the gain over conventional planar architectures is clear (high core-memory bandwidth and high memory capacity leading to reduction/elimination of cache structure, enabling orders of magni- tude improvements in processing time for algorithms requiring high data-rate memory access), the organization of the memory and its spa- tial organization in relation to achievable through-silicon via (TSV) density and characteristics, and to the number and size of processor cores, has to be explored. • Partitioning in transformations from a planar chip to a 3D architecture. It will, for example, be necessary to explore comparisons between a complete system on chip built from an aggressive planar CMOS tech- nology and a technological partition between using the same aggres- sive CMOS technology for data processing, but a less aggressive, more stable CMOS technology for I/O functions, analog, power, voltage reg- ulators to achieve interfacing and to compensate for variability, etc. The tradeoffs here concern cost, variability, performance, power, and process simplification. Nicolescu/Model-Based Design for Embedded Systems 67842_C019 Finals Page 640 2009-10-14 640 Model-Based Design for Embedded Systems • Tradeoffs for mobile computing nodes in a 3D context using, for example, an aggressive CMOS technology for processor cores, specific advanced technology for memory, mature technology for analog, and a specific technology for RF (e.g., passive RF MEMS). Here, the focus is on overall power minimization exploiting the reduced communication cost between the data-processing layer(s) (interpreting received symbols with more complex interpolation functions) and the RF layer (relaxed constraints on RF MEMS tunability and speed based on algo- rithm efficiency). Acknowledgment This work was partially funded by the European FP6 IST program under PICMOS FP6-2002-IST-1-002131. References [BIN2005] P. R. A. Binetti et al., A compact detector for use in photonic interconnections on CMOS ICs, in Proceedings of the Symposium IEEE/LEOS (Benelux Chapter), Mons, Belgium, 233–236, 2005. [CAR2004] C. T. Carr, T. M. McGinnity, and L. J. McDaid, Integration of UML and VHDL-AMS for analogue system modeling, BCS For- mal Aspects of Computing, 16(1), 80–94, 2004. [CHA2004] V. Chaudhary, M. Francis, W. Zheng, A. Mantooth, and L. Lemaitre, Automatic generation of compact semiconductor device models using Paragon and ADMS, in Proceedings of the IEEE International Behavioral Modeling and Simulation Conference (BMAS) 2004, San Jose, CA, 107, 2004, IEEE, Piscataway, NJ. [ENI2007] Strategic Research Agenda, European Nanoelectronics Initia- tive Advisory Council (ENIAC), 2007. http://www.eniac.eu [FU2004] T. Fukazawa et al., Low loss intersection of Si photonic wire waveguides, Japanese Journal of Applied Physics, 43(3), 646–647, 2004. [FUJ2000] R. Fujita, R. Ushigome, and T. Baba, Continuous wave lasing in GaInAsP microdisk injection laser with threshold current of 40 μA, Electronics Letters, 36(9), 790–790, 2000. Nicolescu/Model-Based Design for Embedded Systems 67842_C019 Finals Page 641 2009-10-14 Platform for Model-Based Design of Integrated Multi-Technology Systems 641 [GIE2005] G. Gielen et al., Analog and digital circuit design in 65 nm CMOS: End of the road? in Proceedings of the Design Automation and Test in Europe, Munich, Germany, 2005. [GIR2002] G. Girault and R. Valk, Petri Nets for Systems Engineering, Springer, Berlin, Germany, 2002. [HAM2003] M. Hamour, R. Saleh, S. Mirabbasi, and A. Ivanov, Analog IP design flow for SoC applications, Proceedings of the International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand, IV-676, 2003. [ITR2007] The International Technology Roadmap for Semiconductors (ITRS), Sematech, 2007. http://www.itrs.net [MAS1991] R. E. Massara, Optimization Methods in Electronic Circuit Design, Longman Scientific & Technical, Harlow, U.K., 1991. [MOR1994] J. J. Morikuni et al., Improvements to the standard theory for photoreceiver noise, IEEE Journal of Lightwave Technology, 12, 1174, 1994. [OCO2003] I. O’Connor, F. Mieyeville, F. Tissafi-Drissi, G. Tosik, and F. Gaffiot, Predictive design space exploration of maximum band- width CMOS photoreceiver preamplifiers, in IEEE International Conference on Electronics, Circuits and Systems, Sharjah, United Arab Emirates, 483–486, December 14–17, 2003. [OCO2006] I. O’Connor, F. Tissafi-Drissi, G. Revy, and F. Gaffiot, UML/XML-based approach to hierarchical AMS synthesis, in Advances in Specification and Design Languages for SoCs,A. Vachoux (ed.), Kluwer Academic Publishers, Dordrecht, the Netherlands, 2006. [OCO2007] I. O’Connor et al., Systematic simulation-based predictive syn- thesis of integrated optical interconnect, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(8), 927–940, August 2007. [RIC2005] E. Riccobene, P. Scandurra, A. Rosti, and S. Bocchio, A SoC design methodology involving a UML 2.0 profile for SystemC, in Proceedings of the Design Automation and Test in Europe (DATE) 2005, Munich, Germany, 704–709, 2005, IEEE Computer Society, Washington, DC. [ROE2006] G. Roelkens, D. Van Thourhout, R. Baets, R. Notzel, and M. Smit, Laser emission and photodetection in an InP/In- GaAsP layer integrated on and coupled to a silicon-on-insulator waveguide circuit, Optics Express, 14(18), 8154–8159, 2006. Nicolescu/Model-Based Design for Embedded Systems 67842_C019 Finals Page 642 2009-10-14 642 Model-Based Design for Embedded Systems [ROO2005] F. Roozeboom et al., Passive and heterogeneous integration towards a Si-based system-in-package concept, Thin Solid Films, 504(1–2), 391–396, May 2006. [SAK2001] A. Sakai, G. Hara, and T. Baba, Propagation characteristics of ultrahigh-Δ optical waveguide on silicon-on-insulator sub- strate, Japanese Journal of Applied Physics—Pt. 2, 40(383), L383– L385, 2001. [VAC2003] A. Vachoux, C. Grimm, and K. Einwich, SystemC-AMS require- ments, design objectives and rationale, in Proceedings of the Design Automation and Test in Europe (DATE) 2003, IEEE Com- puter Society, Munich, Germany, 388–393, 2003. [VAN2005] Y. Vanderperren and W. Dehaene, UML 2 and SysML: An approach to deal with complexity in SoC/NoC design, in Pro- ceedings of the Design Automation and Test in Europe (DATE) 2005, Munich, Germany, 716–717, 2005, IEEE Computer Society, Washington, DC. [VAN2007] J. Van Campenhout et al., Electrically pumped InP-based microdisk lasers integrated with a nanophotonic silicon-on- insulator waveguide circuit, Optics Express, 15(11), 6744–6749, 2007. Nicolescu/Model-Based Design for Embedded Systems 67842_C020 Finals Page 643 2009-10-2 20 CAD Tools for Multi-Domain Systems on Chips Steven P. Levitan, Donald M. Chiarulli, Timothy P. Kurzweg, Jose A. Martinez, Samuel J. Dickerson, Michael M. Bails, David K. Reed, and Jason M. Boles CONTENTS 20.1 Introduction 644 20.2 Chatoyant Multi-Domain Simulation 646 20.2.1 System Simulation in Chatoyant 646 20.2.2 Device and Component Models 647 20.2.3 Simulation Issues 649 20.2.4 Electrical and Optoelectronic Models 650 20.2.4.1 Example Modeling of CMOS Circuits 652 20.2.5 Mechanical Models 652 20.2.6 Optical Propagation Models . . . 657 20.2.6.1 Gaussian Models 658 20.2.6.2 Scalar Diffractive Models 659 20.2.6.3 Angular Spectrum Technique 663 20.2.7 Simulations and Analysis of Optical MEM Systems 666 20.2.7.1 Full Link Example 667 20.2.7.2 Optical Beam Steering/Alignment System 668 20.2.7.3 Angular Spectrum Optical Simulation of the GratingLightValve 674 20.3 HDL Co-Simulation Environment 679 20.3.1 Architecture . 680 20.3.1.1 System Generator 680 20.3.1.2 Runtime Environment: Application of Parallel DiscreteEventSimulation 681 20.3.1.3 Conservative versus Optimistic Synchronization 682 20.3.1.4 Conservative Synchronization Using UNIX IPC Mechanisms 683 20.3.2 Co-Simulation of Experimental Systems 685 20.3.2.1 Fiber Image Guide 685 20.3.2.2 Smart Optical Pixel Transceiver 685 20.3.2.3 FIG Runtimes 687 20.3.2.4 SPOT Runtimes 688 20.4 Summary 689 20.4.1 Conclusions 690 Acknowledgments 691 References 691 643 Nicolescu/Model-Based Design for Embedded Systems 67842_C020 Finals Page 644 2009-10-2 644 Model-Based Design for Embedded Systems 20.1 Introduction In the last several years there has been much success in the realm of multi-domain, mixed-signal system on chip (SoC) technology. Devices rang- ing from heterogeneous multi-core processors to micro-electromechanical systems (MEMS) to labs-on-chips are becoming highly integrated into chip-scale packages. However, the complexity of this multi-technology inte- gration increases the difficulty of verifying such systems.Since different tech- nology domains, such as electrical (digital and analog), optical (free-space and fiber), and mechanical (micro and macro), coexist in one package, there has emerged a need for tools that can verify such heterogeneous systems. For these integrated micro-systems the goal is to model large numbers of both linear and nonlinear components with sufficient speed and accuracy to explore the design space at the system level. Beyond functional design, mixed-technology tools, working at the system level, must support the tra- ditional models of performance (e.g., speed, power, and area) as well as the special needs of mixed-technology systems. This means being able to analyze such things as crosstalk, noise, and mechanical tolerance in an interactive environment, and leads to the requirement of a computationally efficient yet accurate mixed-technology simulation framework. These problems are exac- erbated by the need to model the behavior of the controlling digital hardware and/or software and the feedback between these two worlds. Most impor- tantly, the tools must be able to capture the interaction of these realms in order to support the designer in making both architectural and technological tradeoffs. These requirements emphasize the need for high-level models for optical, electronic, and electromechanical components, accurate and computationally efficient analog simulation, and an interface to traditional digital simulation and embedded software development tools. To date, no single CAD tool has been able to completely model the complexity of these multi-domain systems on chips (MDSoCs). Current MDSoC design methodology is to use a vari- ety of “point tools” for each domain present in the design, and then stitch together the results using an additional tool. This process is both time con- suming and inefficient. Therefore, the need to perform high-level system simulations in a single framework has driven both academia and industry to the development of “system simulation” environments. Since most of these support top-down design, the focus is on hardware and software codesign and verification. Some examples of commercially available products include Seamless from Mentor Graphics, Incisive Simulator Products from Cadence, and MultiSim from Electronics Workbench. Many academic tools have also been developed such as Ptolemy [1] from the University of California at Berkeley, Pia [2] from Nicolescu/Model-Based Design for Embedded Systems 67842_C020 Finals Page 645 2009-10-2 CAD Tools for Multi-Domain Systems on Chips 645 the University of Washington, and CoSim [3] from the TIMA Laboratory at the Institut National Polytechnique Grenoble and SGS-Thomson. Most of these simulation environments target hardware–software co-simulation and rely on other simulators to perform tasks such as mechan- ical finite element analysis (FEA), optical propagation analysis (e.g., RSoft), and circuit-level simulation (e.g., SPICE). Some of the modern tools, such as System Vision from Mentor Graphics, allow for complete system modeling and simulation in mechanical and mixed-signal electrical domains, but do not support optical or fluidic systems. In this chapter we introduce a tool that can simulate and thus ver- ify the behavior of MDSoCs from the system architectural level down to the physical level of such technologies. This is accomplished by using the mixed-domain, mixed-signal simulation environment, Chatoyant [4], and a commercial mixed-language HDL simulator, ModelSim. The combination of these two simulators is accomplished using UNIX-style inter-process com- munication (IPC) as an implementation method for parallel discrete event (DE) simulation. The methodology here is similar to the work presented in an earlier chap- ter by Lee and Zheng [5]. However, we have developed our models hierar- chically such that lower-level “component” models support continuous time semantics, while composition of those models is done with discrete time semantics. Components pass complex messages among themselves under a global simulation framework. Similar to the ideas of Gheorghe, Nicolescu, and Boucheneb in this volume [6], message semantics are defined by com- mon message classes. Additionally, conversion between these analog mod- els and the multivalued digital models of a hardware description language (HDL) simulator is mediated by a set of predefined semantic rules. The rest of this chapter is organized as follows: It begins with the inves- tigation of methods for modeling digital free-space optoelectronic systems. These are systems that incorporate electronic digital and analog components, optoelectronic interface devices, such as laser and detector arrays, and free- space optical interconnects that are composed of passive and active optical elements. These models have been successfully incorporated into an opto- electronic system-level design tool called Chatoyant [4,7–9]. We present the features of Chatoyant that are useful in the modeling, simulation, and anal- ysis of MDSoCs. Next, we introduce electrical, mechanical, and optical mod- els that are used as building blocks in multi-domain system design. We then present the analog/digital co-simulation environment and discuss issues in synchronization and signal conversion between the analog domains, man- aged by Chatoyant, and the digital domain, managed by ModelSim. Finally, we show the utility of the co-simulation environment with several example systems. . the expected context for the use of such optical links. For Nicolescu /Model-Based Design for Embedded Systems 67842_C019 Finals Page 638 2009-10-14 638 Model-Based Design for Embedded Systems S 2 ,. performance, power, and process simplification. Nicolescu /Model-Based Design for Embedded Systems 67842_C019 Finals Page 640 2009-10-14 640 Model-Based Design for Embedded Systems • Tradeoffs for. Nicolescu /Model-Based Design for Embedded Systems 67842_C019 Finals Page 636 2009-10-14 636 Model-Based Design for Embedded Systems 2.5 5 7.5 10 12.5 15 17.5