SYSTEM C Methodologies and Applications potx

[...]... Özdemir3 1 STMicroelectronics Belgium (previously with Alcatel Microelectronics) 2 Katholieke Universiteit Leuven, Department Elektrotechniek–ESAT–MICAS 3 STMicroelectronics Turkey (previously with Alcatel Microelectronics) Abstract 1.1 This paper describes aspects of the process and methodologies used in the development of a complex System On Chip SystemC played a key role in supporting the technical work... the number of ports which can be connected to the channel interface, is instance-specific Static design rule checking is performed to detect dangling ports verification of access conflicts — the channel detects concurrent attempts to change the state of the container (i.e., writing at the same address at the same time) It is left up to the designer to specify how to resolve access contention It should... ver- A SystemC Based System On Chip Modellingand Design Methodology 11 ified within the complete system Compilation and linking occur on the host computer In the next phase the Instruction Set Simulator (ISS) of the custom processor can be integrated cycle accurate simulations of the cross-compiled application code are then performed As said before and illustrated in figure 1.4, the complete system can... semi-complete applications that embody domain specific object structures and functionality: complete applications can be composed by inheriting from and/ or instantiating framework components In contrast‚ class libraries are less domain specific and provide a smaller scope of reuse A SystemC Based System On Chip Modellingand Design Methodology Figure 1.8 15 Model layering separating behaviour from communication... Each processing stage communicates with the control processor shown at the bottom of the figure The control processor also has access to the data in each of the memory stages The boxes labelled TB1 – TB5 and the dashed arrows show how each section can be independently exercised by dedicated test bench firmware using this architecture (refer to Section 1.5.3) A SystemC Based System On Chip Modellingand... from communication To provide a common environment for the specification of high level architectural decisions across the disciplines To specify the black box requirements for each major subsystem To specify in detail the requirements for inter-subsystem interfaces To provide a documented framework for the structure of the SystemC model—each major subsystem mapped to a sc_module in the SystemC code A modelling... the details of subsystem interfacing Figure 1.8 illustrates this layering concept At the higher level subsystems interact with each other using ‘logical’ interfaces provided by the communication channels which connect them This interaction occurs at a high level of abstraction and focuses on how the sub- 16 Figure 1.9 Figure 1.10 Logical view of subsystems and channels Design view of channel showing... otherwise have been the case Domain and system experts can confidently specify important algorithms early in the project The exercise of coding the required functionality allowed the consideration and discovery of clean and logical structuring of the requirements applying the classical principles of cohesion and coupling A good example of this is the separation of concerns between the ‘logical’ problem of... banks This allows each section to run asynchronously with respect to each other and allows for very effective test and verification strategies since each section can be autonomously exercised from the control processor Strict separation of the user or data plane and control plane handling should be observed The user plane is implemented in dedicated logic or dedicated processors as described above to maximise... refinement process from early architectural modelling to detailed cycle accurate modelling elements which enabled early co-simulation and validation work In addition to SystemC, significant use was made of the Unified Modelling Language, and process and methodology associated with it, to provide visual, structured models and documentation of the architecture and design as it developed Introduction The challenges . State Machines SystemC Basic Concepts SystemC Operations SystemC Scheduler Example Conclusions Chapter 5 SystemC as a Complete Design and Validation Environment Alessandro Fin, Franco Fummi, Graziano. Refinement Conclusions References Index vii 222 233 245 247 247 253 259 267 268 270 272 273 274 275 282 292 296 299 299 301 305 310 316 320 325 343 Introduction System Specification Methodology SW Generation SW/SW Communication and Driver Generation Example of Software Generation in SystemC 2.0 Impact of SystemC 3.0 Release Conclusions Introduction Modeling. Leuven, Department Elektrotechniek–ESAT–MICAS 3 STMicroelectronics Turkey (previously with Alcatel Microelectronics) Abstract This paper describes aspects of the process and methodologies used in the