Xc9536 xl

- Low power operation- 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V

signals- 3.3V or 2.5V output capability- Advanced 0.35 micron feature size CMOS

FastFLASH™ technology• Advanced system features

- In-system programmable- Superior pin-locking and routability with

FastCONNECT II™ switch matrix- Extra wide 54-input Function Blocks- Up to 90 product-terms per macrocell with

individual product-term allocation- Local clock inversion with three global and one

product-term clocks- Individual output enable per output pin- Input hysteresis on all user and boundary-scan pin

inputs- Bus-hold circuitry on all user pin inputs- Full IEEE Standard 1149.1 boundary-scan (JTAG) • Fast concurrent programming

• Slew rate control on individual outputs• Enhanced data security features• Excellent quality and reliability

- Endurance exceeding 10,000 program/erase cycles

- 20 year data retention- ESD protection exceeding 2,000V• Pin-compatible with 5V-core XC9536 device in the

44-pin PLCC package and the 48-pin CSP package

Power Estimation

Power dissipation in CPLDs can vary substantially ing on the system frequency, design application and outputloading To help reduce power dissipation, each macrocellin a XC9500XL device may be configured for low-powermode (from the default high-performance mode) In addi-tion, unused product-terms and macrocells are automati-cally deactivated by the software to further conserve power.For a general estimate of ICC, the following equation may beused:

depend-ICC (mA) = MCHP(0.5) + MCLP(0.3) + MC(0.0045 mA/MHz) fWhere:

MCHP = Macrocells in high-performance (default) modeMCLP = Macrocells in low-power mode

MC = Total number of macrocells usedf = Clock frequency (MHz)

This calculation is based on typical operating conditionsusing a pattern of 16-bit up/down counters in each FunctionBlock with no output loading The actual ICC value varieswith the design application and should be verified duringnormal system operation

Figure 1 shows the above estimation in a graphical form

CPLD

DS058 (v1.2) June 25, 2001 05Preliminary Product Specification

15050

104050

HighPerfo

e

Figure 2: XC9536XL Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

In-System Programming ControllerJTAG

Controller

I/OBlocks

FunctionBlock 1Macrocells

1 to 18

Macrocells1 to 18JTAG Port

3

54

I/O/GTSI/O/GSRI/O/GCKI/OI/OI/OI/O

2 1I/O

I/OI/OI/O

3

DS058_02_0815001

FunctionBlock 254

1818

DS058 (v1.2) June 25, 2001 www.xilinx.com 3

Preliminary Product Specification 1-800-255-7778

Absolute Maximum Ratings

Recommended Operation Conditions

Quality and Reliability Characteristics

DC Characteristic Over Recommended Operating Conditions

TSOL Maximum soldering temperature (10s @ 1/16 in = 1.5 mm) +260 oC

Notes:

1 Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve During transitions, the device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA

2 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability

VCCINT Supply voltage for internal logic

and input buffers

Commercial TA = 0oC to 70oC 3.0 3.6 VIndustrial TA = –40oC to +85oC 3.0 3.6 VVCCIO Supply voltage for output drivers for 3.3V operation 3.0 3.6 V

Supply voltage for output drivers for 2.5V operation 2.3 2.7 V

Output high voltage for 2.5V outputs IOH = –500 µA 90% VCCIO V

ICC Operating supply current

(low power mode, active)

VI = GND, No loadf = 1.0 MHz

AC Characteristics

Units

Figure 3: AC Load Circuit

Device Output

Output TypeVTEST

3.3V2.5VVTEST

DS058_03_081500

VCCIO

3.3V2.5V

DS058 (v1.2) June 25, 2001 www.xilinx.com 5

Preliminary Product Specification 1-800-255-7778

Internal Timing Parameters

Product Term Control Delays

Internal Register and Combinatorial Delays

Feedback Delays

Time Adders

XC9536XL I/O Pins

XC9536XL Global, JTAG and Power Pins

Function Block

cellPC44VQ44CS48VQ64

Macro-BScan Order

Function Block

cellPC44VQ44CS48VQ64

Macro-BScan Order

Temperature RangeNumber of PinsPackage TypeDevice Type

Speed Grade

Device Ordering Options

-10 10 ns pin-to-pin delay PC44 44-pin Plastic Lead Chip Carrier (PLCC) C = Commercial TA = 0°C to +70°C-7 7.5 ns pin-to-pin delay VQ44 44-pin Quad Flat Pack (VQFP) I = Industrial TA = –40°C to +85°C-5 5 ns pin-to-pin delay CS48 48-pin Chip Scale Package

-4 4 ns pin-to-pin delay VQ64 64-pin Quad Flat Pack (VQFP)

Type

PlasticPLCC

PlasticVQFP

PlasticCSP

PlasticVQFP

09/28/98 1.0 Initial Xilinx release.08/28/00 1.1 Added VQ44 package.06/25/01 1.2 Removed -4 device Added C4 and D4 pins to CS48 No Connects in pinout table Added

industrial availability to -7 device