Electrical engineering principlesand and applications 5th edition hambley solutions manual

The effective address is the content of the X register plus the offset which is 05.. The effective address is the content of the X register which is 0200.. The effective address is the c

Electrical Engineering Principlesand And Applications 5th Edition Hambley

Solutions Manual

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CHAPTER 8

Exercises

E8.1 The number of bits in the memory addresses is the same as the address

bus width, which is 20 Thus, the number of unique addresses is 220 = 1,048,576 = 1024  1024 = 1024K

E8.2 (8 bits/byte)  (64 Kbytes) = 8  64  1024 = 524,288 bits

E8.3 Starting from the initial situation shown in Figure 8.7a in the book,

execution of the command PSHB results in:

0908:

0909: 34 090A: A2

SP  090B:

E8.4 Starting from the initial situation shown in Figure 8.7a in the book,

execution of the command PSHX results in:

0907:

0908:

SP  0909: 00

090A: 00 Then, the command PSHA results in:

0907:

SP  0908: 34

0909: 00 090A: 00 Next the PULX command reads two bytes from the stack, and we have:

0908: 34 0909: 00

SP  090A: 00

E8.5 The results are given in the book

E8.6 (a) LDAA $0202

This instruction uses extended addressing The effective address is

0202 In Figure 8.11 we see that this location contains 1A Thus, the content of the A register after this instruction is 1A The content of X is not changed by this instruction

(b) LDAA #$43 This instruction uses immediate addressing The effective address is the one immediately following the op code This location contains the

hexadecimal digits 43 Thus the content of the A register after this instruction is 43 The content of X is not changed by this instruction

(c) LDAA $05,X This instruction uses constant offset indexed addressing The effective address is the content of the X register plus the offset which is 05

Thus the effective address is 0205 In Figure 8.10 we see that this location contains FF Thus, the content of the A register after this instruction is FF The content of X is not changed by this instruction

(d) LDAA $06 This instruction uses direct addressing The effective address is 0006

In Figure 8.10 we see that this location contains 13 Thus, the content of the A register after this instruction is 13 The content of X is not

changed by this instruction

(e) LDAA $07,X- This instruction uses auto post-decremented indexed addressing The effective address is the content of the X register which is 0200 In Figure 8.10 we see that this location contains 10 Thus the content of the A register after this instruction is 10 Finally, the content of X is decremented by 07 Thus, X contains 01F9 after the instruction is completed

(f) LDAA $05,+X This instruction uses auto pre-incremented indexed addressing The effective address is the content of the X register plus 05 which is 0205

In Figure 8.10 we see that this location contains FF Thus the content of the A register after this instruction is FF Register X contains 0205 after the instruction is completed

E8.7 (a) Referring to Table 8.1 in the book, we see that CLRA is the clear

accumulator A instruction with a single byte op code 87 Furthermore execution of this command sets the Z bit of the condition code register

The BEQ $15 command occupies two memory locations with the op code

27 in the first byte and the offset of 15 in the second byte Thus starting in location 0200, the instructions appear in memory as:

0200: 87 0201: 27 0202: 15 (b) When the instructions are executed, the CLRA command sets the Z bit Then if the Z-bit was clear the next instruction would be the one starting in location 0203 following the BEQ $15 command However since the Z bit is set the next instruction is located at 0203 + 15 = 0218

E8.8 One answer is given in the book Of course, other correct answers exist

E8.9 One answer is given in the book Of course, other correct answers exist

Problems

P8.1 The functional parts of a computer are the central processing unit

(consisting of the control unit and the arithmetic/logic unit), input/output, and memory

P8.2 Tristate buffers act as switches that can be open or closed depending on

a control signal They allow data to be placed without conflict on a common bus by the CPU, by memory, or by I/O devices

P8.3 Some examples of input/output devices are keyboards, display devices,

and printers An important category of input devices in control applications are sensors that convert temperatures, pressures, displacements, flow rates, and other physical values to digital form that can be read by the computer Actuators are output devices that allow the computer to affect the system being controlled Examples of actuators are valves, motors, and switches

P8.4 In memory-mapped I/O, I/O devices are addressed by the same bus as

memory locations The same instructions used for storing and reading data from memory are used for I/O

P8.5 A bus is a parallel set of conductors used to transfer multiple bits at one

time In small computers, the bus width is typically 8 bits The data bus

is used to transfer data between the CPU, memory and I/O devices The address bus is used to transfer addresses from the CPU to memory or I/O

P8.6 An embedded computer is part of another product, such as an automobile,

printer, microwave oven, or dishwasher, that is not called a computer

P8.7* Because the address bus width is 16 bits, we conclude that the maximum

number of words in the memory is 216 = 65536 Since the data bus is 32 bits wide, each memory location can store 32 bits or 4 bytes Thus the potential number of bytes in the memory is 4  65536 = 262,144 bytes

P8.8 A microprocessor is a CPU contained on a single integrated-circuit chip

A microcomputer, such as a PC or a laptop, combines a microprocessor with memory and I/O chips A microcontroller (MCU) combines all of the functions CPU, memory, buses, and I/O on a single chip and is optimized for embedded control applications

P8.9 In computers with Harvard architecture, there are separate memories

for data and instructions If the same memory contains both data and instructions, we have von Neumann architecture

P8.10 As the term is currently used, RAM is read and write memory (originally

random access memory) that is based on semiconductor technology and is volatile (data are lost when the power is turned off) Two types of RAM are static and dynamic Because it is volatile, RAM is generally not useful

for storing programs in embedded computers

P8.11* ROM is read-only memory Some types are:

1 Mask-programmable ROM in which the data is written when the memory is manufactured

2 Programmable read-only memory (PROM) in which data is written by special circuits that blow tiny fuses or not depending on whether the data bits are zeros or ones

3 Erasable PROMs (EPROMs) that can be erased by exposure to ultraviolet light (through a window in the chip package) and

rewritten using special circuits

4 Electrically erasable PROMs (EEPROMs) that can be erased by applying proper voltages to the chip

All types of ROM are nonvolatile and are used for program storage in embedded computers

P8.12 Some types of mass storage devices are hard disks, flash memory, and

CD-ROM or DVD-ROM disks

P8.13 For storage of large amounts of data (many megabytes) the least

expensive type of memory is mass storage

P8.14 An address bus having a width of 32 bits can address 232 4.29109

memory locations

P8.15* In the ignition control system for automobiles, we need to use ROM for

the programs and fixed data, because ROM is nonvolatile Some RAM would be needed for temporary data such as air temperature and throttle setting Presumably many units would be needed for mass production and mask programmable ROM would be least expensive

P8.16 EEPROM is preferable whenever we need to change the data frequently

as in system development

P8.17 RAM is volatile ROM and mass storage are nonvolatile

P8.18 Elements of MCU-based control systems include analog and digital

actuators, sensors, operator input devices, and displays, as well as the

microcontroller

P8.19 A sensor produces an analog or digital signal that is related to a physical

variable Examples are a temperature sensor that produces an output voltage proportional to temperature, a limit switch that produces a logic signal which is high when a robot arm reaches its extreme position, a pressure sensor that produces a voltage proportional to pressure, or a digital flow meter that produces a digital word whose value is

proportional to volumetric flow rate

P8.20 Actuators produce physical outputs in response to digital or analog

electrical signals Examples of digital actuators are switches or valves that are either on or off depending on the logic value of their control signals Motors of various types produce torque, rotational speed, or rotational position in response to electrical signals Electrical heaters

are used to adjust the temperature of reactants in chemical processes

P8.21* A digital sensor produces a logic signal or a digital word as its output An

analog sensor produces an analog output signal that varies continuously with the variable being measured

P8.22 Washing machines, clothes dryers, microwave ovens, refrigerators, ovens,

clocks, radios, garage-door openers, heating-system controls, bread

machines, and so forth

P8.24 An A/D is an analog-to-digital converter that converts samples of an

analog signal into a sequence of digital words They are needed to convert signals from analog sensors into digital form so they can be

processed by a digital computer

P8.25* A D/A is a digital-to-analog converter that converts a sequence of digital

words into an analog signal They are needed when an analog actuator must be controlled by a digital computer

P8.26 Polling is the process of periodically checking digital input signals to a

microprocessor to determine when actions are needed

An interrupt is caused by a high logic value applied to the interrupt pin

Then, the MCU stops its current activity and starts a program called an

interrupt handler

The main advantage of interrupts compared to polling is that the MCU

does not waste time checking input signals

P8.27 The A, B, and D accumulators are registers that hold one of the

arguments and the results of all arithmetic and logical operations The register can be accessed either as two 8-bit registers (A and B) or as a single 16-bit register (D) A is the upper (most significant) 8 bits of D, and B is the lower (least significant) 8 bits of D

P8.28 The program counter (PC) is a 16-bit register that contains the address

of the first byte of the next instruction to be fetched (read) from memory by the control unit

The condition-code register (C) is an 8-bit register in which each bit

depends on a condition of the processor or on the result of a previous operation The details of the condition-code register are shown in Figure 8.6 in the text

P8.29* A stack is a sequence of locations in RAM used to store information such

as the contents of the program counter and other registers when a subroutine is executed or when an interrupt occurs Information is added to (pushed onto) the top of the stack and then read out (pulled off) in the reverse order that it was written After data are pulled off the stack, they are considered to no longer exist in memory The stack pointer is a register that keeps track of the address of the top of the

X: 34BF 004B: 00

004C: 00 004D: 00 004E: 00 004F: 00

After the command PSHA, we have:

SP: 004E 004A: 00 X: 34BF 004B: 00

004C: 00 004D: 00 004E: 07 004F: 00

After the command PSHB, we have:

SP: 004D 004A: 00 X: 34BF 004B: 00

004C: 00 004D: A9 004E: 07 004F: 00

After the command PULA, we have:

SP: 004E 004A: 00 X: 34BF 004B: 00

004C: 00 004D: A9 004E: 07 004F: 00 After the command PULB, we have:

A: A9 0048: 00

SP: 004F 004A: 00 X: 34BF 004B: 00

004C: 00 004D: A9 004E: 07 004F: 00

After the command PSHX, we have:

SP: 004D 004A: 00 X: 34BF 004B: 00

004C: 00 004D: 34 004E: BF 004F: 00

P8.32 Initially, we have:

SP: 004E 004A: 00 Y: B804 004B: 00

004C: 00 004D: 00 004E: 00 004F: 00 After the command PSHY, we have:

SP: 004C 004A: 00 Y: B804 004B: 00

004C: B8 004D: 04 004E: 00 004F: 00

After the command PSHB, we have:

SP: 004B 004A: 00 Y: B804 004B: 69

004C: B8 004D: 04 004E: 00 004F: 00 After the command PULY, we have:

SP: 004D 004A: 00 Y: 69B8 004B: 69

004C: B8 004D: 04 004E: 00 004F: 00 After the command PSHA, we have

SP: 004C 004A: 00 Y: 69B8 004B: 69

004C: A7 004D: 04 004E: 00 004F: 00

P8.33* A sequence of instructions that results in swapping the high and low

bytes of the X register is:

PSHA ;save the original content of A PSHB ;save the original content of B PSHX ;put content of X on the stack PULA ;pull upper byte of X into A PULB ;pull lower byte of X into B PSHA ;push upper byte of X onto stack PSHB ;push lower byte of X onto stack

PULX ;pull X with upper and lower bytes interchanged PULB ;restore original content of B

PULA ;restore original content of A Comments (following the semicolon on each line) explain the effect of each command

P8.34 For each part of this problem, the initial contents of the registers are

A:01 and X:2000 The contents of various memory locations are shown in Figure P8.34 in the book

*(a) LDAA $2002 Extended addressing A:20 (b) LDAA #$43 Immediate addressing A:43

*(c) LDAA $04 Direct addressing A:9A (d) LDAA 6,X Indexed addressing A:FF

*(e) INCA Inherent addressing A:02 (f) CLRA Inherent addressing A:00

*(g) LDAA $2007 Extended addressing A:F3 (h) INX Inherent addressing A:01 (unchanged)

P8.35

Addressing

(D) = (A):(B)

(X) (Y)

(a) ADDB $1002,Y Constant-offset IDX $0023 $1FFF $1000 (b) LDAA B,X Accumulator-offset IDX $2003 $1FFF $1000 (c) LDAB 7,+X Auto pre-

incremented IDX

$00FF $2006 $1000

(d) LDX [$1004,Y] Indexed indirect $0003 $37AF $1000 (e) LDAA [D,X] Indexed indirect $F303 $1FFF $1000

P8.36 *(a) The A register contains FF Because the most significant bit is 1,

the TSTA command results in the N bit of the condition code register being set (i.e., N = 1) Thus the BMI $07 instruction results in a branch

Instead of executing the instruction following the BMI command in location 2003, the next instruction to be executed is 2003 plus the offset, which is 7 Thus the command starting at location 2003 + 7 = 200A is the next to be executed after the BMI $07 command

(b) The A register initially contains FF The INCA instruction causes the content of the A register to become zero Because the most significant bit is 0, the N bit of the condition code register is clear (i.e.,

N = 0) Thus the BMI $11 instruction does not result in a branch, and the next instruction to be executed is in location 2003

(c) The A register contains FF Because the most significant bit is 1, the TSTA command results in the N bit of the condition code register being set (i.e., N = 1) Thus the BMI -$0A instruction results in a branch

Instead of executing the instruction following the BMI command in location 2003, the next instruction to be executed is 2003 plus the offset, which is -0A Thus, the command starting at location 2003 - A = 1FF9 is the next to be executed after the BMI -$0A command

P8.38

Instruction sequence

Content of A after execution