SU DUNG
VERILOG THIET KE MACH NHAN S BIT
Trang 2Thành Viên
01 02
Hứa Phi Vũ Đỗ Văn Tấn
Trang 301
Mạch nhân 2 số (
Trang 8START c A Q M 0 0000 1101 1011 Initial values 0 1011 1101 1011 Add Ƒ First CA<0 0 0101 1110 1011 Shift cycle M < Multiplicand Second Q < Multiplier 0 0010 1111 1011 Shift t er Count — n 0 1101 1111 1011 Add | 0 0110 1111 1011 Shift cycle
1 0001 1111 1011 Add t Fourth 0 1000 1111 1011 Shift cycle
(b) Example from Figure 10.7 (product in A, Q)
Figure 11.8 Hardware Implementation of Unsigned Binary Multiplication
€,AA+M
Shift right C, A, Q Count <—Count - 1
Product inA, Q
Trang 9
Số bịnhân M = 0110 (6) S6 nhan Q= 0101 (5) Tich = (30)
c A Q
0 0000 0101 Các giá trị khởi đầu
0 0110 0101 A «.A+M 0 0011 0010 Dịch phải 0 0001 1001 Dịch phải O 0111 1001 A ~ A+M O 0011 1100 Dich phai
Trang 10VERILO
Trang 11verilog HDL
Verilog HDL là một chuẩn "ngôn ngữ mô tả phần cứng" của IEEE, là một ngôn ngữ dạng text thuần túy được sử dụng để mô tả các mạch Số (thậm chí các mạch Số này có thể
Trang 14Multiple 8bit
by Wallace Tree
Trang 15Half Adder (HA) Implementation
ay, = Cray module ha (Cout, Sum, A, B);
by " b |
y | js, input A, B;
output Cout, Sum;
Figure 3.1 Half Adder (HA) Implementation
Trang 16
Full Adder (FA) Implementation ee module fa (Cout, Sum, A, B, Cin); a input A, B, Cin;
output Sum, Cout;
Figure 3.3 Full Adder (FA) Implementation
ha hal (gi, tempi, A, B); ha ha2 (g2, Sum, templ, Cin);
or o1, (Couk, gly 2);
A A HALF C _ >w
B B ADDER @ A C
Pee endmodule fa
Trang 17
Full Adder (FA) Implementation
module fulladd (Cin, x, y, s, Cout):
Gj ” ` input Cin, x, y: x << tf —ễx se z 7 oufput s Cout:
y, HA Gc Ci4+]
ae xor (s, x, y, Cin); and (z1, x, y): (a) Block diagram and (z2, x, Cin);
and (z3, y, Cin):
or (Cout, z1, 22, 23): C¡ ) :
} Si endmodule Ke — J
ry Figure 3.18 Verilog code for the full-adder using gate-level yi 7 primitives module fulladd (Cin, x, y, s, Cout); input Cin, x, y: output s, Cout;
(b) Detailed diagram xor (s, x, y, Cin);
and (zl, x, y) ° 8 : oo, (72: x, Cin),
Figure 3.4 A decomposed implementation of the full-adder circuit (73 y Cin):
or (Cout, z1, 22, 23): endmodule
Trang 20Mach nhan 4 bit Wallace tree
Trang 21
Mach nhan 4 bit Wallace tree
module PP (P3, P2, Pi, PO, X, Y); |hodule array4 (X, Y, Z):
input [3:0] X, Y-;
input [3:0] Y; output [7:0] Z;
input [3:0] X; // Partial Product Generation
wire [3:0] P3, P2, P1, PO; EP:bDpU (Đ3; E27 E1;.P0;-.X,.Y)z output [3:0] P3, P2, P1, P0; // Partial Product Reduction
// Partial Product Generation wire [2:0] carry3,carry2,carryl;
and pp1(P0O[3], X[3], Y[0]); wire [2:0] sum3,sum2,suml; and pp2(P0[2], XL2], Y[0]);
and pp3(P0[1], X[1], Y[0]); ha HAI (carryl[2],suml[2],P1[2],PO[3]) ha HA2 (cCarrvyl[1],suml[1],P1[1],PO[2]): :
and pp4(PO[0], x{0], Y[0]); ha HA3 (carryl[0],sum1[0],P1[0],P0[1]);:
and pp5(P1[3], X[3], Y[1]); fa FAl (carry2[2],sum2[2],P2[2],P1[3],carryl[2]):;
and pp6(P1[2], X[2], Y[1]); fa FA2 (carry2[1],sum2[1],P2[1],suml[2],carryl[1]);
and pp7(P1[1], x11], Y[E1l)› fa FA3 (carry2[0],sum2[0],P2[0], suml[1],carrv1l[0]): and pp8(P1[0], x[0], Y[1]); fa FA4 (carry3[2],sum3[2],P3[2],P2[3],carrvy2[2]):
fa FA5 (carry3[1],sum3[1],P3[1], sum2 [2], carry2[1]) :
and pp9(P2[3], X{3], Y[2]); fa FA6 (carry3[0],sum3[0],P3[0],sum2[1],carry2[0]);
and pp10(P2L2], X[2], Y[2]); // Generate lower product bits YBITS
and pp11(P2[1], X[1]1, Y[2]); buf bl(Z[0], P0[0]):; and pp12(P2[0]1, X[0], Y[2]); buf b2(Z[1], suml[0]);
Trang 22Thuc hién mach nhan 8 bit 7 a6 a5 a4 b7 b6 b5 bá b3 b2 b1 b0 23 a2 a1 a0 a7 a6 a5 a4(43 b7 b6 b5 b4'b3 b2 b1 b0 a2 a1 a0) b[7:4] b[7:4] b[3:0] b[3:0] a[7:4] + 4 a[3:0] + ng ‡ 4 a[3:0] A mn ma a es > Nhân phân multiply block multinly block multiply block multiply block | + + %1) AT 07:0] D h O | {q3[7:0] , 0000 ] {0000, q2[7:0] FF (60607Á)) - > 2 bê ^ Ộ cộng 6 = ——T _ bit uc > 1 bộ cộng 12 | bit QI15:4] Q{3:0] a7 a6 a5 a4'a3 a2 a1 a0 0 b3 b2 b1 b0
Trang 23
module add_8 bit (X,Y,2Z);
input [7:0] Y;
input [7:0] X;
Trang 24module add 12 bit (X,Y,Z); input [11:0] Y;
input [11:0] xX; output [11:0] Z; wire [11:0] carry; wire [11:0] sum;
//assign Z = X + Y;
ha fa fa fa fa fa fa fa fa fa fa fa
HAI
FA2
FA3 FA4 FAS FA6 FA7 FAS FAS
FA1O(carry[9] ,sum[9] ,Y[9] ,X[9] ,carry[8] ); EA11 (carry[10],sum[10],Y[10],X[E10],carry[9] ); EA12 (carry[11],sum[11] ,Y[11],X[11],carry[L10]);
(carry[9],sum[©2],Y[2],X[LS] is (carry[:],sum[° ],Y[:],X[:],carry[9]); (carry[2],sum[2],Y[2],X[2],carry[1i]); (carry[3] ,sum[3] ,Y[3] ,X[3]1,carry[2]) ; (carry[4],sum[4],Y[4],X[4],carry[3]);
(carry[5],sum[5],Y[5],X[5],carry[4]); (carry[6],sum[6],Y[6],X[6],carry[5]); (carry[7],sum[7],Y[7],X[7],carry[6]); (carry[8],sum[8],Y[(8],X[8],carry[7]);
assign Z = sum;
endmodule
Trang 25Ne Oo WwW Nw oe oe oe oe oe oe wow on wo hb Ww ww = © H3 Hà Hà Hà Hà Ww Ww Ww Ww Ww Ww ow Ww HAOoOePWNkrF OF HW OTA oO NN 37 module array8 (X, input [7:0] X; input [7:0] Y-; output [15:0] Z; wire
wire wire
wire
wire
wire wire wire wire wire
wire [7:0] [7:0] [7:0] [7:0] [7:0] [11:0] [11:0] [11:0] [7:0] [11:0] [11:0]
Y,Z):
q0; q1; g2; q3: templ; temp2; temp3; temp4; q4;
q5z
q6;
// using 4 4x4 multipliers array4
array4 array4 array4
z1(X[3:0],Y[3 z2(X[7:4],Y{[3 z3(X[3:0],Y([7 z4(X[T:4],Y[L7
// stage 1 adders
assign templ ={4'b0,gq0[7:4]};
add_ 8
:0),q0[7 :0),ql[7 :4),q2[7 :4),q3[7
:0]); :0]); :0]);
:0]); _ bịt Z5(g1[7:0],templ, g4) ; assign temp2 ={4'b0O,q2[7:0]}; assign temp3 ={q3[7:0],4'bO}; add 12 bit z6é(temp2,temp3,q5); assign temp4={4'b0O,q4[7:0]}; // stage 2 adder
add 12 bit z7(temp4,q5,q6); // final output assignment assign Z[3:0]=q0[3:0]; assign Z[15:4]=q6[11:0]; endmodule
Trang 2603
MO PHONG
Trang 27// Wait 100 ns for global reset to finish
// Wait 100 ns for global reset to finish
Trang 28module test; ari Ÿ q ¡| b »p% 1.00us ~) Ge J Re-aunch
// Inputs 62.500 ns
reg [7:0] X; reg [7:0] Y;
CC“ iiitttnliiii] ii ~=—t—“‘i;S™Ci«S; 000000000000000U ý 0000000000001000 '0
// Outputs
immjj mi HA ẰẲ 0000D0 10 00000 100 0 00000000) — `) 0000D001 0000D0 10 om
wire [15:0] 2;
// Instantiate the Unit Under Test (UUT)
array8 uut (
-X(X), -Y(Y),
.2(2) ); initial begin // Initialize Inputs X = 0; Y=0; // Wait 100 ns for global reset to finish #100; // Add stimulus here X = 2; Y=1; : operator1 (8 bit) operator2 (8 bit)
Result (16 bit)
// Wait 100 ns for global reset to finish
#100;
Trang 30Kién truc
may tinh 8-
Trang 31Bộ luận lý số học ( ALU) ALU8bit SNe [ Ops | Ope
4 _ 1 000 Result = Operand] + Operand2 Opcode(2:0) Result(15:0) 2 001 Result = Operand] - Operand2
R) 010 Result = Operandl * Operand2 Operand 1 (7:0) — —— ——— _ fiag C 4 011 Result = Operand] & Operand2 Operan d2 (7:0) fl ag 7 5 100 Result = Operand] | Operand2
Trang 32BỘ xử lý trung tâm
Trang 33
May tinh 8-bit ( vi diéu khién 8
bit)
8051
Trang 36Nhom chung em cam