Effectively demonstrate the best operating threshold of circuit designs to match thedelay and energy of the circuit based on the optimization of the subcircuits.Learn the appropriate ope
INTRODUCTION
Overview
A significant turning point in the development of contemporary industry and commerce was the creation of the complementary metal oxide semiconductor (CMOS) integrated circuit Because of its affordability, simplicity of integration, and performance, it has brought about revolutionary developments in computing Power efficiency has grown to be a top priority for VLSI designers in recent years The development of embedded systems, portable electronics, audio- and video-based systems, including digital signal processing (DSP) technologies, is one of the major elements contributing to this trend These computationally demanding systems must perform their complicated functions with the least amount of power usage while preserving dependability, increasing throughput, and reducing expenses.
Approximate computing has recently emerged as a promising approach to energy-efficient design of digital systems Approximate computing relies on the ability of many systems and applications to tolerate some loss of quality or optimality in the computed result By relaxing the need for fully precise or completely deterministic operations, approximate computing techniques allow substantially improved energy efficiency This resreach reviews recent progress in the area, including design of approximate arithmetic blocks, pertinent error and quality measures, and algorithm-level techniques for approximate computing.
Objective
The topic "Design of approximate adder based on limited hardware resources" provides solutions to optimize the design of approximate adder, an important element in many digital signal processing applications Approximation adders are used to calculate the product of two binary numbers, a fundamental calculation in many image processing applications such as error tolerant image processing, sharpening approaches.
The goal of the project is to design a set of approximately optimal adders in terms of size, power and processing speed on a limited hardware resource platform The solution will focus on reducing transistor count and power consumption, improving performance, and increasing processing speed.
These solutions include using optimal adder architecture, optimizing design size, and optimizing voltage and frequency collapsing expressions to optimize mathematical operations.
Research methods
Effectively demonstrate the best operating threshold of circuit designs to match the delay and energy of the circuit based on the optimization of the subcircuits.
Learn the appropriate operating threshold parameters for each basic logic gate, then apply calculations, compare the results of calculations and select the most suitable parameters.
Learn the principles based on theory and then experiment on Cadence simulation software.
Design subcircuits based on theory, and synthesize the designs.
Run simulations using different measurement technology scenarios (90nm and180nm), then select appropriate results and perform performance evaluation based on accuracy criteria , resource usage, energy consumption and propagation delay threshold.
Scope
The research object of the project is approximate adders based on exact adders and XOR/XNOR sets To optimize the design of approximate adders, the project offers solutions such as using optimal adder architecture, optimizing design size and optimizing voltage and frequency However, to apply these solutions, it is necessary to re-design and simulate the operation of Full Adder and XOR/XNOR sets in different designs such as Full Adder (10T, 14T, 16T, ) ; XOR/XNOR (4T, 8T, 10T).
With conventional adder designs, it is also possible to redesign and reimagine their operation to optimize the design of the full adder However, optimization solutions may vary depending on the type of full adder and its intended use.
Therefore, to optimize the design of full adders and XOR/XNOR, it is necessary to conduct detailed research and analysis on the structure, operation and requirements of each type of full adders and XOR/XNOR, and then Offer appropriate optimization solutions.
Because of limited research time, we only learn and analyze two approximate adders:Lower-part Or Adder Design (LOA) and Hardware Efficient Approximate Adder Design(HEAA).
Research contents
The research topic includes pages, tables, 67 figures and charts In addition to the introduction and conclusion, list of acronyms, list of tables and charts, list of references and appendices, the topic is structured into 5 sections as follows:
Chapter 1: Survey methods of performing cumulative multiplication, through which to find optimal methods, thereby building a system and setting tasks and goals for the project.
Chapter 2: Presents the theory and structure of full adders and XOR/XNOR, their applications in performing approximate calculations.
Chapter 3: Optimize designs, select optimal methods, and design scalability.
Chapter 4: Conduct simulations, compare and contrast designs, and demonstrate the optimization of the newly proposed design.
Chapter 5: Conclusions drawn from optimal design, setting out development directions for design.
THEORETICAL BASIS
The Full Adder Circuit
The growing number of battery-powered portable devices like as laptops, personal digital assistants (PDAs), and mobile phones necessitates the use of VLSI and ultra large-scale integration architectures with better power delay characteristics Since full adders are among the most fundamental building blocks of all the circuit applications outlined above, researchers have continued to work heavily on them throughout the years. Various forms of logic were examined, each with advantages and drawbacks, in order to build 1-bit complete adder cells The designs that have been revealed thus far may be largely divided into two groups: 1) dynamic style and 2) static style In comparison to its dynamic version, static full adders often consume less power, are simpler, and are more dependable However, they also typically require a bigger on-chip space.
Certain logic styles often prioritize some aspects of performance over others The most significant logic design types in the conventional arena are transmission gate full adder (TGA), dynamic CMOS logic, complementary pass-transistor logic (CPL), and standard static complementary metal-oxide-semiconductor (CMOS) The other adder designs utilize a hybrid-logic design style, which combines many logic styles The total performance of the complete adder is enhanced by these designs, which take use of the characteristics of various logic types.
In such a full adder circuit, the pass transistor logic module used just ten transistors to create the XOR and XNOR functions concurrently These functions were then used in the CMOS module to produce full-swing outputs of the full adder, although at the expense of a higher transistor count and slower speed Even while hybrid logic adders have promising performance, most of them have weak driving capabilities, and if properly designed buffers are not included, their performance significantly deteriorates in the cascaded mode of operation This work aims to enhance the various performance metrics of the complete adder, such as power, latency, and transistor count, in comparison to the current ones Using Cadence Virtuoso tools, the circuit was built in both 180-nm and 90-nm technology.
A full adder is an electronic circuit that performs the addition of binary numbers It is a fundamental building block in digital circuits, and it is used in a wide variety of applications, including arithmetic logic units (ALUs), counters, and shift registers The full adder is designed to add two one-bit binary numbers, A and B, and a carry-in bit, Cin.
Full Adder is the adder that adds three inputs and produces two outputs The first two inputs are A and B and the third input is an input carry as Cin The output carry is designated as Cout and the normal output is designated as S which is Sum The Cout is also known as the majority 1’s detector, whose output goes high when more than one
5 input is high A full adder logic is designed in such a manner that can take eight inputs together to create a byte-wide adder and cascade the carry bit from one adder to another. we use a full adder because when a carry-in bit is available, another 1-bit adder must be used since a 1-bit half-adder does not take a carry-in bit A 1-bit full adder adds three operands and generates 2-bit results.
Figure 2- 1 The symbol of full adder Where,
Cin : The carry in from the previous stage.
Table 2- 1 The Full Adder Truth
Minimize the output function using the Karnaugh:
Table 2- 2 Logical Expression for Sum AB
Sum = A’ B’ Cin + A’ B Cin’ + A B’ Cin’ + A B Cin = Cin (A’B’ + AB) + Cin’(A’B +AB’) = Cin XOR (A XOR B)
Table 2- 3 Logical Expression for Cout AB
Cout= A’BCin + AB’Cin + ABCin’ + ABCin = AB + BCin + ACinFull adder circuit diagram:
Figure 2- 2 Block Diagram of basic full adder circuit Full adder N-bit:
To design an adder with more than 1 bit, we will have to connect many 1-bit adders together, by connecting Cin of the previous adders with Cout of the adders.
Figure 2- 3 Logic circuit diagram of a 2-bit full adder.
We can add an adder if we wish to do calculations with additional bits, but this is not advised since it would increase the propagation delay, which will slow down processing and make signal recovery more difficult.
2.1.1 The CLRCL (Complementary & Level Restoring Carry Logic) Full Adder
CLRCL full adder is a novel full adder design that uses Complementary and LevelRestoring Carry Logic to reduce the circuit complexity and achieve faster cascade operation.
Figure 2- 4 Logic block diagram of the CLRCL full adder Compared to previous complete adder designs, it has a lower operating voltage, consumes less energy, and contains 10 transistors In addition to having the lowest energy usage per addition, the CLRCL full adder can withstand lower Vdd operation than comparable designs.
In order to achieve quicker cascade operation, the complementary and level restoring carry logic full-adder is a low complexity circuit In the carry propagate chain, the multiple threshold voltage fit losses problem is resolved by using an appropriate level restoring mechanism with an inverter First, make an effort to refrain from using the stage's degraded output as gate control signals This is the typical issue with the majority of 10-transistor full adder designs In addition to causing repeated threshold voltage losses, it could prevent the cascaded circuit from operating correctly Secondly, attempt to remove the transmission of unbuffered carry signals in a pass transistor chain The propagation delay is a quadratic function of the number of cascaded pass transistors, according to the Elmore formula The latency is unbearable even with a reasonable number of cascade lengths As seen in figure 2-4, a 2-to-1 multiplexer and an inverter implement the XNOR circuit used in the design The inverter serves three purposes It is first utilized as a circuit for level restoration in order to counteract output threshold voltage loss MUX 2/3 receives the level restored output after which it generates Carry and Sum signals There will only be one threshold voltage loss for Carry and Sum when they are far from the power supply Second, the inverter accelerates the carry propagation by acting as a buffer along the carry chain Thirdly, the inverter supplies the complementary signals required for the phase that comes after Two transistor XOR structures make up the complementary and level restoring carry logic full-adder unit.Inverters are used to produce carry by propagating full swing signals and preventing
9 threshold loss problems Despite operating in full swing, the carry signal circuit uses more power Complementary signals make the XNOR design simpler since they only require one signal for selection control Figure 2-5 shows the MOS circuit schematic design of a CLRCL complete adder Ten transistors (5 pMOS and 5 nMOS) are all that are needed for the complete adder circuit.
Figure 2- 5 MOS circuit schematic design of the CLRCL full adder
2.1.2 High-gate-count full adder designs (TG-CMOS, TFA, 14T, 16T)
2.1.2.1 The Transmission Gate Full Adder
The Full Adder circuit using transmission gates is an essential tool in digital electronics This circuit, which builds on the half-adder circuit, gives us the ability to add two single-digit binary numbers together and produce a result.
Figure 2- 6 The Full Adder circuit using transmission gates
A transmission gate is a type of switch that uses transistors, both PMOS and NMOS, connected source to source end and drain to drain This switch has a Dc characteristic that is independent of input level and low resistance The input terminal is connected to the source ends of NMOS and PMOS, while the output terminal is linked to the drain ends of NMOS and PMOS By connecting an enable "en" signal to one transistor and its complemented logic to another using an inverter, both transistors are turned on and off simultaneously It transmits by PMOS towards the output while the input is strong 1, and through NMOS when the input is strong 0 When the resistance drops and the capacitance rises with an increase in the W/L ratio, the transistor's channel length (L) and channel width (W) are modified accordingly.
The NMOS and PMOS transistors, sometimes referred to as pass transistors, are used in the transmission gate design The linearized RC network can be used to mimic the worst-case delay of a chain of pass transistors A resistor is used to represent the transmission gate's linearized on-resistance, which has been calculated For every transistor, the linearized diffusion capacitance is also calculated.
There are several benefits to building a full-adder circuit with a transmission gate.First of all, it does away with the requirement for extra parts like relays or transistors.Second, by shortening the signal route, power consumption is decreased and reaction times are improved Thirdly, it enables more effective design and quicker switching processes.
30 transistors are needed for the whole adder construction employing transmission gate logic An arithmetic circuit block having three inputs and two outputs (a SUM and a CARRY) is called a complete adder design N complete adders are needed for every N it addition Let's review the steps involved in adding higher binary integers First, we add the two numbers' LSBs together We take the carry, if any, ahead to the next higher column bits after recording the total beneath the LSB column Therefore, if there were a carry from the previous addition, we would have to add three bits when adding the next neighboring upper column bits Until the MSB, the circumstances for the additional upper column bits are also comparable Therefore, in order to create an adder circuit that can add bigger binary values in hardware, a complete adder is required The addition of LSBs is the only use for a halfadder The fundamental component of binary adders is the complete adder of the kind mentioned above Nonetheless, adding one-bit binary values is limited to a single complete adder circuit To create adders that can add binary integers with more bits, a cascade configuration of these adders can be utilized.
The XOR/XNOR circuits
The XOR and XNOR gate functions are shown in Table 1 and denoted by ⊕ and ⨀ respectively The logic expression for XOR and XNOR are
Table 2- 4 XOR and XNOR gate function
Four transmission gates are used by the 8 transistor XOR-XNOR gate, which is regulated by the input signals A and B Depending on the mix of inputs, the gates function as switches that selectively link ground (GND) and the supply voltage (VDD) to the output.
Figure 2- 11 The 8-transistor XOR/XNOR circuits.
A high output (VDD) is produced when both A and B are the same (0 or 1) This is achieved by both TGs linked to GND turning off and both transmission gates connected to VDD turning on The XNOR function is corresponding to this.
One TG linked to VDD turns on and the other goes off when A and B are different. Furthermore, one TG that is linked to GND turns on and the other one shuts off As a result, the XOR function is represented as a low output (GND).
Several XOR-XNOR design strategies have been established in the last several years.There exist two construction methods for XOR-XNOR circuits The first approach is creating the XOR circuit first, then obtaining the XNOR output—basically, a transmission gate adder (TGA)—by means of an inverter The main issue is that incorrect switching and glitches in the outputs of Modules II (sum circuit) and III (carry circuit) arise from the XOR and XNOR outputs not being generated concurrently To overcome this shortcoming of the second method, the XOR–XNOR circuit is constructed so that the XOR and XNOR outputs are generated simultaneously Furthermore, an attempt is made to minimize the difference in delay between the XOR and XNOR signals.
Radhakrishnan exhibited an XOR-XNOR circuit that uses just six transistors to provide full swing outputs and has acceptable delay performance for inputs 01 and 10, but a switching delay for inputs 11 and 00 Naseri and Timarchi added four more transistors—two nMOS and two pMOS—to solve this issue This design reduces power consumption in addition to resolving the delayed response issue.
The suggested XOR-XNOR circuit reduces the total delay and power consumption of the XOR-XNOR circuit by replacing the extra transistors and internal inverters at the input (A-) with fewer of them.
The 10-transistors are used to form the suggested XOR-XNOR circuit, which is based on the cross-couple construction and CPL as seen in figure 2-12 The proposed XOR-XNOR circuit, which is based on the cross-couple construction and CPL as shown in figure 2-12, is formed by the 10-transistors.
Figure 2- 12 10-transistor XOR/XNOR circuits.
As for the XOR output side, it uses two pMOS (P1 and P2) and three nMOS (N3, N4, and N5) transistors; for the XNOR output side, it uses two nMOS (N1 and N2) and three pMOS (P3, P4, and P5) On the xor side and the xnor side, respectively, five transistors are used This circuit generates the xor and nor outputs as well as full output swing simultaneously.
A full swing output is obtained by connecting PTLs P1 and P2, N4, and N5, in parallel with the feedback transistor at the XOR side, nMOS N3 In contrast, P4 and P5 are connected as storer transistors to provide a full swing output, N1 and N2 transistors
17 are connected in parallel as PTL, and P3 is connected as a feedback transistor at the XNOR output side.
When two of the inputs, A and B, are set to 01, transistors P2, N1, and P4 turn on. Taking into account that pMOS is a decent logic 1 and nMOS is a great logic 0 While transistors P2 and N1 pass logic "1" and "0" at the XOR and XNOR outputs, respectively, transistor P4 activates transistor P3 to pass the weak logic "0" at the XNOR output.
Additionally, when inputs A and B equal 10, transistors P1, N2, and N4 turn on. Transistor N3 passes the weak logic "1" at the XOR output when transistor N4 activates it The logic "1" and "0" are sent via transistors P1 and N2 to the XOR and XNOR outputs, respectively.
The output swing of AB's "01" and "10" will not be affected by the weak logic outputs because there are paths available for full swing outputs Transistors P1, P2, P4, and P5 come on when inputs A and B are set to "00." P1 and P2 pass weak logic "0" at the XOR output, whereas P5 and P4 pass full logic "1" at the XNOR output and the internal node X.
Logic "1" at node X activates transistor N3, and a strong logic "0" passed at the XOR output maximizes its output Transistors N1, N2, N4, and N5 also become active when inputs A and B equal "11" The XOR node fully discharges through N4 and N5, and the transistors N1 and N2 pass weak logic "1," for the XNOR output Furthermore, transistor P3 is turned on by the logic "0" being transmitted to the internal node X, which enables the full logic "1" to be passed at the XNOR output.
2.2.3 The 4-transistor XOR/XNOR circuits
In PTL (pass transistor logic), an XOR/XNOR function may be accomplished with just 4 transistors, as shown in figure 2-13 While the circuits in (c) and (d) are PTL based, the circuits in (a) and (b) are inverter based Table 5 compiles the output voltages subject to various input combinations, assuming both inputs have full voltage swing.
The size of a threshold voltage in inverter-based circuits degrades both the output high and low values under specific input combinations The condition is improved and only the output high or output low voltage is worsened in PTL-based circuits More voltage deterioration might happen if the compromised output is utilized to regulate the gate of the next stage in pass transistor logic On the other hand, poor output quality does not always indicate a negative impact on circuit performance Whether or whether they result in further voltage drop in the subsequent step will determine this.
Figure 2- 13 The 4-transistor XOR/XNOR circuits.
Table 2- 5 Output voltage levels of 4T XOR/XNOR circuit inputs (a) (b) (c) (d)
Approximate XOR/XNOR-based Adders design
2.3.1.1 Accurate XOR/XNOR-based Adders
The XOR-XNOR module discussed before is included in the suggested 10-T complete adder architecture The whole adder, which has ten transistors overall, is built on four-transistor (4T) XNOR gates, as seen in figure 2-14 I is an internal signal,whereas X, Y, and Cin are inputs.
Figure 2- 14 Accurate XOR/XNOR-based 10T Full-Adders
In order to prevent double threshold voltage loss, there is greater flexibility in the pass transistor types that may be used when implementing sum and carry modules when complementary control signals are available By minimizing the deterioration in output voltage swing, the design becomes more sustainable when operating at low Vdd.
The non-full swing pass transistor is created in the complete adder 10T employing a restricted number of transistors thanks to the swing restored transmission gate technology.
A voltage supply of less than 1.8V will result in improper operation of the whole adder, the power source accounts for the little delay The main disadvantage of the 10-transistor adder cell is that it generates significant levels of input capacitance.
The cell does not require inverted inputs and just requires ten transistors The XNOR gate full adder design served as the model for the design The charge delivered to the load capacitance during logic level high in a non-energy recovery device is drained to ground at logic level low Note that there is no direct path to the ground for the new SERF (StaticEnergy Recovery Full adder) adder Removing a route to the earth lowers power consumption and takes the Psc variable—the product of voltage and Isc—out of the equation for total power Reapplied to the control gates is the charge held at the load capacitance The energy-recovering full adder is an energy-efficient design because it reapplies the load charge to the control gate and lacks a direct connection to ground The lowest transistor count for a full adder implementation is achieved with this innovative design.
Figure 2- 15 Conventional 10T full adder designs: The New Static Energy-Recovery Full
(SERF) Adder Inverter buffered XOR/XNOR designs are used in the design to improve driving capabilities for cascaded operations and to mitigate the threshold voltage loss issue The buffering circuit is effectively integrated into the whole adder architecture, resulting in a reduced number of transistors.
2.3.1.2 Design and Analysis of an Approximate Adder with Hybrid Error Reduction: Lower-Part OR Adder (LOA)
The application of the mentor graphics tool in 90 nm CMOS technology to analyze the Lower-part OR Adder for 4-bit addition and compare it with the precise adder (Ripple Carry Adder).
An equal-segment-based approximation adder splits an n-bit adder into several equally partitioned smaller k-bit sub-adders that perform partial adds and partial carry generations concurrently using a finite number of input bits It should be noted that sub-adders can be utilized in ripple carry adders (RCA) and carry lookahead adders (CLA), among other types of classic accurate adders.
An improved low-power high-speed adder for error-tolerant applications and high performance reliable variable latency carry select addition uses an improved carry speculation scheme for sub-adders that makes use of 2k and more input bits to generate carries This results in a much better computation accuracy than that of the adders Kahng et al suggested an accuracy-configurable adder For approximation arithmetic designs, an accuracy-configurable adder consists of many 2k-bit sub-adders that overlap k bits to provide approximate outputs.
Figure 2- 16 Architecture of lower-part OR adder (LOA)
In addition, certain least significant bits (LSBs) in a multi-bit adder are added using approximately 1-bit complete adders As seen in Figure 2-16, the Lower-Part OR Adder (LOA) approximates the addition of several LSB inputs by using OR gates An n-bit adder is split into a (n-k)-bit approximation adder and a k-bit exact adder The most significant k bit (MSB) inputs and the carry are fed into the exact adder (Cin) to produce correct outputs for the MSBs An AND operation of two (n−k−1)th LSB inputs is used to forecast the carry-in signal of the precise adder Bit-by-bit OR operations are used to realize the (n−k)-bit approximation adder.
To achieve the (n−k)-bit approximation adder for the LSBs, the LOAWA (i.e., LOA without AND operation) also employs the OR operation; the primary distinction from the LOA is the removal of the carry prediction technique, which lowers hardware cost at the price of accuracy The LOA and the optimized lower-part constant OR adder (OLOCA) are nearly the same In order to save hardware costs, a few LSB outputs are forced to "1" in the approximation adder portion, which uses the OR function Put otherwise, the OR operation generates just a small portion of the higher (n−k) LSB outputs, while the remaining lower bits of the LSB outputs are set to "1."
Both the sub-adder and the full adder are made up of exact and approximate full adders The approximate complete architecture of an adder is represented in figure 2-16 and consists of an OR gate and an AND gate, where the OR gate generates sum and theAND gate generates carry only in the bit position Because the carry is not taken into account in the adder's trailing portion, the adder functions roughly but reasonably efficiently; the approximation is restricted to the adder's trailing bits, and the LSB portion bears the brunt of the approximation mistake because it carries less information For a single bit approximation adder, the number of mistakes in sum is '4', whereas in carry there are '2' errors and the maximum error distance is "2," as Table 2.5 below illustrates.
Table 2- 6 Truth Table for precise adder and approximate adder for 1-bit addition
Input Precise Adder Approximate Adder (LOA)
A B Cin Sum Cout OR AND ED
The functioning of the suggested adder with 16-bit inputs is seen in figure 2-17 Two distinct addition types are needed for an n-bit addition The accurate portion is acquired by performing OR and XOR operations on the remaining (n−k) LSBs, where k < n, and the exact part is obtained using a k-bit accurate adder (such as an RCA or CLA) for k MSBs A 16-bit input is divided into an 8-bit accurate component and an 8-bit approximation part in the example shown in figure 2-17 It is important to note that two portions do not have to have equal bit-widths The exact portion uses k MSB inputs to generate an accurate addition, and it predicts the carry-in signal (Cin) by performing an AND operation on two inputs (i.e., Cin = An−k−1 AND Bn−k−1) The proposed adder differs from the LOA primarily in that it replaces the bit operation of inputs 1) th
(n with the XOR operation The approximation section of the adder works similarly to the LOA, using the OR function to add the lower order input bits of two operands This leads to the creation of a half adder for (n - k - 1) th LSB inputs and essentially increases the length of accurate addition by one bit As a consequence, the accuracy is improved overall as compared to the LOA Stated differently, the suggested n-bit adder substitutes the XOR gate at the (n - k - 1) th LSB position for the OR gate, therefore always producing valid outputs for bit locations from (n −1) to (n−k−1). Consequently, the suggested adder produces an approximate part output of “01011010” under the input depicted in figure 2-17, whereas the LOA produces an output of
“11011010.” The proposed adder's output clearly approaches the correct summation of
"01101010" more than the LOA's output does, and the error distance - defined as the difference between the approximate and correct outputs, as �approximate− �accurate , respectively, represented by the parameters Sapproximate and Saccurate-for the given input drops from "1110000" (112) to "10000" (16).
Figure 2- 17 Operation of proposed adder When both of the (n−k−2) th input bits are "1" (An−k−2 = 1 and Bn−k−2 = 1), the suggested approximation adder carries out an error reduction to further reduce the output errors In the absence of such, it makes no effort to reduce errors, as seen by the example in figure 2-18.
Process Design Kit
A Process Design Kit (PDK) is an open-access library of fundamental photonic components created by the foundry to facilitate their general production process.
Designers may use the photonic components of the foundry, which are geometrically and technically described in their Process Design Kits, to create a wide range of photonic integrated circuits (PICs).
Every photonic component in the library may be thought of as a single block when contrasted to a set of building blocks, which is what a PDK is These building blocks may be used by a designer to create a wide range of photonic circuits for different uses When the designer uses specified, validated photonic components on the material platform of their choosing, a generic technology can help save costs.
A technology's attributes and fabrication details, which can be represented asSPICE/VerilogA models or saved in technology files, are all included in the PDK database The PDK includes all the information required for a standard circuit design flow, as shown in figure 2-24, from schematic simulation and physical verification to post-layout simulation Circuit simulation and design space exploration require preciseSPICE/Verilog-A models Technology data is kept in the technology file, together with definitions of electrical characteristics and fabrication guidelines It includes definitions for the layers, devices, and physical and electrical rules that are needed for physical verification Verification involves three steps: layout versus schematic (LVS), layout parasitic extraction (LPE), and design rule checking (DRC) DRC is used to confirm that the actual layout complies with the design guidelines—such as minimum widths,spacings, and overlaps—that are specified in the technology files Therefore, a high production yield is promised by a DRCcleared design LVS is used to confirm if the schematic design, used for simulation, and the physical layout, made for production, are same In order to maintain high simulation realism, parasitic devices such parasitic resistors and capacitors must be included in post-layout simulation Lastly, LPE is used to extract these devices.
Figure 2- 24 Process Design Kit (PDK) provides necessary information for the circuit design.
2.4.1 Generic Process Design Kit (GPDK) 90 nm technology (gpdk90)
A whole design kit based on a pseudo 90nm BiCMOS technology is called GPDK090. Based on the Custom IC Platform, the design kit's components will enable a CIC front-to-back design cycle.
Design kits have always been necessary for product testing, client demonstrations, and examples Traditionally, these design kits have been quite basic and lacking in assistance A more complete and reliable design kit is needed to enable the Custom IC Platform, as Cadence now wants a design kit with its products.
The GPDK090 will address the following requirements:
Build the groundwork for the Custom IC Platform's flow development and testing.
Build the groundwork for CIC product flows and demonstrations.
Assist clients with PDK development.
Increase the capacity of CIC Product Validation engineers to test the defined flow and products.
Give Product R&D a more useful design kit so they can test and create new products with it.
Assist ES and customer service with inquiries about design kits in relation to our CIC products and flow (s).
Provide a generic PDK that is free to distribute and doesn't include any intellectual property from third parties.
The GPDK090 ought to be as practical as is permissible.
2.4.2 Generic Process Design Kit (GPDK) 180 nm technology (gpdk180)
Semiconductor companies use the Generic Process Design Kit (GPDK) for 180 nanometers (nm) technology (gpdk180), a shared set of process design guidelines, models, and specifications, to create integrated circuits at this technology node IC designers can produce their designs on a common platform by using GPDKs, which are developed by semiconductor foundries or EDA (Electronic Design Automation) companies.
Process 180nm Technology Node: From 1998 to 2000, leading semiconductor firms like TSMC, Fujitsu, Sony, Toshiba, Intel, AMD, Texas Instruments, and IBM commercialized the 180 nm process, a MOSFET (CMOS) semiconductor process technology Because it greatly accelerated the technological growth of the mobile and smart electronic industries, which have transformed the world and our way of life in just over ten years, low power process technology is essential Numerous applications,including as mobile phones, wireless communication, tablets, Bluetooth devices, gaming goods, and a range of portable consumer gadgets, are powered by low power technologies.
CONSTRUCT THE IDEAL APPROXIMATE ADDER
Optimal Design Quality
The XNOR set makes a significant contribution to the processing of input values, making it a component of considerable importance This architecture cannot fail since every input value has to pass through the XNOR set mistakes and the XNOR set's design need to be as good as possible.
According to the XNOR logic gate's properties, two bits of 0 and 1 will result in an output of 1 in two circumstances when the inputs are the same, notably in cases 00 and
11, whereas two separate inputs will result in the same output of 0.
In order to reverse the XOR signals, an XNOR architecture typically consists of four NAND gates linked in series, followed by a not gate A traditional XNOR unit needs a lot of space in addition to having sluggish speed due to its up to 18 transistors and high power (uW or mW) This uses a lot of power supply and is detrimental to the system's processing As a result, professionals have been looking for better, more effective XNORs with higher processing speeds and smaller physical footprints.
Based on the PULL UP and PULL DOWN structure, this is an XNOR gate composed of 2 PMOS and 2 Nmos Additionally, its output F will be level 1 when both of its inputs,
A and B, are 0 F will be level 0, which corresponds to the XNOR gate's truth table, when their input signals vary, but when the two A noise signal of 1 will be present if the input signal is V Tn
Figure 3- 1 Schematic of 4T XOR-XNOR circuit.
Figure 3- 2 Waveforms of the outputs of 4T XOR/XNOR circuit
Although the 4T XOR/XNOR circuit's outputs appear to be correct, there will be differences in the noise amplitude and latency Significant noise is seen at the output of the 4T XOR/XNOR circuit when the input signals (A and B) change from high to low or from low to high values.
We can see the delay circuit based on the Cadance simulation.
Figure 3- 3 TPHL and TPLH of 4T XNOR circuit.
Considering the average power consumption, the following image is provided:
Figure 3- 4 The average power of 4T XNOR.
The average power use may be determined using the formula below:
Next, using the transmission gate cascading approach, we will look at the XNOR, which consists of 8 transistors: 5 pmos and 3 nmos consists of the F_XNOR and F_XOR outputs.
Figure 3- 6 Waveforms of the outputs of 8T XOR/XNOR circuit.
The outputs of the 8T XOR/XNOR circuit appear to be correct, but the noise amplitude and delay will change When input signals (A and B) go from high to low or from low to high, the 8T XOR/XNOR unit produces a lot of noise at the output.
We can see the delay circuit based on the Cadance simulation.
Figure 3- 7 TPHL and TPLH of 8T XNOR Considering the average power consumption, the following image is provided:
Figure 3- 8 The average power of 8T XNOR.
The average power use may be determined using the formula below:
Finally, using the transmission gate cascading approach, we will look at the XNOR, which consists of 10 transistors: 5 pmos and 5 nmos Consists of the F_XNOR and F_XOR outputs Because there are the most transistors in this configuration, the output signal will have the least amount of delay To ensure that the output has the cleanest signal possible for F_XNOR and F_XOR, extra pmos and nmos are included at the output port to filter off output noise signals.
Figure 3- 9 Schematic of 10T XOR/XNOR circuit
Figure 3- 10 Waveforms of the outputs of 10T XOR/XNOR circuit
We can see the delay circuit based on the Cadance simulation.
Figure 3- 11 TPHL and TPLH of 10T XNOR Considering the average power consumption, the following image is provided
Figure 3- 12 The average power of 10T XNOR.
The average power use may be determined using the formula below:
In summary, we can observe that XNOR gates, which have respective values of 4T, 8T, and 10T, are compared here.
Table 3- 1 The compare of 4T, 8T, 10T about average power and delay circuits
Name of XNOR Average power consumption Delay
The 4T XNOR gate will be the most schematic in terms of area and power consumption, in terms of delay, it is acceptable since it is negligible In terms of delay, we find that the 10T delay level is the lowest, but it is not optimal in terms of the number of transistor gates.
Known as the "static energy recovery full adder," or stand for SERF, it makes use of a 2-1 multiplexer with two 4-transistor XNOR circuits, which are the best 4T XNOR circuit previously discussed It is said to be low power as the signal will be sent back to the control port (energy recovery) rather than having a direct path down to GND.
Figure 3- 13 Schematic of SERF Full Adder
Figure 3- 14 Waveforms of the outputs of SERF Full Adder circuit.
We can see the delay circuit based on the Cadance simulation.
Figure 3- 15 TPHL and TPLH of SERF Full Adder.
Considering the average power consumption, the following image is provided:
Figure 3- 16 The average power of SERF The average power use may be determined using the formula below:
This is called a transfer function full adder (TFA) It includes 16 transistors Basically,the XOR circuit needs 2 different inputs to output a signal of 1, so it requires 2 different
41 inputs, so an Inverter gate is needed to increase the number of trans to 6, including 2 trans inverters, 2 trans transmission gates , 2 trans mux 2-1 TFA is composed of XOR, 2 2-1 muxes, 1 inverter and 1 cmos TG At the Cout output, a 2-1 transmisstion gate multiplexer is used because the output is Vdd and Vss, not reduced by Vtp and Vtn, convenient for cascading.
Figure 3- 17 Schematic of TFA Full Adder
Figure 3- 18 Waveforms of the outputs of TFA Full Adder circuit
We can see the delay circuit based on the Cadance simulation.
Figure 3- 19 TPHL and TPLH of TFA Full Adder.
Considering the average power consumption, the following image is provided:
Figure 3- 20 The average power of TFA Full Adder.
The average power use may be determined using the formula below:
14 transistors full adder design or stand for 14T, It differs from TFA in containing a 4T XOR circuit, an inverter and two transmit gate based multiplexer designs (same as those used in TFA in terms of Cout and Sum) Despite the threshold voltage loss at the internal nodes, this design maintains the output voltage fluctuation completely unaffected by the threshold voltage.
Figure 3- 21 Schematic of 14T Full Adder.
Figure 3- 22 Waveforms of the outputs of 14T Full Adder circuit.
We can see the delay circuit based on the Cadance simulation.
Figure 3- 23 TPHL and TPLH of 14T Full Adder Considering the average power consumption, the following image is provided:
Figure 3- 24 The average power of 14T Full Adder The average power use may be determined using the formula below:
Symbolized as 16T, inspired by the 14T design, to eliminate the inverter gate that creates the signal for the XOR gate, people instead use the XNOR gate as shown in figure 3-25, 1d to eliminate the inverter gate (eliminate the short circuit phenomenon) power dissipation may occur due to the inverter Despite the threshold voltage loss at the internal nodes, this design maintains the output voltage fluctuation completely unaffected by the threshold voltage.
Figure 3- 25 Schematic of 16T Full Adder.
Figure 3- 26 Waveforms of the outputs of 16T Full Adder circuit
We can see the delay circuit based on the Cadance simulation.
Figure 3- 27 TPHL and TPLH of 16T Full Adder circuit.
Considering the average power consumption, the following image is provided:
Figure 3- 28 The average power of 16T Full Adder.
The average power use may be determined using the formula below:
As seen below, the Full adder circuit is based on the CLRCL (complementary and level restoring carry logic) design which is formed from 1 XNOR gate (implemented as a2-1 multiplexer and output is an Inverter gate), 2 multiplexers 2-1 and 1 inverter port.Here, the 2-1 multiplexer does not have an inverting selection gate, so it is the most optimal, without an inverting selection gate, which helps optimize the input delay signal.From there, this is a FULL ADDER circuit with 10 trans (5p, 5n).
Figure 3- 29 Schematic of CLRCL Full Adder.
Figure 3- 30 Waveforms of the outputs of CLRCL Full Adder circuit.
We can see the delay circuit based on the Cadance simulation
Figure 3- 31 TPHL and TPLH of CLRCL Full Adder.
Considering the average power consumption, the following image is provided:
Figure 3- 32 The average power of CLRCL Full Adder The average power use may be determined using the formula below:
Based on the comparison of average power Full Adder ports in section 3.1.2 We draw intuitive conclusions about statistical data.
As figure 3-33 and table 3-2, we can see that there are two models that use the most optimal power: SERF So we can derive the most optimal Full Adder model for this report which is SERF (static energy recovery full adder).
Table 3- 2 The average power of Full Adder in 90nm.
Figure 3- 33 Column chart show the average power of Full Adder
Optimization of Adder design methods
3.2.1 Optimization of Adder design methods: Low-part OR Adder (LOA)
The Adder block's position is to add the number of 1 bits, or to count the number of 1 bits in the bit string that is entered into it The bit string that is entered into this block is the output that was obtained from the previous design SERF 10T complete adder.
Figure 3- 35 1-bit Full Adder The preceding section discussed the design of the Lower-part OR Adder, which is a 1-bit counter block combined with the wrong portion of the OR gate The Adder is made up of 1, 2, 3 and 4 bit adders, respectively, and the input design is as follows Figure 3.36 is shown below.
Figure 3- 36 The 6-bit Low-part OR Adder design
As seen in the preceding section, Figure 3.36 depicts a 6-bit Low-part OR adder design, where the first 4-bits are the right adder part and the first 2 bits are the wrong part. The output of the AND gate with inputs A1 and B1 will be sent into the precision adder's Cin pin The output will be determined by the Sum1 and Sum0 components using the OR gate's calculating characteristics The 4-bit precision adder component will generate the output Sum using the same computation technique as standard adders.
3.2.2 Optimization of Adder design methods: Hardware Efficient Approximate
The 10T - SERF Full Adder design is the source of the 1bit Full Adder block because of its low noise amplitude, low design area, low energy production, high performance,and low latency The next appropriate step in constructing the HEAA approximation adder is to create the full 1bit SERF adder.
As was explained in the previous section, the design is broken into two sections: the proper and wrong portions Using the figure 3.38, we can create an approximate 6-bit HEAA adder circuit that uses four bits for the full adder and two bits for the faulty component (OR gate and the MUX 2 to 1).
In the inexact part of HEAA, is OR gate, sum bits Sum1 to Sum0 are calculated by OR-ing the corresponding input bits present at the respective bit locations The value of Sum1 is equal to the output of a 2-to-1 multiplexer (MUX) whose select input is equal to the AND of A1 and B1 If the select input of the MUX is 0, Sum1 is equal to the OR of A1 and B1; otherwise Sum1 becomes 0.
Figure 3- 38 The 6-bit Hardware Efficient Approximate Adder design
RESULTS OF SIMULATION, COMPARISON, ANALYSIS AND SYNTHESIS
Results of simulation by Cadence
4.1.1 A comparison delay of each full adder in 90, 180nm: 10T adder (90nm and 180nm)
As I presented the Full Adder ports above, I presented Full Adder designs in the 180nm library Now just present at the 90nm library.
The model in schematic form is the same, only the Pmos and Pmos structures are different so we do not need to present it again in schematic form and here is the waveform of the SERF Full adder model at 90nm.
Figure 4- 1 The waveform of delay of SERF.
We can see the delay circuit based on the Cadance simulation
Figure 4- 2 TPHL and TPHL of SERF in 180nm
Table 4- 1 Delay of SERF in 90nm and 180nm
SERF Delay 16 , 4082 2 18 , 6519 17 , 53005 ( ps ) Delay 21 , 174 2 24 , 611 22 , 892 ( ps )
Figure 4- 3 Column chart show delay of SERF in 90nm and 180nm
From the above results, we can see that the delay of SERF in the 90nm library is 2 times lower than in the 180nm library, along with that the optimal area of 90nm is 2 times smaller than that of 180nm.
4.1.2 A comparison power of each full adder in 90, 180nm 10T adder (90nm and 180nm)
As I presented the Full Adder ports above, I presented Full Adder designs in the 180nm library Now just present at the 90nm library.
The model in schematic form is the same, only the Pmos and Pmos structures are different so we do not need to present it again in schematic form and here is the waveform of the SERF Full adder model at 90nm.
Figure 4- 4 The waveform of average power of SERF.
Figure 4- 5 The average power of SERF in 90nm.
The average power use may be determined using the formula below:
Table 4- 2 Average power of SERF in 90nm and 180nm.
Figure 4- 6 Column chart show average power of SERF in 90nm and 180nm.
From the above results, we can see that the average power of SERF in the 90nm library is lower that in the 180nm library, along with that the optimal area of 90nm is 2 times smaller than that of 180nm
Analysis of result
4.2.1 A software tool for automatic generation of approximate arithmetic circuits
Even though they sacrifice some precision, approximate arithmetic circuits offer a considerable reduction in time, space, and power compared to exact arithmetic circuits.Approximate arithmetic circuits can be used for a wide range of real-world applications,including digital signal processing, digital filtering, low-power graphics processing,neuromorphic computing, hardware realization of neural networks for artificial intelligence and machine learning, etc., as long as the errors resulting from approximate computation are kept within reasonable bounds The target application's error resilience often determines the maximum degree of approximation that may be included in an approximate arithmetic circuit Because of this, manually designing approximate arithmetic circuits in a hardware description language (HDL) that correspond to varying degrees of approximation may be a laborious and time-consuming operation, especiallyHungvippro2804for larger circuits Therefore, by accelerating the construction of circuits and systems, a software tool that can automatically build approximation arithmetic
57 circuits of any size according to a required accuracy will not only help with design flow but also increase the productivity of designers.
A software program called an approximator was created to automatically create approximations of arithmetic circuits depending on specifications provided by the user. Based on our innovative approximation arithmetic circuit topologies, Approximator can automatically produce Verilog HDL codes of approximate adders and multipliers of arbitrary size The Approximator's Verilog HDL codes may be synthesized in an FPGA or ASIC (standard cell based) design environment The program may also analyze approximation arithmetic circuits for correctness and inaccuracy Several sample screenshots taken at various points throughout the tool's use serve to highlight its key features For the advantage of the research community, Approximator has been made publicly available on GitHub, and tool documentation is included for user reference.
Figure 4- 7 A software tool for automatic generation of approximate arithmetic circuits
A flowchart that graphically explains the steps a user must take while utilizing the GUI version of Approximator is displayed in figure 4-8 The user has to launch the Python file "GUIMainToolCode.py" after installing the packages As shown in figure 4-7, a window labeled "Approximate Computing Tool" opens The user can choose between the three tabs in the window, "Verilog Code Generator," "Error Analysis," or "AccuracyAnalysis," according on the needs at hand Important areas of the "Verilog CodeGenerator" tab are marked in red from 1 to 6, for example Label 1 lets the user choose the kind of Verilog code by using radio buttons The user may choose the amount of adder bits for both FPGA-based and ASIC-based adders using Label 2 Two inputs are received by Label 2 in the case of the ASIC-based Multiplier: the multiplicand and multiplier bit counts Label 3 has a slider to set the bit count for the precise and imprecise portions of the approximation adder Label 3 allows the user to enter the location of the vertical cut (V-cut) in a text box for the estimated multiplier The user can choose the approximate adder or multiplier architecture needed by selecting Label 4 Label 5 explains how the user may provide a directory to store the Verilog file that will be created in accordance with the given approximation of an arithmetic circuit Label 6 indicates that the user has the option to either quit the GUI or produce a Verilog code. The GUI tool makes sure that the inputs from the user are within acceptable bounds If a user input does not meet the input requirements, an error message is displayed, as indicated in Tables 8–10 for accuracy analysis, error analysis, and Verilog code generation, respectively.
Figure 4- 8 Flowchart describing the use of the GUI version of Approximator
Table 4- 3 Specification of Verilog code generator constraints in Approximator Verilog Code
Total Number of Bits #Bits for
Inaccurate Part of Approximate Adder
Table 4- 4 Contraints associated with the error analysis of approximate arithmetic circuits in Approximator Error Analysis Approximate
Inaccurate Part of Approximate Adder
Example: the computing approximate_HEAA (Hardware Efficient Approximate Adder Design) 8 bits with 5 accurate bits and 3 inaccurate bits
Figure 4- 9 Display 8-bit approximate adders with a 3-bit inaccurate part using
The generalized equation to estimate the average error (AE) of an approximate adder is given by Equation (1) The generalized equations to calculate MAE and RMSE of approximate adders are given by Equations (2) and (3).
Approximate_Sum(An, Bn) − Accurate_Sum(An, Bn) (2)
Figure 4- 10 Result of AE, MAE, and RMSE for 8-bit approximate adders with a 3-bit inaccurate part using Approximator GUI: HEAA
4.2.3 Relation of the computing approximate_LOA (Lower-Part Or Adder Design), 10T, XOR/XNOR
As was indicated in chapters 2 and 3, there are several ideal designs for full adders.The best design is the one that meets the greatest number of requirements regarding circuit capacity and latency Smaller circuit sizes are also somewhat favored as they might conserve a significant amount of hardware resources Traditional designs for 10T complete adders: Static Energy-Recovery Full (SERF): A Novel Approach is the bestAdder has been chosen, as shown below.
Figure 4- 11 Design the full adder SERF on Cadence simulation software
Once all the design blocks are joined, we get the computing approximation adder LOA Furthermore, it may be said that this computing approximation adder LOA is the best for uses involving simple adder design.
Results of the computing approximate LOA design: (LOA 8-bit)
Figure 4- 12 Design the computing approximate LOA on Cadence simulation software
To lower voltage loss, more OR gates are used in this design To get the output voltage closer to the values, the OR gates will function as a voltage booster typical value.
You may use the illustrated examples below, which are examples from throughout the chapter that demonstrate how to summarise data in an easy-to-read manner, to confirm the accuracy of the design.
Example 1: Lower-Part Or Adder Design 8-bit
Figure 4- 13 The input values of the adder computing approximate LOA in example1.
In this example 1, we take the input value at the logic level position A[8:0] {1,1,0,0,1,0,0,1} and B[8:0] = {1,0,1,0,1,0,1,0,1}, these values are shown in detail in the image above, with such weights, the output value Sum[8:0] of this design will be as shown
Figure 4- 14 Result of the LOA in example 1.
Output result with logic level of output Sum[8:0] = 1| 0 1 1 1 0 0 1 1
The results after simulation coincide with the theoretical results, so it can be said that the design is correct with example 1.
4.2.2 Relation of the computing approximate_HEAA (Hardware Efficient Approximate Adder Design), 10T, XOR/XNOR
We obtain the computational approximation adder, HEAA, after connecting all the design blocks (the full adder 10T_SERF) It may also be said that the HEAA computational approximation adder is the best for applications involving straightforward adder construction.
Figure 4- 15 Design the computing approximate HEAA on Cadence simulation software The approximate adder HEAA design by Cadence tool is shown in figure 4-15 In the inexact part of HEAA, sum bits Sum1 to Sum0 are calculated by OR-ing the corresponding input bits present at the respective bit locations The value of Sum2 is equal to the output of a 2-to-1 multiplexer (MUX) whose select input is equal to the AND of A2 and B2 If the select input of the MUX is 0, Sum is equal to the OR of A2 and B2; otherwise Sum2 becomes 0.
Example 2: Hardware Efficient Approximate Adder Design: HEAA 8-bit
Figure 4- 16 The input values of the adder computing approximate HEAA in example 2.
In this example 2, we take the input value at the logic level position
These values are shown in detail in the image above, with such weights, the output value Sum[8:0] of this design will be as shown
Figure 4- 17 Result of the HEAA in example 2.
Output result with logic level of output Sum[8:0] = 1 1 1 1 0 1 1 1
The results after simulation coincide with the theoretical results, so it can be said that the design is correct with example 2.
The implementer has produced a high-performance and low-power design by improving the components of the new full adder design and condensing the expression to optimize the operations In practical applications, this result can help us conserve energy and enhance performance.
CONCLUSION AND DEVELOPMENT DIRECTION
Conclusion
In this project, the Cadence Virtuoso tool on the TSMC 90-nm and 180-nm technology platform was used by the performer to develop completely simulate the full adder approximation design based on the XOR-XNOR circuit For embedded systems, the XOR-XNOR optimization of the architecture combined with approximation reduces memory requirements and boosts processing performance This study has used enlarged and upgraded microchip technology, enabling it can be fully replaced by the typical full adder or adapted to big designs.
The full adder approximation design may be optimized using the XOR-XNOR, according to research findings, which also reduces capacity and maximizes processing performance and hardware resources In comparison to conventional designs, the designer's design has reduced processing speed by up to 80% and transistor count by more than 90% This indicates that one possible way to enhance embedded device performance is to use the XOR-XNOR optimized circuit.
Nevertheless, there are still issues with this investigation that need to be resolved in further research First, because of the state of microprocessor technology, the approach to reality remains a barrier The executors have not been able to execute on a variety of platforms that may aid in more accurately assessing the application of the design in reality; instead, they are only able to conduct the simulation in order to analyze the performance of the design Even while the study still has a lot of restrictions, such the fact that it can only be done in theory and cannot access reality due to current microchip technology, however, the research has produced significant findings that are applicable to the actual full adder approximately design based on the XOR-XNOR circuit.
This investigation used the Cadence Virtuoso tool on the TSMC 90NM and 180Nm technology platform to optimize the full adder approximately design based on theXOR-XNOR circuit Embedded devices' processing performance has increased and memory resources have been reduced because to the Xor-Xnor Advanced microprocessor technologies have also been employed in this investigation, which has the potential to grow to big designs or altogether replace conventional full adder.
Development Direction
Currently, a variety of topologies are being explored for full adders with the goal of enhancing performance and lowering energy usage It is still difficult to get sufficient and reliable information to access these designs, though.
The 8T and 10T full adder designs are among the most often used adder architectures.
In order to save hardware resources and power consumption, the 10T full adder is designed to employ less transistors than a full adder architecture In order to increase performance and employ fewer transistors than the 10T full adder, a novel adder architecture called the 8T full adder was created The 4T XNOR circuit, which is intended to employ less transistors than the 10T XNOR circuit architecture used in the design, has also been developed.
The ideal approximation adder design will be much more potent if the 10T, 8T full adder designs, and 4T XOR-XNOR circuit designs can be employed By using new adder designs, performance and processing speed will be increased while hardware resources and energy consumption are significantly reduced.
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