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ANALOG MULTIPLEXERS

/DEMULTIPLEXERS

DESCRIPTION

The UTC 4052 analog multiplexers is digitally

–controlled analog switch The device feature low ON

impedance and very low OFF leakage current Control

of analog signals up to the complete supply voltage

range can be achieved

FEATURES

*Triple Diode Protection on Control Inputs

*Switch Function is Break Before Make

*Supply Voltage Range=3.0 Vdc to 18 Vdc

*Analog Voltage Range(VDD-VEE)=3.0 to 18V

*Note:VEE must be≤Vss

*Linearized Transfer Characterisstics

*Low-noise-12nV/√Cycle ,f≥1.0kHz Typical

DIP-16 SOP-16

ABSOLUTE MAXIMUM RATINGS*1

DC Supply Voltage (Referenced to VEE,Vss≥VEE) VDD -0.5 ~ +18.0 V

Input or Output Voltage (DC or Transient) (Referenced to

Vss for Control Inputs and VEE for switch I/O) Vin,Vout -0.5 ~ V

Power Dissipation *2

DIP-16

SOP-16

*1 Maximum Ratings are those values beyond which damage to the device may occur

*2 Temperature Derating : 7.0 mW/℃ From 65℃ ~ 125℃

INHIBIT A B X0 X1 X2 X3 Y0 Y1 Y2 Y3

6

10

9

12

14

15

11

1

5

2

4

X

Y

Dual 4-Channel Analog

Multiplexer/Demultiplexer

CONTROLS

SWITCHES

IN/OUT

COMMONS OUT/IN 13

9

VDD=PIN16, VSS=PIN8, VEE=PIN7

1

2

3

4

5

6

7

8

Y0

Y2

Y

Y3

Y1

INH

V EE

10 11 12 13 14 15

16 V DD

X2

X1

X

X0

X3

A

B

PIN ASSIGMENT

Note: Control Inputs referenced to Vss

Analog Inputs and Outputs reference to VEE

VEE must be <Vss

ELECTRICAL CHARACTERISTICS

-55°C 25°C 125°C PARAMETER SYMBOL TEST CONDITIONS

MIN MAX MIN TYP*3 MAX MIN MAX UNIT

SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

Power Current Per

DD VDD-3.0≥Vss≥VEE 3.0 18 3.0 18 3.0 18 V Quiescent Current

DD Control Inputs:

Vin=Vss or VDD,Switch I/O : VEE≤VI/O≤≤VDD,

and△Vswitch≤500mV *4

VDD=5.0V

VDD=10V

VDD=15V

5.0

10

20

0.005 0.010 0.015

5.0

10

20

150

300

600

µA

Total Supply Current

(Dynamic Plus

Quiescent, Per

Package

ID(AV) TA=25℃only (The channel component, (Vin-Vout) /Ron, is not included.)

VDD=5.0V

VDD=10V

VDD=15V

(0.07µA/kHz)f+IDD

Typical (0.20µA/kHz)f+IDD

(0.36µA/kHz)f+IDD

µA

CONTROL INPUTS-INHIBIT, A, B, C (Voltages Referenced to Vss)

Low-Level Input

IL Ron=per spec, Ioff=per spec

VDD=5.0V

VDD=10V

VDD=15V

1.5 3.0 4.0

2.25 4.50 6.75

1.5 3.0 4.0

1.5 3.0 4.0

V High-Level Input V Ron=per spec,

Input Leakage

-5±0.1 1.0 µA

SWITCHES IN/OUT AND COMMONS OUT/IN –X,Y,Z(Voltages Referenced to V EE )

Recommended

Peak-to-Peak

Voltage Into or Out of

the Switch

VI/O Channel On or Off 0 VDD 0 VDD 0 VDD Vpp

Recommended Static

or Dynamic Voltage

Across the Switch *4

(Figure 3)

△Vswitch Channel On 0 600 0 600 0 300 mV

Output Offset

ON Resistance Ron △Vswitch≤500mV *4

Vin=VIL or VIH (Control), and Vin=0 to VDD(Switch)

VDD=5.0V

VDD=10V

VDD=15V

800

400 220

250

120

80

1050

500 280

1200

520

300 Ω

△ON Resistance

Between Any Two

Channels in the

Same Package

△Ron VDD=5.0V

VDD=10V

VDD=15V

70

50

45

25

10

10

70

50

45

135

95

65 Ω Off-Channel Leakage

Current(Figure 8) Ioff V(Control) Channel to DD=15V ,Vin=VIL or VIH

Channel or Any One Channel

±100 ±0.05 ±100 ±1000

nA

Capacitance,

Capacitance,

Capacitance,

Feedthrough

(Channel Off)

CI/O Pins Not Adjacent

*3 Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential

*performance

*4 For voltage drops across the switch (△Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD

*current may be drawn, i.e the current out of the switch may contain both VDD and switch input components The

*reliability of the device will be unaffected unless the Maximum Ratings are exceeded (See first page of this data

*sheet.)

ELECTRICAL CHARACTERISTICS *5

(CL = 50 pF, TA = 25℃) (VEE ≤VSS unless otherwise indicated)

Propagation Delay

Times(Figure 4)

Switch Input to Switch

Output

tPLH,tPHL RL=10kΩ

VDD-VEE= 5.0, tPLH,tPHL=(0.17 ns/pF) CL+21.5 ns

VDD-VEE=10, tPLH,tPHL=(0.08 ns/pF) CL+8.0 ns

VDD-VEE=15, tPLH,tPHL=(0.06 ns/pF) CL+7.0 ns

30

12

10

75

30

25

ns

Propagation Delay

Times(Figure 4)

Inhibit to Output

tPHZ,tPLZ

tPZH,tPZL

RL=10kΩ,VEE=Vss Output”1” or “0” to High Impedance, or High Impedance to”1” or “0” Level

VDD-VEE= 5.0

VDD-VEE=10

VDD-VEE=15

300

155

125

600

310

250

ns

Propagation Delay

Times(Figure 4)

Control Input to Output

tPLN,tPHL RL=10kΩ,VEE=Vss

VDD-VEE= 5.0

VDD-VEE=10

VDD-VEE=15

325

130

90

650

260

180

ns

Second Harmonic

Distortion RL=10kΩ, f=1kHz, Vin=5Vpp, VDD-VEE=10 0.07 % Bandwidth (Figure 5) BW RL=1kΩ, Vin=1/2(VDD-VEE)p-p, CL=50pF,

20 Log (Vout/Vin)=-3dB, VDD-VEE=10

17

MHz Off Channel

Feedthrough Attenuation

(Figure 5)

RL=1kΩ, Vin=1/2(VDD-VEE)p-p, Fin=30MHz,

VDD-VEE=10

-50

dB Channel Separation

DD-VEE)p-p, fin=3.0MHz,

VDD-VEE=10

-50

dB Crosstalk ,Control Input

to Common O/I (Figure

7)

R1=1kΩ, RL=10kΩ, Control tTLH=tTHL=20ns ,Inhibit=Vss), VDD-VEE=10

75

mV

*5 The formulas given are for the typical characteristics only at 25 ℃

*6 Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential

*performance

VEE

LEVEL

CONVERTED

CONTROL

VDD

VDD

VDD

VDD

VEE

Figure 1.Switch Circuit Schematic

TRUTH TABLE

Control Inputs

Inhibit B A

0

0

0

0

0

0

1

1

0

1

0

1

Y0 Y1 Y2 Y3

X0 X1 X2 X3

LEVEL CONVERTER

BINARY TO 1-OF-4 DECODER WITH INHIBIT

Figure 2 Functional Diagram

Y0 Y1 Y2 Y3

X0 X1 X2 X3 12

5 2 4

14 15 11 1

INH A B

6 10 9

13

3

X

Y

* X=Don't Care

TEST CIRCUITS

SECTION

OF IC

SOURCE

ON SWITCH

LOAD V

Figure 3.→△V Across Switch

PULSE GENERATOR

INH C B A

RL CL

Vout

VDD VEE VEE VDD

Figure 4 Propagation Delay Times, Control and Inhibit to Output

INH

C

B

A

RL CL=50pF

Vout

VDD VEE

Figure 5 Bandwidth and Off-Channe Feedthrough Attenuation

Vin

A,B,and C inputs used to tum ON or OFF

the switch under tes

2

INH C B A

RL CL=50pF

Vout

VDD VEE

Figure 6 Channel Separation (Adjacent Channels Used For Setup)

Vin

2

RL

Vss

ON OFF

C

B

RL CL=50pF

Vout

Figure 7 Crosstalk,Control Input to Common O/I

R1

Figure 8 Off Channel Leakage

CONTROL SECTION

OF IC

OTHER CHANNEL(S)

COMMON VEE

VDD

VEE

VDD

VEE

X-Y PLOTTER

1kΩ RANGE

VEE=VSS

Figure 9 Channel Resistance(RON) Test Circuit

VDD

10K

VDD

KEITHLEY 160 DIGITAL MULTIMETER

TYPICAL RESISTANCE CHARACTERISTIS

350

0

150

250

300

-10

Vin,INPUT VOLTAGE (VOLTS)

-8.0 0 0.2 4.0 6.0

200

50

100

-6.0 -4.0 -2.0 8.0 10

Figure10.V DD =7.5V,V EE =-7.5V

TA=125℃

25℃

-55℃

350

0 150

250 300

-10 Vin,INPUT VOLTAGE (VOLTS) -8.0 0 0.2 4.0 6.0

200

50 100

-6.0 -4.0 -2.0 8.0 10 Figure11.V DD =5.0V,V EE =-5.0V

TA=125℃ 25℃ -55℃

0

300

500

600

-10

Vin,INPUT VOLTAGE (VOLTS)

-8.0 0 0.2 4.0 6.0

400

100

200

-6.0 -4.0 -2.0 8.0 10

Figure12.V DD =2.5V,V EE =-2.5V

TA=125℃

25℃

-55℃

350

0

150

250 300

-10

Vin, INPUT VOLTAGE (VOLTS) -8.0 0 0.2 4.0 6.0

200

50 100

-6.0 -4.0 -2.0 8.0 10 Figure13 Comparison at 25℃,V DD =-VEE

TA=25℃

V DD =2.5V

5.0V 7.5V

Figure A illustrates use of the on–chip level converter detailed in Figures 2 The 0 ~ 5 V Digital Control

signal is used to directly control a 9 Vp–p analog signal

The digital control logic levels are determined by VDD and VSS The VDD voltage is the logic high voltage; the VSS

voltage is logic low For the example, VDD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low The maximum analog signal level is determined by VDD and VEE The VDD voltage determines the maximum recommended peak above VSS The VEE voltage determines the maximum swing below VSS For the example, VDD –

VSS = 5 V maximum swing above VSS; VSS – VEE = 5 V maximum swing below VSS The example shows a ± 4.5 V signal which allows a 1/2 volt margin at each peak If voltage transients above VDD and/or below VEE are anticipated

on the analog channels, external diodes (Dx) are recommended as shown in Figure B These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping

The absolute maximum potential difference between VDD and VEE is 18.0 V Most parameters are specified up to

15 V which is the recommended maximum difference between VDD and VEE

Balanced supplies are not required However, VSS must be greater than or equal to VEE For example, VDD = + 10

V, VSS = + 5 V, and VEE – 3 V is acceptable See the Table below

EXTERNAL

CMOS

DIGITAL

CIRCUITRY 0 ~ 5V DIGITAL

CONTROL SIGNALS

ANALOG SIGNAL

9 Vp-p SWITCH

I/O

INHIBIT, A,B,C

COMMON O/I

VDD Vss VEE

ANALOG SIGNAL

9 Vp-p

-4.5V

+4.5V GND +5V

Figure A Application Example

4052

Dx

VEE

Dx

Dx

VEE

ANALO G I/O

CO MMO N

O /I

Figure B.External G ermanium or Schottky Clipping Diodes

POSSIBLE SUPPLY CONNECTIONS

VDD

IN VOLTS

VSS

IN VOLTS

VEE

IN VOITS

CONTROL INPUTS LOGIC HIGH/LOGIC LOW

IN VOLTS

MAXIMUM ANALOG SIGNAL RANGE IN VOLTS