IntroductionThis project will present you with the process of using Vivado and IP Integrator to create a complete Zynq ARM Cortex-A9 based processor system targeting the ZyBoard Zynq dev
INTRODUCTION
Introduction
This project will present you with the process of using Vivado and IP Integrator to create a complete Zynq ARM Cortex-A9 based processor system targeting theZyBoard Zynq development board You will use the Block Design feature of IPIntegrator to configure the Zynq PS and add IP to create the hardware system, andSDK to create an application to verify the design functionality It will also guide you through the process of profiling an application and analyzing the output.
Purpose and requirements
This lab introduces a design flow to generate a IP-XACT adapter from a design using Vivado HLS and using the generated IP-XACT adapter in a processor system using IP Integrator in Vivado. b) Requirements
After completing this lab, you will be able to:
- Understand the steps and directives involved in creating an IP-XACT adapter from a synthesized design in Vivado HLS
- Create a processor system using IP Integrator in Vivado
Layout
The report is divided into 4 parts:
Part 3 Creating a Processor System Lab
CREATING A PROCESSOR SYSTEM
Embedded System Design in Zynq using IP Integrator
2.1.1 Embedded Design Architecture in Zynq
Embedded design in Zynq is based on:
• Dual ARM® Cortex™ -A9 processors of Zynq-7000 AP SoC
– Software platform for processing system
2.1.2 The PS and the PL
The Zynq-7000 AP SoC architecture consists of two major sections:
• Dual ARM Cortex-A9 processor based (Single core versions available)
• Uses the same 7 series programmable logic
– Artix™-based devices: Z-7010, Z-7015, and Z-7020 (high-range I/O banks only) – Single core versions: Z-7017S, Z-7012S, and Z-7014S
– Kintex™-based devices: Z-7030, Z-7035, Z-7045, and Z-7100 (mix of high-range and high-performance I/O banks)
What are Vivado, IP Integrator and SDK?
– Vivado is the tool suite for Xilinx FPGA design and includes capability for embedded system design
• IP Integrator, is part of Vivado and allows block level design of the hardware part of an Embedded system
• Vivado includes all the tools, IP, and documentation that are required for designing systems with the Zynq-7000
AP SoC hard core and/or Xilinx MicroBlaze soft core processor
• Vivado + IPI replaces ISE/EDK
– SDK is an Eclipse-based software design environment
• Enables the integration of hardware and software components
Vivado is the overall project manager and is used for developing non-embedded hardware and instantiating embedded systems
– Vivado/IP Integrator flow is recommended for developing Zynq embedded systems.Embedded System Design using Vivado
Creating IP-XACT Hardware Accelerator
The AXI4 interfaces supported by Vivado HLS include
• Specify on input arguments or output arguments only, not on input/output arguments
• Specify on arrays and pointers (and references in C++) only You can group multiple arguments into the same AXI4-Lite interface using the bundle option
• Specify on any type of argument except arrays You can group multiple arguments into the same AXI4-Lite interface using the bundle option.
– AXI4 Slave Lite, AXI4 Master, AXI Stream supported by INTERFACE directive
• Provided in RTL after Synthesis
• Supported by C/RTL Co-simulation
• Supported for Verilog and VHDL
– Identical IO protocol to ap_memory
– Bundled differently in IP Integrator
• Provides easier integration to memories with BRAM interface
2.2.3 Native AXI Slave Lite Interface
– Multiple ports may be grouped into the same Slave Lite interface
• All ports which use the same bundle name are grouped
– Default mode is ap_none for input ports
– Default mode is ap_vld for output ports
– Default mode ap_ctrl_hs for function (return port)
– Default mode can be changed with additional INTERFACE Directives.
2.2.4 Controllable Register Maps in AXI4 Lite
Assigning offset to array (RAM) interfaces
– Specified value is offset to base of array
– Array’s address space is always contiguous and linear
C Driver Files include offset information
– In generated driver file xhls_sig_gen_bram2axis.h
– Multiple ports may be grouped into the same AXI4 Master interface
• All ports which use the same bundle name are grouped
– Depth option is required for C/RTL co-simulation
• Required for pointers, not arrays
• Set to the number of values read/written
– Option to support offset or base address
2.2.6 Burst Accesses Inferred for AXI4 Master
There are two types of accesses on an AXI Master:Single Access and Burst Access – Burst accesses are more efficient
– Burst access has until now required the use of memcpy()
Burst Accesses are now inferred
– From operations in a for-loop and from sequential operations in the code
– However: there are some limitations
• Single for-loops only, no nested loops
2.2.7 Byte-Enable Accesses on AXI4 Master
Byte-Enable Accesses Support on AXI4 Master Interfaces
– Single bytes are now written and read
– This code uses 8-bit data
• Previously, accessing this required reading/writing full 32-bit
• This implied a required read-modify-write behavior: Impacted performance – Similar performance improvement when accessing struct members
• Also often implied read-modify-write behavior
• Variables of different sizes can be grouped into same AXI4 Master port.
AXI4 Master and Lite Port Bundling
– The bundle options groups arguments into the same AXI4 port
– For example, group 3 arguments into AXI4 port “ctrl” :
Arguments can be Bundled into AXI4 Master and AXI4 Lite ports
– If no bundle name is used a default name is used for all arguments
• All go into a single AXI4 Master or AXI4 Lite
• Default name applied if no –bundle option is used
– Group different sized variables into an AXI4 Master port
2.2.9 AXI4 Stream Interface: Ease of Use
Native Support for AXI4 Stream Interfaces
– Native = An AXI4 Stream can be specified with set_directive_interface
• No longer required to set the interface then add a resource
• This AXI4 Stream interface is part of the HDL after synthesis
• This AXI4 Stream interface is simulated by RTL co-simulation
Select IP Catalog, System Generator for Vivado or design check point (dcp) Click on Configuration… if you want to change the version number or other information
– The directory (ip) will be generated under the impl folder under the current project directory and current solution
– RTL code will be generated, both for Verilog and VHDL languages in their respective folders
Integrating the Hardware Accelerator in AXI System
Create a new Vivado project, or open an existing project
Construct(modify) the hardware portion of the embedded design by adding the IP-XACT
Create (Update) top level HDL wrapper
Synthesize any non-embedded components and implement in Vivado
Export the hardware description, and launch XSDK
Create a new software board support package and application projects in the XSDK
Compile the software with the GNU cross-compiler in XSDK
Download the programmable logic’s completed bitstream using Xilinx Tools > Program
Use XSDK to download and execute the program (the ELF file).
CREATING A PROCESSOR SYSTEM LAB
Create a New Project
Create a new project in Vivado HLS targeting xc7z020clg400-1 device
1 SelectStart > Xilinx Design Tools > Vivado HLS 2017.4
2 In the Getting Started section, click on Create New Project TheNew Vivado HLS Projectwizard opens.
3 ClickBrowse… button of the Location field, browse to{labs}\lab4, and then click OK.
4 For Project Name, typefir.prjand clickNext.
5 In theAdd/Remove Filesfor the source files, typefir as the function name (the provided source file contains the function, to be synthesized, called fir).
6 Click the Add Files… button, select fir.c and fir_coef.dat files from the {sources}\lab4folder, and then clickOpen.
8 In theAdd/Remove Files for the testbench, click theAdd Files… button, select fir_test.cfile from the{sources}\lab4folder and clickOpen.
10 In theSolution Configurationpage, leaveSolutionName field as solution1 and make sure the clock period as 8 Leave Uncertainty field blank.
11 Click on the Part’s Browse button and using the Parts Specifyoption, select xc7z020clg400-1.
You will see the created project in the Explorer view Expand various sub-folders to see the entries under each sub-folder.
13 Double-click on the fir.c under the source folder to open its content in the information pane.
Figure 1: The design under consideration The FIR filter expectsxas a sample input and pointer to the computed sample out y Both of them are defined of data type data_t The coefficients are loaded in arrayc of type coef_t from the file calledfir_coef.datlocated in the current directory The sequential algorithm is applied and accumulated value (sample out) is computed in variable acc of type acc_t.
14 Double-click on thefir.hin the outline tab to open its content in the information pane.
Figure 2: The header file The header file includes ap_cint.h so user defined data width (of arbitrary precision) can be used It also defines number of taps (N), number of samples to be generated (in the testbench), and data types coef_t, data_t, and acc_t The coef_t and data_t are short (16 bits) Since the algorithm iterates (multiply and accumulate) over
59 taps, there is a possibility of bit growth of 6 bits and hence acc_t is defined as int38. Since the acc_t is bigger than sample and coefficient width, they have to cast before being used (like in lines 16, 18, and 21 of fir.c).
15 Double-click on thefir_test.cunder the testbench folder to open its content in the information pane.
Notice that the testbench opens fir_impulse.dat in write mode, and sends an impulse (first sample being 0x8000.
Run C Simulation
Run C simulation to observe the expected output.
1 SelectProject > Run C Simulationor click on the button from the tools bar buttons, and clickOKin the C Simulation Dialog window.
The testbench will be compiled using apcc compiler and csim.exe file will be generated The csim.exe will then be executed and the output will be displayed in the console view.
Synthesize the Design
Synthesize the design with the defaults View the synthesis results and answer the question listed in the detailed section of this step.
1 Select Solution > Run C Synthesis > Active Solution to start the synthesis process.
2 When synthesis is completed, several report files will become accessible and the Synthesis Results will be displayed in the information pane.
3 TheSynthesis Report shows the performance and resource estimates as well as estimated latency in the design.
4 Using scroll bar on the right, scroll down into the report and answer the following question.
5 The report also shows the top-level interface signals generated by the tools.
Figure 4: Generated interface signals You can see the design expects x input as 16-bit scalar and outputs y via pointer of the 16-bit data It also has ap_vld signal to indicate when the result is valid.
Add PIPELINE directive to the loop and re-synthesize the design View the synthesis results.
1 Make sure that thefir.cis open in the information view.
2 Select theDirectivetab, and apply thePIPELINEdirective to the loop.
3 Select Solution > Run C Synthesis > Active Solution to start the synthesis process.
4 When synthesis is completed, the Synthesis Results will be displayed in the information pane.
5 Note that the latency has reduced to 63 clock cycles The DSP48 and BRAM consumption remains same; however, LUT and FF consumptions have slightly increased.
Run RTL/C CoSimulation
Run the RTL/C Co-simulation, selecting Verilog Verify that the simulation passes.
1 SelectSolution > Run C/RTL Co-simulationor click on the button to open the dialog box so the desired simulations can be run.
Setup IP-XACT Adapter
Add INTERFACE directive to create AXI4LiteS adapters so IP-XACT adapter can be generated during the RTL Export step.
1 Make sure thatfir.cfile is open and in focus in the information view.
3 Right-clickx, and click onInsert Directive….
4 In the Vivado HLS Directive Editor dialog box, selectINTERFACEusing the drop-down button.
5 Click on the button besidemode (optional) Selects_axilite.
6 In thebundle (optional)field, enterfir_ioand clickOK.
Figure 5: Selecting the AXI4LiteS adapter and naming bundle
7 Similarly, apply theINTERFACEdirective (including bundle) to theyoutput.
Figure 6: Applying bundle to assign y output to AXI4Lite adapter
8 Apply theINTERFACEdirective to the top-level modulefirto include ap_start, ap_done, and ap_idle signals as part of bus adapter (the variable name shown will be return) Include the bundle information too.
Note that the above steps will create address maps for x, y, ap_start ap_valid,ap_done, and ap_idle, which can be accessed via software Alternately, ap_start,ap_valid, ap_done, ap_idle signals can be generated as separate ports on the core by not applying RESOURCE directive to the top-level module fir These ports will then have to be connected in a processor system using available GPIO IP.
Generate IP-XACT Adapter
Re-synthesize the design as directives have been added Run the RTL Export to generate the IP-XACT adapter.
1 Since the directives have been added, it is safe to re-synthesize the design Select Solution > Run C Synthesis > Active Solution
Check the Interface summary at the bottom of the Synthesis report to see the interface that has been created.
2 Once the design is synthesized, selectSolution > Export RTLto open the dialog box so the desired IP can be generated.
AnExport RTL Dialogbox will open.
3 ClickOKto generate the IP-XACT adapter.
4 When the run is completed, expand the impl folder in the Explorer view and observe various generated directories, such as ip, misc, verilog and vhdl.
Figure 8: IP-XACT adapter generated
Expand the ip directory and observe several files and sub-directories One of the sub-directory of interest is the drivers directory which consists of header, c, tcl, mdd, and makefile files Another file of interest is the zip file, which is the ip repository file that can be imported in an IP Integrator design
5 Close Vivado HLS by selectingFile > Exit.
Create a Vivado Project
Create an empty project targeting the part xc7z020clg400-1, and run the provided tcl script to create an initial system.
1 Open Vivado by selectingStart > Xilinx Design Tools > Vivado 2018.2
2 ClickCreate New Projectto start the wizard You will see the Create a NewVivado Project dialog box ClickNext.
3 Click the Browse button of the Project Location field of the New Project form, browse to{labs}\lab4, and clickSelect.
4 Enter audio in the Project Name field Make sure that the Create Project Subdirectorybox is checked Click Next.
5 SelectRTL Projectin the Project Type form, and clickNext.
8 In theDefault Partform, selectParts, and selectxc7z020clg400-1 ClickNext.
9 Check the Project Summary and clickFinishto create an empty Vivado project.
10 In theTcl Console, change the directory to{sources}/lab4using thecdcommand.
11 Run the provided script file to create an initial system havingaudio_codec_ctrlandaxi_gpioperipherals by typing the following command: source zybo_audio_create.tcl
The script will be run and the initial system, shown below, will be created.
Figure 10: Block design made for Pynq Add the HLS IP to the IP Catalog
1 SelectFlow Navigator > Project Manager > Settings
2 ExpandIP > Repositoryin the left pane.
3 Click the+button (Thelab4/ip_repodirectory has already been added) Browse to{labs}\lab4\fir.prj\solution1\impl\ipand clickSelect.
The directory will be scanned and added in theIP Repositorieswindow, and one IP entry will be detected.
Figure 11: Setting path to IP Repositories
Instantiate fir_top core twice, one for each side channel, into the processing system naming the instances as fir_left and fir_right.
1 Click theAdd IPicon (+) and search for Firin the catalog by typingFirand double-click on theFirentry to add an instance.
Notice that the added IP has HLS logo in it indicating that this was created by Vivado HLS.
2 Select the added instance in the diagram, and change its instance name tofir_leftby typing it in theNamefield of theBlock Propertiesform in the left.
3 Similarly, add another instance of the HLS IP, and naming itfir_right.
4 Click onRun Connection Automation, and selectAll Automation.
5 Click on/fir_left/s_axi_fir_io and/fir_right/s_axi_fir_io and verify that they will both be connected to the M_AXI_GP0, and clickOK.
Enable the PS-PL Interrupt ports > IRQ_F2P ports Add an instance of concat IP with two single-bit input ports Connect input ports to the interrupt ports of the two FIR instances and the output port to the IRQ_F2P port of the processing_system7_0 instance.
1 Double-click on theprocessing_system7_0instance to open the re-customization form.
2 Select theInterruptentry in the left pane, click on theFabric Interruptscheck box in the right.
3 Expand theFabric Interrupts > PL-PS Interrupt Ports > IRQ_F2Pentry in the right, and click the check-box ofIRQ_F2P[15:0].
5 Add an instance of theconcatIP.
6 Connect the interrupt port of each of the FIR instances to the two input ports of thexlconcat_0instance.
7 Connect the output port of the xlconcat_0 instance to the IRQ_F2P port of theprocessing_system7_0instance.
At this stage the design should look like shown below (you may have to click the regenerate button).
Figure 12: Generated design after IRQ_F2P interface enabled
Verify addresses and validate the design Generate the system_wrapper file, and add the provided Xilinx Design Constraints (XDC).
1 Click on theAddress Editor, and expand theprocessing_system7_0 > Dataif necessary.
The generated address map should look like as shown below.
2 RunDesign Validation(Tools > Validate Design) and verify there are no errors
3 In the sources view, right-click on the block diagram file, system.bd, and selectCreate HDL Wrapperto update the HDL wrapper file When prompted, click
OK with the Let Vivado manage wrapper and auto-update option.
4 Click Add Sources in the Flow Navigator pane, select Add or Create Constraints, and clickNext.
5 Click the Add Files button, browse to the {sources}\lab4 folder, selectzybo_audio_constraints.xdc.
6 ClickCopy constraints files into projectand then clickFinishto add the file.
7 Click on theGenerate Bitstream in the Flow Navigator to run the synthesis, implementation, and bitstream generation processes.
8 ClickSave, Yes, andOKif prompted to start the process.
9 When the bit generation is completed, a selection box will be displayed withOpenImplemented Designoption selected ClickCancel.
Export to SDK and create Application Project
Export the hardware along with the generated bitstream to SDK.
2 Make sure that Include Bitstream option is selected and click OK, leaving the target directory set to local project directory.
5 In SDK, selectFile > New > Board Support Package.
6 ClickFinishwith the default settings (withstandalone operating system).
This will open the Software Platform Settings form showing the OS and libraries selections.
7 ClickOKto accept the default settings, as we want to create astandalone_bsp_0 software platform project without requiring any additional libraries support.
The library generator will run in the background and will createxparameters.h file in the {labs}\lab4\audio\audio.sdk\standalone_bsp_0\ps7_cortexa9_0\include directory.
9 EnterTestAppas theProjectName, and for Board Support Package, choose Use Existing (standalone_bsp should be the only option)
11.SelectTestAppin the project view, right-click thesrcfolder, and selectImport
12 ExpandGeneralcategory and double-click onFile System.
13 Browse to{sources}\lab4folder and clickOK.
14 Select both zybo_testapp.c and zybo_audio.h and clickFinishto add the file to the project.
The program should compile successfully.
Verify the Design in Hardware
Connect a micro-usb cable between a PC and the JTAG port of the board. Connect an audio patch cable between the Line In jack and the speaker (headphone) out jack of a PC Connect a headphone to the Line Out jack on the board Power On the board.
1 Connect a micro-usb cable between a PC and the JTAG port of the board.
2 Connect an audio patch cable between the Line In jack and the speaker out(headphone) jack of a PC.
3 Connect a headphone to theHP+MICjack on board PowerONthe board.
5 Make sure that the system_wrapper.bit bitstream is selected and the BMM filefield is blank.
This will configure the FPGA.
7 Double-clickcorrupted_music_4KHz.wavor some other wave file of interest to play it using the installed media player Place it in the continuous play mode.
8 Right-click on theTestAppin the Project Explorer pane and select Run As > Launch On Hardware (System Debugger).
The program will be downloaded and run If you want to listen to corrupted signal then set theSW0 OFF To listened the filtered signal set theSW0 ON.
9 When done, power OFF the board.
10 Exit SDK and Vivado usingFile > Exit.
You used the INTERFACE directive to create an IP-XACT adapter in this lab.During the implementation phase, you created the IP-XACT adapter You then used IPIntegrator to create a processor system, integrate the generated IP-XACT adapter, and test the system with the provided application.