Ultra Wideband Part 8 ppt

Ultra Wideband 204 1.12.3.1 Comparisons The circuit in Figure 40 is simulated in a 0.18m CMOS technology with a power supply of 1.8V. The complete VCO with the values of its elements is shown in Figure 48. The total power is 29.1mW, with dc current of 2mA in active inductor and 17mA in the main core of oscillator. Tuning range of 3.8GHz- 7.4GHz is achieved by varying V tune from 1V to 2.5V, as shown in Figure 49. Maximum quality factor of active inductor is acquired at 3.8GHz with 0.55nH inductance. At 1MHz frequency offset, phase noise varies from -92.05dBcHz to - 70dBcHz. Fig. 48. The final circuit used for simulation Fi g C o fr o ac t 0. 6 Fi g g . 49. Frequenc y v o mparison of th e o m simulation ar t ive resistor swi t 6 1nH, as depicte d g . 50. (a) simulati o v ariation with V t u e accurac y betwe e shown in Fi g u r t ches on. As a r e d in Figure 51. o n results (b) fre q u ne en frequencies c o r e 50. V tune can b e sult, the active q uencies derived o mputed from ( 4 b e increased unti l inductor can be from equation ( 4 4 3) and those o b l the parallel N M tuned from 0.3 4 4 3) b tained M OS in 4 nH to Ultra wideband oscillators 205 1.12.3.1 Comparisons The circuit in Figure 40 is simulated in a 0.18m CMOS technology with a power supply of 1.8V. The complete VCO with the values of its elements is shown in Figure 48. The total power is 29.1mW, with dc current of 2mA in active inductor and 17mA in the main core of oscillator. Tuning range of 3.8GHz- 7.4GHz is achieved by varying V tune from 1V to 2.5V, as shown in Figure 49. Maximum quality factor of active inductor is acquired at 3.8GHz with 0.55nH inductance. At 1MHz frequency offset, phase noise varies from -92.05dBcHz to - 70dBcHz. Fig. 48. The final circuit used for simulation Fi g C o fr o ac t 0. 6 Fi g g . 49. Frequenc y v o mparison of th e o m simulation ar t ive resistor swi t 6 1nH, as depicte d g . 50. (a) simulati o v ariation with V t u e accurac y betwe e shown in Fi g u r t ches on. As a r e d in Figure 51. o n results (b) fre q u ne en frequencies c o r e 50. V tune can b e sult, the active q uencies derived o mputed from ( 4 b e increased unti l inductor can be from equation ( 4 4 3) and those o b l the parallel N M tuned from 0.3 4 4 3) b tained M OS in 4 nH to Ultra Wideband 206 Fi g 1. 1 Fo to be s vo Fi g i m Fi g g . 51. Inductance 1 2.3.2 Phase No r phase noise si m estimate the bes t s t phase noise p e lta g e for active l g ure 40). This w m proves the phas e g . 52. (a) phase n o variation with V t ise Results m ulation, differe n t performance. Si e rformance is ac h l oad, separate bi a w ill prevent qu a e noise about 4d B o ise variation b y t t une n t trade-offs bet w mulations show t h ieved. Despite [ 3 a s volta g e, Vc, c a lit y factor de gr B cHz, as shown i n t unin g V C (b) p h w een circuit ele m t hat, when C2, C 3 0], which emplo y an be utilized f o r adation due to n Figure 52. h ase noise variati o m ents may be ex a C 3 and C4 are eq u y s onl y a sin g le b o r active load M 1 increasin g V tu n o n for V C =consta n a mined u al, the b iasin g 1 1 (see n e , and n t 1. 1 T h O b w r 1. 4 vo 82 d in Fi g 1 2.3.3 Effect of B h e oscillator per f b viousl y , this wil r aps up to wors e 4 V will have ne g l lta g e will si g nifi d BcHz. Despite t Figure 53 and Fi g g . 53. Bandwidth B ias Voltage De c f ormance may a l reduce the am p e quantit y . The r e i g ible ef f ect on p h cantl y de g rade t t his, the frequen c g ure 54. with Vdd reduc t c reasing a lso be examin e p litude of oscillat i e sults of simulat i h ase noise. Neve t he phase noise, cy ran g e of opera t io n e d b y decreasin g i on. In this case, t i on at 4GHz sho w rtheless, further r such that for V D tion tends to ma i g the suppl y v o t he phase noise q w that reducin g r eduction of the s D D =1V phase no i i ntai n . These are s o lta g e. q uickl y V DD to s uppl y i se is - s hown Ultra wideband oscillators 207 Fi g 1. 1 Fo to be s vo Fi g i m Fi g g . 51. Inductance 1 2.3.2 Phase No r phase noise si m estimate the bes t s t phase noise p e lta g e for active l g ure 40). This w m proves the phas e g . 52. (a) phase n o variation with V t ise Results m ulation, differe n t performance. Si e rformance is ac h l oad, separate bi a w ill prevent qu a e noise about 4d B o ise variation b y t t une n t trade-offs bet w mulations show t h ieved. Despite [ 3 a s volta g e, Vc, c a lit y factor de gr B cHz, as shown i n t unin g V C (b) p h w een circuit ele m t hat, when C2, C 3 0], which emplo y an be utilized f o r adation due to n Figure 52. h ase noise variati o m ents may be ex a C 3 and C4 are eq u y s onl y a sin g le b o r active load M 1 increasin g V tu n o n for V C =consta n a mined u al, the b iasin g 1 1 (see n e , and n t 1. 1 T h O b w r 1. 4 vo 82 d in Fi g 1 2.3.3 Effect of B h e oscillator per f b viousl y , this wil r aps up to wors e 4 V will have ne g l lta g e will si g nifi d BcHz. Despite t Figure 53 and Fi g g . 53. Bandwidth B ias Voltage De c f ormance may a l reduce the am p e quantit y . The r e i g ible ef f ect on p h cantl y de g rade t t his, the frequen c g ure 54. with Vdd reduc t c reasing a lso be examin e p litude of oscillat i e sults of simulat i h ase noise. Neve t he phase noise, cy ran g e of opera t io n e d b y decreasin g i on. In this case, t i on at 4GHz sho w rtheless, further r such that for V D tion tends to ma i g the suppl y v o t he phase noise q w that reducin g r eduction of the s D D =1V phase no i i ntai n . These are s o lta g e. q uickl y V DD to s uppl y i se is - s hown Ultra Wideband 208 Fi g 1. 1 Si m 5 % ch a In p h 1. 1 Fo w i Fi g Fi g g . 54. Phase nois e 1 2.3.4 Effect of P m ulation results s % variation in b i a n g ed b y 0.1% w addition, mobili t h ase noise and fre 1 2.3.5 Package a r accurate simul a i res is required t g ure 55 is emplo y g . 55. Wirebondi n e versus Vdd red u P rocess Variati o s how 2% and 0.1 i as volta g e. For w hile the frequen c ty variation of N M e quency of opera t a nd Wirebond M a tion of the RF ci t o be tested [11] y ed [31]. ng and pad mod e u ctio n o ns % chan g e in freq u 10% chan g e in cy is approximat e M OS model aro u t ion, respectively M odeling rcuit, an equival e . Suppose the Q e l [31] u enc y and phas e temperature, t h e l y constant. u nd 5% shows 0. 5 . e nt model of pa d Q FN packa g e wi t e noise, respectiv e h e phase noise i 5 % and 1% variat i d includin g the b o t h equivalent m o e l y , for s onl y i ons in o ndin g o del of Si m fr e sli g co m T a 1. 1 L a pa pa ve r th e in d μ fi n sil i th e Fo fo r be t in d Fi g m ulations show e quenc y of the tu n g ht improvemen t m pared in Table Package model SOIC-20 SSOP-20 TSSOP-20 TVSOP- 20 QFN-20 a ble 1. compariso n 1 2.3.6 Oscillato r ay out desi g n can b ssive inductor m ssive inductor ( L ry low serial res i e la y out to be c h d uctor with la y e r m. Capacitors o f ng er-based archit e i con resistors ar e e desired resista n r phase noise re d r transistors. Eac h t ween cascade t d uctor la y out is d g . 56. Active ind u that addin g th e n in g ran g e from t . Other packa g e 1. Frequency (GHz) 3.8 3.8 3.8 3.8 3.8 n between differ e r Layout b e divided into t w m a y be desi g ned L in Figure 48) c a i stor. Neverthele h an g ed to one-l a r one metal. Tot a f C1 to C4 have e cture [26]. Total e also utilized wi t n ce. d uction and chip h g ate is divided t ransistors. Usin d esi g ned as sho w u ctor la y out e model elemen t 7.4GHz to 7.0G H models [32] wer Phase Noise ( d -91.84 -92.21 -92.18 -92.11 -92.25 e nt packa g e mod e w o parts as of pa usin g different a n be implement e ss, it introduces ay er desi gn [19]. a l area occupied f been desi g ned u area occupied f o t h narrow la y ers size minimizati o into number of f i g this method w w n in Figure 56. t s to the circuit H z, while the pha s e also tested for 3 d Bc/Hz) Equ i L(nH) 5.01 3.49 2.80 2.56 1.10 e ls s sive and active d la y ers of metals e d with 4 metal l a ver y lar g e par a Here “L” is de s f or the lumped i n u sin g metal la y e r o r each capacitor of pol y silicon s h o n, fin g er-based l a i n g ers, which ar e w ith pol y silico reduces the hi g s e noise will exp e 3 .8GHz. The res u i valent circuit C(pF) R(Ω) 0.71 0.03 0.42 0.04 0.31 0.05 0.34 0.04 0.35 0.05 d evices. Capacit o [19, 26]. For in s l a y ers, which ex h a sitic capacitor, f s i g ned as square n ductor is 157 μ m r s of one to four , is 20 μ m *21 μ m h aped in a wa y t o a y out has been u e utilized s y mme t n resistors, the g h-end e rience u lts are o rs and s tance, h ibits a f orcin g spiral m *157 , usin g m . Pol y o form u tilized t rically active Ultra wideband oscillators 209 Fi g 1. 1 Si m 5 % ch a In p h 1. 1 Fo w i Fi g Fi g g . 54. Phase nois e 1 2.3.4 Effect of P m ulation results s % variation in b i a n g ed b y 0.1% w addition, mobili t h ase noise and fr e 1 2.3.5 Package a r accurate simul a i res is required t g ure 55 is emplo y g . 55. Wirebondi n e versus Vdd red u P rocess Variati o s how 2% and 0.1 i as volta g e. For w hile the frequen c ty variation of N M e quenc y of opera t a nd Wirebond M a tion of the RF ci t o be tested [11] y ed [31]. ng and pad mod e u ctio n o ns % chan g e in freq u 10% chan g e in cy is approximat e M OS model aro u t ion, respectivel y M odeling rcuit, an equival e . Suppose the Q e l [31] u enc y and phas e temperature, t h e l y constant. u nd 5% shows 0. 5 . e nt model of pa d Q FN packa g e wi t e noise, respectiv e h e phase noise i 5 % and 1% variat i d includin g the b o t h equivalent m o e l y , for s onl y i ons in o ndin g o del of Si m fr e sli g co m T a 1. 1 L a pa pa ve r th e in d μ fi n sil i th e Fo fo r be t in d Fi g m ulations show e quenc y of the tu n g ht improvemen t m pared in Table Package model SOIC-20 SSOP-20 TSSOP-20 TVSOP- 20 QFN-20 a ble 1. compariso n 1 2.3.6 Oscillato r ay out desi g n can b ssive inductor m ssive inductor ( L ry low serial res i e la y out to be c h d uctor with la y e r m. Capacitors o f ng er-based archit e i con resistors ar e e desired resista n r phase noise re d r transistors. Eac h t ween cascade t d uctor la y out is d g . 56. Active ind u that addin g th e n in g ran g e from t . Other packa g e 1. Frequency (GHz) 3.8 3.8 3.8 3.8 3.8 n between differ e r Layout b e divided into t w m a y be desi g ned L in Figure 48) c a i stor. Neverthele h an g ed to one-l a r one metal. Tot a f C1 to C4 have e cture [26]. Total e also utilized wi t n ce. d uction and chip h g ate is divided t ransistors. Usin d esi g ned as sho w u ctor layout e model elemen t 7.4GHz to 7.0G H models [32] wer Phase Noise ( d -91.84 -92.21 -92.18 -92.11 -92.25 e nt packa g e mod e w o parts as of pa usin g different a n be implement e ss, it introduces ay er desi gn [19]. a l area occupied f been desi g ned u area occupied f o t h narrow la y ers size minimizati o into number of f i g this method w w n in Figure 56. t s to the circuit H z, while the pha s e also tested for 3 d Bc/Hz) Equ i L(nH) 5.01 3.49 2.80 2.56 1.10 e ls s sive and active d la y ers of metals e d with 4 metal l a ver y lar g e par a Here “L” is de s f or the lumped i n u sin g metal la y e r o r each capacitor of pol y silicon s h o n, fin g er-based l a i n g ers, which ar e w ith pol y silico reduces the hi g s e noise will exp e 3 .8GHz. The res u i valent circuit C(pF) R(Ω) 0.71 0.03 0.42 0.04 0.31 0.05 0.34 0.04 0.35 0.05 d evices. Capacit o [19, 26]. For in s l a y ers, which ex h a sitic capacitor, f s i g ned as square n ductor is 157 μ m r s of one to four , is 20 μ m *21 μ m h aped in a wa y t o a y out has been u e utilized s y mme t n resistors, the g h-end e rience u lts are o rs and s tance, h ibits a f orcin g spiral m *157 , usin g m . Pol y o form u tilized t rically active Ultra Wideband 210 Symmetric finger-based design typically helps in 10% chip size reduction. Total occupied die area is 0.22mm 2 as shown in Figure 57. Fig. 57. VCO Circuit layout 1.12.3.7 Phase Noise Reduction The noise reduction techniques were described in Section 1.11. First, the Noise filtering technique [28] is employed here. This implies LC resonating networks in the sources of M1 and M11, instead of directly connecting them to ground, as shown in Figure 58. The frequency of oscillation for LC networks is 2GHz. This helps in turning the NMOS off rapidly and having a positive impact on the phase noise. Simulation in this case shows 3dBcHz improvement in the phase noise, reducing it to -93.7dBcHz from -91.01dBcHz at the frequency of 4GHz and the offset of 1-MHz. Although this limits the frequency tuning range, it can be used as a good technique for noise reduction when narrower frequency range is required. As explained above, another technique for noise suppression is given in [29], in which a frequency to current converter extracts the noise properties of VCO output signal. This extracted current then passes through an integrator, which will converts it to a voltage carrying important noise and frequency properties. This voltage will enter a low pass filter and fed back as an input voltage to the oscillator. Fi g Al de C h ar e w i pr e T a g . 58. Noise filter i thou g h this me t crease in phase n h aracteristics of t h e shown in Table i der tunin g ran ge e sented in this s e a ble 2. brief chara c i n g technique t hod has been t e n oise, here we ob t h e proposed VC O 2 and Table 3, r e e with better no i e ctio n . Technology Power supply Bias current Power Dissipation Frequency Ran g Phase noise c teristics of prop o e sted for rin g o s t ain onl y 1dBC/ H O and also a nu m e spectivel y . Com p i se performance 0.18 μ m C 1 g e 3.8 G -92.05 ~ -75 o sed VCO s cillators [34] a n H z improvement m ber of previous l p arison with sim i and g ain factor C MOS Technolo g 1.8V 1 7.21mA 29.1mW Hz ~ 7.4GHz .42 dBc/Hz @1 M n d shows a si gn for UWB oscillat ly simulated osc i i lar desi g ns illus t for the UWB os c gy M Hz n ificant or. i llators t rates a c illator Ultra wideband oscillators 211 Symmetric finger-based design typically helps in 10% chip size reduction. Total occupied die area is 0.22mm 2 as shown in Figure 57. Fig. 57. VCO Circuit layout 1.12.3.7 Phase Noise Reduction The noise reduction techniques were described in Section 1.11. First, the Noise filtering technique [28] is employed here. This implies LC resonating networks in the sources of M1 and M11, instead of directly connecting them to ground, as shown in Figure 58. The frequency of oscillation for LC networks is 2GHz. This helps in turning the NMOS off rapidly and having a positive impact on the phase noise. Simulation in this case shows 3dBcHz improvement in the phase noise, reducing it to -93.7dBcHz from -91.01dBcHz at the frequency of 4GHz and the offset of 1-MHz. Although this limits the frequency tuning range, it can be used as a good technique for noise reduction when narrower frequency range is required. As explained above, another technique for noise suppression is given in [29], in which a frequency to current converter extracts the noise properties of VCO output signal. This extracted current then passes through an integrator, which will converts it to a voltage carrying important noise and frequency properties. This voltage will enter a low pass filter and fed back as an input voltage to the oscillator. Fi g Al de C h ar e w i pr e T a g . 58. Noise filter i thou g h this me t crease in phase n h aracteristics of t h e shown in Table i der tunin g ran ge e sented in this s e a ble 2. brief chara c i n g technique t hod has been t e n oise, here we ob t h e proposed VC O 2 and Table 3, r e e with better no i e ctio n . Technology Power supply Bias current Power Dissipation Frequency Ran g Phase noise c teristics of prop o e sted for rin g o s t ain onl y 1dBC/ H O and also a nu m e spectively. Com p i se performance 0.18 μ m C 1 g e 3.8 G -92.05 ~ -75 o sed VCO s cillators [34] a n H z improvement m ber of previous l p arison with sim i and g ain factor C MOS Technolo g 1.8V 1 7.21mA 29.1mW Hz ~ 7.4GHz .42 dBc/Hz @1 M n d shows a si gn for UWB oscillat ly simulated osc i i lar designs illust for the UWB os c gy M Hz n ificant or. i llators t rates a c illator Ultra Wideband 212 Year Freq. range GHz K VCO (MHz/V) Process Ref. 2001 4.20 ~ 5.05 340 0.25um [35] 2005 2.70 ~ 5.40 1687 0.18um [30] 2005 0.50 ~ 2.0 500 0.18um [27] 2005 1.14 ~ 2.46 270 0.18um [7] 2005 1.90 ~ 2.19 116 0.18um [34] 2007 3.80 ~ 7.40 2400 0.18um [19] Table 3. comparison with Previously simulated VCOs 1.13 Summary This chapter has explored the techniques for VCO design with wide tuning range. An overview of various wideband tuning solutions proposed in the literature and the associated design challenges have been discussed. Wideband (Ultra Wideband) oscillators can be realized by carefully designing passive and active devices. The techniques for sizing and layout design of active and passive elements are discussed to optimize the phase noise performance of oscillators. The feasibility of CMOS VCO capable of multi-GHz operation has been demonstrated. The performance of the VCOs highlight the higher tuning ranges achieved in the case of inductive tuning. The VCO based on inductive tuning, realized by the tunable active inductor (TAI) using a 0.18m CMOS technology, can provide a tuning range between 0.5–2.0 GHz and 3.8-7.4GHz using Colpitts and Hartley structures, respectively. Also, it is shown that with phase noise reduction techniques such as PLL-based feedback and harmonic tuning, the phase noise can be improved for 1-3dB. 1.14 References [1] A. Hajimiri and T. Lee, “Design Issues in CMOS Differential LC Oscillators,” IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 717–724, 1999. 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[...]... voltage gain and the noise figure for a 6 .8- 8 .8 GHz LNA prototype A good agreement between measured and simulated results is also observed 0 S(1,1), (dB) -5 -10 -15 -20 mesurement simulation with lines simulation without lines -25 -30 2 4 6 8 Freq (GHz) 10 12 14 Fig 11 Simulated and measured input return loss for a 6 .8- 8 .8 GHz LNA Design and implementation of ultra- wide-band CMOS LC filter LNA 30 20... Electron Devices Letters, vol 26, no 4, pp 2 58- 260, 2005 [23] A Kral, F Behbahani, and A A Abidi, “RF-CMOS Oscillators with Switched Tuning,” IEEE Custom Integrated Circuits Conference, pp 555-556, 19 98 [24] Chung-Yu Wu, Chi-Yao Yu, “A 0.8V 5.9GHz wide tuning range CMOS VCO using inversion-mode band switching varactors,” IEEE Conference, pp 5079-5 082 , 2005 214 Ultra Wideband [25] Neric Fong, Jean-Olivier... Techniques, vol 53, no 1, pp 81 -93, 2005 [31] Sajay Jose, Design of RF CMOS Power Amplifier for UWB Applications, MS Thesis, Blacksburg, Virginia, 2004 [32] Frank Mortan, Lans Wright, Quad Flatpack No-Lead Logic Packages, Application Report, Texas Instruments [33] M Mehrabian, A Nabavi, N.Rashidi, “A 4~7GHz Ultra Wideband VCO with Tunable Active Inductor,” ICUWB 20 08, pp 21-24, 20 08 [34] Khouzema B Unchwaniwala,... allowing an increase of the M 1 size This way (16) becomes:  S 2  GS b   S 2   GS g 2 (36) 226 Ultra Wideband and both the noise minimization and the power matching can be achieved by taking a M1 width leading to (37): A.g3  (37) A.g3 b  g2  ( 38)  GS  Provided ( 38) is satisfied  GS  If ( 38) is not satisfied another way is to use a parallel capacitor between the gate and the source terminals... with relations (14) –( 18) 2 28 Ultra Wideband S2 S2   M11 M12 S1 P1/2 S2 S2 S2 Fig 7 Input matching cell for large fractional bandwidths (a) Second order LC ladder filter (b) Single ended input matching cell implementation (c) Differential ended input matching cell 5.3 Differential ended LNA architectures A fully differential ended LNA architecture is shown in Fig 8 where the first and the.. .Ultra wideband oscillators 213 [8] J S Dunn et.al “Foundation of RF CMOS and SiGe BiCMOS technologies,” IBM J Res & Dev., vol 47, no 2/3, pp 101-1 38, 2003 [9] Krzysztof Iniewski, Wireless Technologies_Circuits, Systems, and Devices, CRC Press, Taylor& Francis Group, 20 08 [10] K T Christensen, “Low Power RF Filtering for CMOS Transceivers,”... The element values of the normalized input matching cell are given by relations (14)-( 18) where gi are the normalized values of the second order Tchebycheff Low-Pass ladder filter and b the fractional bandwidth 222 Ultra Wideband  P1  g1 b (14) P1  b g1 (15)  GS  b g2 (16) S 2  S  rIN  g2 b 1 g3 (17) ( 18) The overall series inductor value LS2 + LS is reduced by using an even Tchebycheff... Proceedings of the 25th Solid-State Circuits Conference, pp 1 98 201, 1999 [15] Chien-Cheng Wei, Hsien-Chin Chiu and Wu-Shiung Feng “An Ultra- Wideband CMOS VCO with 3-5GHz Tuning Range,” IEEE International Workshop on Radio-Frequency Integration Technology, 2005 [16] Chao-Chih Hsiao, Chin-Wei Kuo, Chien-Chih Ho and Yi-Jen Chan, “Improved QualityFactor of 0. 18- μm CMOS Active Inductor by a Feedback Resistance Design,”... LNA Design and implementation of ultra- wide-band CMOS LC filter LNA 30 20 231 Simulated Gv 30 Measured Gv 20 10 0 0 S11, Gv, dB 10 -10 -10 -20 -20 -30 4 6 8 Frequency, GHz 10 12 14 -30 Fig 12 Simulated and measured voltage gain loss for a 6 .8- 8 .8 GHz LNA 6.2 LNA implementation in UWB System on Chip The methodology presented in section 6.1 has been validated on several stand alone LNA for different... because of the great number of spiral inductors (8) Heydari (Heydari, 2007) has also used a distributed amplifier architecture in a 0. 18 m CMOS technology The originality of this design is to use bandwidth enhancing inductors So the full FCC bandwidth is obtained with a good noise figure but with high power consumption (21mW) However the gain is low (8dB) and the number of inductors very high (11 spiral . [35] 2005 2.70 ~ 5.40 1 687 0.18um [30] 2005 0.50 ~ 2.0 500 0.18um [27] 2005 1.14 ~ 2.46 270 0.18um [7] 2005 1.90 ~ 2.19 116 0.18um [34] 2007 3 .80 ~ 7.40 2400 0.18um [19] Table 3. comparison. Other packa g e 1. Frequency (GHz) 3 .8 3 .8 3 .8 3 .8 3 .8 n between differ e r Layout b e divided into t w m a y be desi g ned L in Figure 48) c a i stor. Neverthele h an g ed to one-l a r . Other packa g e 1. Frequency (GHz) 3 .8 3 .8 3 .8 3 .8 3 .8 n between differ e r Layout b e divided into t w m a y be desi g ned L in Figure 48) c a i stor. Neverthele h an g ed to one-l a r