Signals and data types in VHDL

[...]... have its type defined VHDL provides scalar and composite data types Enumerated types can be used to enhance code readability A two-dimensional array can be created to model memory structures VHDL subtypes are constrained versions of existing types Aggregate assignments can be made for arrays and records Types on connecting signals must match ... means for initializing the 2-D array • type ROM_ARRAY is array ( 0 to 3 ) of std_logic_vector ( 7 downto 0); constant MY_ROM : ROM_ARRAY := continued below 7 0 1 2 3 6 5 4 3 2 1 0 constant MY_ROM : ROM_ARRAY := ( 0 => (others => ‘1’) , 1 => “10100010”, 2 => “00001111”, 3 => “11110000” ) ; Summary • • • • • • • Each object and port must have its type defined VHDL provides scalar and composite data types. .. BUS_C 0 1 2 Inadvertent bit-swap? 3 Array Assignment Notation • To simplify array assignments and enhance readability—you can designate a hexadecimal or octal base – Underscores can also be used to further enhance readability signal DATA_ WORD : std_logic_vector (11 downto 0) ; DATA_ WORD . • Declare ports and signals using appropriate data types • List possible values for each data type • Declare scalar and composite data types – array and records • Declare one-dimensional and two-dimensional. and two-dimensional arrays • Declare and use VHDL subtypes Data Types • The wide range of available data types provides flexibility in hardware modeling and built-in error checking to ensure. signal assignment and data type std_logic G O O D Composite Data Types • Composite data types are groups of elements in the form of an array or record – Bit_vector, Std_logic_vector, and String are