Ultra Wideband Communications Novel Trends System, Architecture and Implementation Part 11 potx

A Method for Improving Out-Of-Band Characteristics of a Wideband Bandpass Filter in an LTCC Substrate 239 C a1 0.27pF Z S1 46.3 ohm Z So 45.7 ohm 2S θ 10 deg. C a2 0.25pF Z Se 45.9 ohm 1S θ 18 deg. 3S θ 5 deg. Table 2. Parameters of the lowpass filters shown in Fig.7. Fig. 8. Simulated results of the filter shown in Fig.7. Fig. 9. Simulated results of the filter shown in Fig.7, when the coupling condition of the stripline is varied. Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation 240 4. LTCC structure Fig.10, Fig.11 and Fig.12 indicate the LTCC structure of the filter. The filter is obtained by means of modifying the structure based on the basic circuit shown in Fig.7, taking into consideration the various parasitic effects caused by the three-dimensional LTCC structure. The filter consists of the three conductor layers inserted into the middle portion of the LTCC substrate, with the ground planes on the top and bottom layers. The conductor thickness is 8 um. The diameter of via holes is 0.1 mm. The ground planes are connected by the via holes. The via hole between the coupled line adjusts the coupling condition. The dimensions of the bandpass filter are 6.2 x 2.7 x 0.366 mm 3 , and this size could be fabricated into the LTCC substrate for wireless modules. Fig.13 shows the simulated results using a commercial electromagnetic simulator (HFSS Ansys Inc.). The filter has the wide passband and suppresses second and third harmonics. The filter also has an additional attenuation pole at the low-frequency region. Fig. 10. Three-dimensional structure of the filter. Fig. 11. Cross sectional structure of the filter. A Method for Improving Out-Of-Band Characteristics of a Wideband Bandpass Filter in an LTCC Substrate 241 Fig. 12. Top view of the filter. Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation 242 Fig. 13. Simulated results by the electromagnetic simulator. 5. Experiments We verify the effectiveness of the presented method by experiments. Fig. 14 indicates the LTCC structure for the evaluation of the embedded filter. The dimensions of the LTCC Fig. 14. Structure of the LTCC substrate for evaluation. A Method for Improving Out-Of-Band Characteristics of a Wideband Bandpass Filter in an LTCC Substrate 243 substrate are 8.0 x 5.0 x 0.63 mm 3 . The presented filter (6.2 x 2.7 x 0.366 mm 3 ) is fabricated in the substrate. In order to connect the SMA connectors for the evaluation, the top layer of the LTCC substrate has the electrodes for RF signals and a ground plane. The feed lines between the filter and the input/output ports consist of a via hole, a stripline, and the electrode of the top layer. These feed lines are designed 50 ohm. Fig. 15 shows a photograph of the LTCC substrate. The prototype which is connected to the SMA connectors is measured by a vector network analyzer (N5230A PNA-L, Agilent Technologies Inc). Fig.16 and Fig.17 indicate the measured results. It is confirmed that the filter suppresses the spurious responses less than 20 dB up to 16 GHz and has an additional attenuation pole in the low-frequency region. In addition, the insertion loss is less than 3.0dB and the group delay is within 1 ns in the wide passband. Fig. 15. Photograph of the prototype. Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation 244 Fig. 16. Measured results of the filter shown in Fig.15. Fig. 17. Measured group delay of the filter shown in Fig.15. A Method for Improving Out-Of-Band Characteristics of a Wideband Bandpass Filter in an LTCC Substrate 245 6. Conclusion In this study, we propose a method for improving out-of-band characteristics for the wideband filter in the LTCC substrate. This method uses the lowpass filters with the coupling structure, which are set at input and output ports of the bandpass filter. This method is very useful for the compact wireless modules because additional compact circuits can suppress spurious responses and can add an attenuation pole in the low-frequency band. The fabricated UWB bandpass filter for the low-frequency band achieves the insertion loss less than 3.0 dB and the group delay within 1 ns in the wide passband. The filter also suppresses spurious responses up to 16 GHz and has the good attenuation performances in the low-frequency region. 7. References Lin, Y S., Liu, C C., Li,K M., & Chen, C.H. (2004). Design of an LTCC tri-band transceiver module for GPRS mobile applications. IEEE Transactions on Microwave Theory and Techniques , Vol. 52, No. 12, pp. 2718-2724. Wang, G., Van, M., Barlow, F. & Elshabini, A. (2005). An interdigital bandpass filter embedded in LTCC for 5- GHz wireless LAN applications. IEEE Microwave and Wireless Components Letters,Vol. 15, No. 5, pp. 357-359. Ishida, H. & Araki, K. (2004). Design and analysis of UWB bandpass filter with ring filter. IEEE MTT-S International Microwave Symposium, pp. 1307-1310. Saitou, A., Aoki, H. , Satomi, N., Honjo, K., Sato, K., Koyama, T. & Watanabe, K.(2005). Ultra-wideband differential mode bandpass filters embeded in self-complementary antennas. IEEE MTT-S International Microwave Symposium, pp. 717-720. Li, K., Kurita, D. & Matsui, T. (2005).An ultra-wideband bandpass filter using broadside- coupled microstrip-coplanar waveguide structure. IEEE MTT-S International Microwave Symposium., pp. 675-678. Zhu, L., Sun, S. & Menzel, W.(2005). Ultra-wideband (UWB) bandpass filters using multiple- mode resonator. IEEE Microwave and Wireless Components Letters, Vol. 15, No. 11, pp. 796-798. Horii, Y. , Tanaka, A., Hayashi, T., & Iida, Y.(2006). A compact multi-layered wideband bandpass filter exhibiting left-handed and right-handed behaviors. IEICE Transactions on Electronics , Vol. E89-C, No. 9, pp. 1348-1350. Yamamoto, Y., Li, K. & Hashimoto, O.(2007). Ultra-wideband (UWB) bandpass filter using shunt stub with lumped capacitor. IEICE Electronics Express, Vol. 4, No.7, pp. 227- 231. Shaman, H. & Hong, J S.(2007). Input and output cross-coupled wideband bandpass filter. IEEE Transactions on Microwave Theory and Techniques, Vol. 55, No. 12, pp. 2562-2568. Tanii, K., Shimizu, Y., Nishimura, F., Sasabe, K., Ueno, Y., Wada, K. & Iwasaki,T.(2008) A study of various wide-band BPFs with attenuation poles using distributed tap- coupling microstrip-line resonators. IEICE Transactions on Electronics (Japanese Edition), Vol.J91-C , No.6 , pp.332-340. Sun, S. & Zhu, L.(2009). ``Multimode-resonator-based bandpass filters. IEEE Microwave magazine, Vol. 10, No. 2, pp. 88-98. Oshima, S., Wada, K., Murata, R., & Shimakata, Y. (2008). A study of a compact multilayer wideband bandpass filter in LTCC substrate using distributed resonator with Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation 246 attenuation poles consisted of a capacitor and λ/2 open-ended stub,” IEICE Transactions on Electronics (Japanese Edition) , Vol.J91-C, No.8, pp.409-417. Oshima, S., Wada, K., Murata, R., & Shimakata, Y.(2010) . Multilayer dual-band bandpass filter in low temperature co-fired ceramic substrate for ultra-wideband applications. IEEE Transactions on Microwave Theory and Techniques, Vol.58, No.3, pp.614-623. Ghorashi, S.A., Allen,B., Ghavami, M., & Aghvami, A.H. (2004). An overview of MB-UWB OFDM, IEE Seminar on Ultra Wideband Communications Technologies and System Design, 2004 . , pp.107- 110. Kurita,D.& Li, K. (2007). Super UWB lowpass filter using open-circuited radial stubs. IEICE Electronics Express , Vol.4, No.7, pp.211-215. Ohwada, T., Ikematu, H., Oh-hashi, H., Takagi, T. & Ishida, O.,(2002). A Ku-band low-loss stripline low-pass filter for LTCC modules with low-impedance lines to obtain plural transmission zeros. IEEE MTT-S International Microwave Symposium, pp. 1617-1620. 13 Calibration Techniques for the Elimination of Non-Monotonic Errors and the Linearity Improvement of A/D Converters Nikos Petrellis 1 and Michael Birbas 2 1 Technological Educational Institute of Larisa, 2 Analogies SA Greece 1. Introduction The Analogue/Digital Converters (ADCs) play a very important role in several wideband applications like wired and wireless high speed telecommunication systems (e.g., 802.11g) or communication over powerlines (IEEE P.1901). High definition TV or high precision real time image processing are also examples of applications that require a conversion rate of several hundreds MSamples/sec or even multi-GSsamples/sec. While the ADCs may operate in an optimal way when they are initially designed and verified using DC simulation, a transient simulation can designate several problems that appear during the high speed operation. Additional linearity errors are posed by process variations and component mismatches after the chip fabrication. Finally, operating conditions like voltage supply levels and temperature variations can also affect the linearity of an ADC. Several foreground and background calibration techniques have been proposed in the literature. Most of them are developed for specific ADCs and cannot be applied to different ADC architectures. The most important error sources and the most popular calibration methods for Pipelined, Segmentation/Reassembly and Sigma Delta ADCs as well as a number of generic error compensation methods based on the processing of the ADC output are presented in (Balestrieri et al, 2005). A popular error correction technique used in pipelined ADCs exploits the least significant bit of a “coarse” ADC stage for the error detection and correction. For example, in (Colleran & Abidi, 1993) a 10-bit ADC is constructed by a 4-bit “coarse” and a 7-bit “fine” ADC. The least significant bit of the coarse ADC should match the most significant bit of the fine ADC. Similarly, a 10-bit pipeline ADC consists of a coarse 6-bit and a fine 5-bit ADC in (Sone et al, 1993). Two more recent approaches that are described in (Kurose et al, 2006) and in (Ahmed & Johns, 2005)(Ahmed & Johns, 2008) use 8 stages of 1.5-bit and a 2-bit Flash ADC stage in a 10-bit (or 11-bit in (Ahmed & Johns, 2008)) pipelined ADC architecture. Moreover, in (Ahmed & Johns, 2008), the DAC linearity errors are also taken into consideration. The use of a redundant signed digit also appears at an Analogue-to-Quaternary pipelined converter in (Chan et al, 2006). The ADC architectures that are based on high precision capacitors suffer from the effects of the mismatch. In (Wit et al, 1993), an additional array of capacitors is used for real time Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation 248 trimming that is performed by an algorithm implemented on-chip in order to handle component ageing. Trimming arrays are also used in (Ohara et al, 1987). A digital calibration of the capacitor mismatch, the comparator offsets and the charge injection offsets in a pipelined ADC is performed in (Karanicolas et al, 1993) for the improvement of DNL errors. The biasing of the operational amplifiers used in a pipelined ADC according to the power supply, the temperature and the sampling speed is determined by calibration in (Iizuka et al, 2006). The offset of the residue amplifiers is calibrated in the background in (Ploeg et al, 2005) (Van De Vel, 2009). Background calibration is also performed in (McNeill et al, 2005) where two identical algorithmic ADCs operate in parallel, their output is averaged and any difference in their results steers the calibration procedure. In (Wang et al, 2009), a nested digital calibration method is described for a pipeline ADC that does not require an input Sample/Hold Amplifier. A digital background calibration technique is proposed in (Hung & Lee, 2009) to correct gain errors in pipelined ADCs. This calibration technique performs the error estimation and the adaptive error correction based on the concept of split ADCs. In (Sun et al, 2008), a technique called Commutated Feedback Capacitor Switching is used to extract information about the mismatches of the capacitors used and then this information is exploited by a digital background calibration method. Post processing techniques offer a different approach to the linearity error reduction of the ADCs. While all the aforementioned techniques target to the correction of the error sources, the post processing methods operate on the ADC output. The Differential or Integral Non- Linearity (DNL/INL) errors can be measured in order to estimate correction factors for each output code. These correction factors are stored in large lookup tables and are added to or subtracted from the corresponding output codes at real time. These lookup tables are also subject to real time calibration as described in (De Vito et al, 2007). The estimation of the correction factors can be performed in the simplest case by applying successive DC levels at the ADC input and measuring the DNL of the generated ADC output codes (Provost & Sanchez-Sinencio, 2004). More sophisticated techniques apply a sinusoidal signal to the ADC input and construct a Histogram using the resulting ADC output in order to estimate the DNL errors and consequently the correction factors (Correa-Alegria & Cruz-Sera, 2009). In this chapter, some representative calibration approaches presented in the literature are described emphasising on the more general ones in the sense that they can be applied to different ADC architectures. Moreover, the calibration schemes proposed by the authors in a current mode implementation of a 12-bit ADC with a novel binary tree structure (Petrellis et al, 2010a) as well as in a voltage mode subrange ADC (Petrellis et al, 2010b, 2010c) are also presented since they can also be used in different target applications. 2. Resistor and capacitor trimming The highest speed ADCs are based on the Flash or Parallel architecture where the input signal is concurrently compared to 2 n reference levels generated by a resistor ladder consisting of identical resistors R. The Flash ADCs cannot offer a high resolution (it is practically lower than 8-bits) since the required area and power is increased in an exponential manner. Linearity is essential in these ADCs in order to prevent the already low dynamic resolution from a further reduction. [...]... 840mV A similar biasing approach may be chosen for the differential signal at the bottom of Fig 16 to avoid missing codes 262 Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation Nevertheless, in this case the codes of the binary form x0000 and x 1111 will have a significantly higher DNL error than the others due to the teeth clipping In fact, the DNL of these output codes... shown in Fig 8 at the residue of the root ADC divider of Fig 6 256 Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation Residue Residue Non-monotonic errors interval Bad linearity interval Time Fig 8 Residue imperfections A simple way to handle this kind of problem is to detect the changes in the bit No 4 and keep the previous ADC output stable for an interval equal to... Input Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation S/H + S/H - m+1 bit Coarse ADC n bit Fine ADC D m-MSBs A C Least significant bit Most significant bit m-MSBs Correct operation indication n- LSBs Fig 2 Two stage pipeline ADC with a redundant bit correction 4 Bias adjustment The biasing of the operational and differential amplifiers used in several ADC architectures... Analogue Input Fig 11 Non-monotonic error reduction with the use of the BUSY signal 9 Correction of differential signals in voltage mode ADCs High speed conversion is achieved by ADCs that operate on differential signals The differential amplifiers are faster because the stage that converts the differential signal to a 258 Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation. .. lookup table and are accessed at real time in order to determine how the current output code should be altered to improve linearity The DNL error is defined using the ADC transfer function shown in Fig 4 In the ideal case, any output code should have the same width as the Least Significant Bit (LSB): LSB  Vref 2n (3) 252 Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation. .. range that was detected if this time interval has an appropriate duration The switches S0-S2 of Fig 13b can be directly connected to the output of the 2nd Counter 260 Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation Start Calibration EN Counter 1 CK System Clock Combinatorial Logic EN Counter 2 + V Monitored Signal … CK + Threshold Vcmp S0 S1 - Comparator Fig 14 Frequency... expressed as a multiple of the reference Iref Iref Iref Iin 2Iref Iin (N-1)Iref Iin qIref Vcc W/L W/L 2W/L Iref Iref 2Iref Fig 5 A current mode integer divider Vcc 254 Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation current Iref All the Iref current sources are implemented using current mirrors with equally sized transistors, while the 2Iref, 3Iref, etc, levels are... of Fig 5 A novel ADC architecture based on integer division was presented in (Petrellis et al, 2010a) and is shown in Fig 6 A binary tree structure is used and each node of the tree implements L an integer division by a number of the form: 2 2 , where L is the level of the tree (leaves are assigned to level L=0) The quotient and the residue of such a division are the outputs of each node and are connected... Non-Monotonic Errors and the Linearity Improvement of A/D Converters 263 Colleran, W & Abidi, A (1993) A 10-b 75MHz Two-Stage Pipelined Bipolar A/D Converter IEEE Journal of Solid State Circuits, Vol 28, No 12, pp 118 7 -111 9 Correa-Alegria, F & Cruz-Sera, A (2009) Precision of Independently Based Gain and Offset Error of an ADC Using the Histogram Method IEEE Transactions on Instrumentation and Measurement,... level shifting, delay insertion, frequency range detection and bias adjustment 12 Acknowledgement Part of this work has been supported by Analogies SA and is patent pending (Application No PCT/GB2009/0 5110 1) 13 References Ahmed, I & Johns, D (2005) A 50MS/s (35mW) to 1kS/s(15uW) Power Scalable 10-bit Pipelined ADC Using Rapid Power-On Opamps and Minimal Bias Current Variation IEEE Journal of Solid State . of the stripline is varied. Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation 240 4. LTCC structure Fig.10, Fig .11 and Fig.12 indicate the LTCC structure. distributed resonator with Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation 246 attenuation poles consisted of a capacitor and λ/2 open-ended stub,” IEICE. (3) Ultra Wideband Communications: Novel Trends – System, Architecture and Implementation 252 Fig. 4. DNL error The parameter V ref is the maximum input voltage of the ADC and n is