Advances in PID Control Part 15 doc

PID Controller Using FPGA Technology 269 Fig. 16. Answer of the system in open buckle (݉<1). According to this answer, one verifies that the tension of exit stabilizes with oscillations (m <1) nearly to the value 1,4V. 4.2.2.2 System answer results with P regulator For an order (ref) of the order of 2V applied to the system ordered by a Proportional regulator (P) with KP = 2, one gets the answer y (t) presented on the following Figure Fig. 17. Answer of the system ordered by proportional regulator P. Advances in PID Control 270 One notices that this answer presents a static mistake of the order of 40%. Theoretically this mistake is given by: ଵ ଵା௄ ೛ ∙௄ ೞ ∙100%= 42%. 4.2.2.3 System answer results with PD regulator For an order (ref) of the order of 2V applied to the system ordered by a PD regulator with KP = 2,KD=1 one gets the answer y (t) presented on the following Figure Fig. 18. Answer of the system ordered by proportional regulator P D. ( ݉<1) One notices that the answer gotten present less oscillations that the one with the regulating P thanks to the Derivative action. 4.2.2.4 System answer results with PI regulator For an order (ref) of the order of 2V applied to the system ordered by a PI regulator with KP=2, KI=0,5 one gets the answer y (t) presented on the following Figure. PID Controller Using FPGA Technology 271 Fig. 19. Answer of the system ordered by proportional regulator P I. (݉<1) one notices the annulment of the static mistake well thanks to the introduction of the I action 4.2.2.5 System answer results with PID regulator For an order (ref) of the order of 2V applied to the system ordered by a PI D regulator with KP = 2, KD=1 and KI=0, 5 one gets the answer y (t) presented on the following Figure Fig. 20. Answer of the system ordered by proportional regulator P ID. Advances in PID Control 272 (݉<1) One notices that with the addition of the Derivative action, one has a light reduction of the oscillations in relation to the answer gotten by a regulating PI. 4.3 Tentative evaluation of sampling period While following the evolution of the order u (t) one could estimate the value of the sampling period experimentally (T) as it’s indicated in the following figure Fig. 21. Tentative evaluation of the sampling period (T). According to the figure 21, one estimates the value of the sampling period (T) that is the order of 6,7µs. 5. Conclusion A digital PID controller implemented in FPGA technology is a configurable controller in terms of latency, resolution, and parallelism. PID Controller Using FPGA Technology 273 The speed or execution or latency of the controller can be precisely controlled with the amount of reuse of arithmetic elements such as the speed of execution of FPGA based PID controller can be less then 100 ns if desired for high throughput requirements. Implementing PID controllers on FPGAs features speed, accuracy, power, compactness, and cost improvement over other digital implementation techniques. In a future fork we plan to investigate implementation of fuzzy logic controllers on FPGAs. Also we plan to explore embedded soft processors, such as MicroBlaze, and study some applications in which design partitioning between software and hardware provides better implementations. 6. References [1] L. Samet, N. Masmoudi, M.W. Kharrat, L. Kamoun: A Digital Pid Controller for Real Time and Multi Loop Control, 5ème Colloque d'Informatique Industrielle CII'98 8,9 et 10 février 1998,Djerba Tunisie [2] H. D. Maheshappa, R. D. Samuel, A. Prakashan, “Digital PID controller for speed control of DC motors”, IETE Technical Review Journal, V6, N3, PP171-176, India 1989 [3] J. Tang, “PID controller using the TMS320C31 DSK with on-line parameter adjustment for real-time DC motor speed and position control”, IEEE International Symposium on Industrial Electronics, V2, PP 786-791, Pusan 2001. [4] Mohamed Abdelati, the Islamic University of Gaza, Gaza, Palestine:" FPGA-Based PID Controller Implementation". [5] K. Nurdan, T. Conka-Nurdana, H. J. Beschc, B. Freislebenb, N. A. Pavelc, A. H.Walentac, “FPGA-based data acquisition system for a Compton camera”, Proceedings of the 2nd International Symposium on Applications of Particle Detectors in Medicine, Biology and Astrophysics, V510, N1, PP. 122-125, Sep 2003. [6] R. Jastrzebski, A. Napieralski,O. Pyrhonen, H. Saren, “Implementation and simulation of fast inverter control algorithms with the use of FPGA circuit”, 2003 Nanotechnology Conference and Trade Show, pp 238-241, Nanotech 2003. [7] Lin, F.S.; Chen, J.F.; Liang, T.J.; Lin, R.L.; Kuo, Y.C. “Design and implementation of FPGA-based single stage photovoltaic energy conversion system”, Proceedings of IEEE Asia Pacific Conference on Circuits and Systems, pp 745-748, Taiwan, Dec. 2004. [8] Bouzid Aliane and Aladin Sabanovic, “Design and implementation of digital band pass FIR filter in FPGA”, Computers in Education Journal, v14, p 76-81, 2004. [9] M. Canet, F. Vicedo,V. Almenar, J. Valls, “FPGA implementation of an IF transceiver for OFDM-basedWLAN”, IEEEWorkshop on Signal Processing Systems, SiPS: Design and Implementation, PP 227-232, USA 2004. [10] Xizhi Li, Tiecai Li, “ECOMIPS: An economic MIPS CPU design on FPGA”, Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, PP 291-294, Canada 2004. [11] R. Gao, D. Xu,J. P. Bentley, “Reconfigurable hardware implementation of an improved parallel architecture for MPEG-4 motion estimation in mobile applications”,IEEE Transactions on Consumer Electronics, V49, N4, November 2003. [12] S. Poussier, H. Rabah, S. Weber, “Smart Adaptable Strain Gage Conditioner: Hard- ware/Software Implementation”, IEEE Sensors Journal, V4, N2, April 2004. Advances in PID Control 274 [13] L. Samet, "Etude de l'intégration électronique en technologie FPGA d'un algorithme de contrôle de processus: le PID" Thèse Docteur Ingénieur, ENIS-TUNISIE, décembre 1996 . Conclusion A digital PID controller implemented in FPGA technology is a configurable controller in terms of latency, resolution, and parallelism. PID Controller Using FPGA Technology 273 . “Digital PID controller for speed control of DC motors”, IETE Technical Review Journal, V6, N3, PP171-176, India 1989 [3] J. Tang, PID controller using the TMS320C31 DSK with on-line parameter. Advances in PID Control 274 [13] L. Samet, "Etude de l'intégration électronique en technologie FPGA d'un algorithme de contrôle de processus: le PID& quot; Thèse Docteur Ingénieur,