[...]... RPS Electronic Device Architectures for the Nano -CMOS Era “ch01” 2008/7/28 7 Electronic Device Architectures for the Nano -CMOS Era Which are the main showstoppers for CMOS scaling? In this paper, we focus on the possible solutions to investigate and guidelines for research in the next years in order to propose solutions to enhance CMOS performance before we need to skip to alternative devices In other... CMOS Nanoelectronics Reaching the End of the Roadmap 1 RPS Electronic Device Architectures for the Nano -CMOS Era This page intentionally left blank “ch01” 2008/7/28 2 RPS Electronic Device Architectures for the Nano -CMOS Era “ch01” 2008/7/28 Sub-section 1.1 ………………………………… Core CMOS 3 RPS Electronic Device Architectures for the Nano -CMOS Era This page intentionally left blank “ch01” 2008/7/28 4 RPS Electronic. . .Electronic Device Architectures for the Nano -CMOS Era “intro” 2008/7/28 Electronic Device Architectures for the Nano -CMOS Era (2) introduce new devices, systems architectures or paradygms Beyond CMOS These questions are very much linked to the progress law that microelectronics has been following since the 1960’s.2 In the 1960’s, Gordon Moore2 first reported a progress law of microelectronics... Electronic Device Architectures for the Nano -CMOS Era “ch01” 2008/7/28 Electronic Device Architectures for the Nano -CMOS Era HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating also new disruptive devices For these devices, the low parasitics required to obtain high performance circuits, makes competition against logic CMOS extremely challenging 1 International... gate insulator ϕMS Cox = 12 S Deleonibus et al 12 RPS Electronic Device Architectures for the Nano -CMOS Era “ch01” 2008/7/28 Electronic Device Architectures for the Nano -CMOS Era is the difference between the workfunctions of the gate and the semiconductor; Qox is the oxide charge density; ϕM and ϕS are the metal and the semiconductor workfunction Gate depletion and quantum confinement in the inversion... CMOS Scaling CMOS device engineering consist of minimizing leakage current together with maximizing the output current In sub 100 nm CMOS devices, non stationary transport gains more importance as compared to diffusive transport Physical and Technological Limitations of NanoCMOS Devices 7 RPS Electronic Device Architectures for the Nano -CMOS Era “ch01” 2008/7/28 8 Electronic Device Architectures for the. .. S Deleonibus x RPS Electronic Device Architectures for the Nano -CMOS Era “intro” 2008/7/28 Electronic Device Architectures for the Nano -CMOS Era of CMOS gate oxide cannot satisfy anymore the power dissipation specifications required to design practical and usable chips for the increasing Nomadic market needs Other roadblocks appeared in microelectronics history in the 90’s such as the whole interconnect... Limitations of NanoCMOS Devices 13 13 RPS Electronic Device Architectures for the Nano -CMOS Era “ch01” 2008/7/28 Electronic Device Architectures for the Nano -CMOS Era roughness These contributions will be added to the films interface roughness and thickness fluctuations to affect transport properties or noise figures at the level of a device or a complete integrated system 4 Technological Options to MOSFET Optimization... Limitations of NanoCMOS Devices 9 9 RPS Electronic Device Architectures for the Nano -CMOS Era “ch01” 2008/7/28 Electronic Device Architectures for the Nano -CMOS Era The power dissipation P of a MOSFET is due to static and dynamic contributions expressed by: P = Pstat + Pdyn (1) Pstat = Vdd × Ioff (2.1) Pdyn = CVdd2 f (2.2) and P is the total power dissipation; Pstat and Pdyn are the static and the dynamic... Limitations of NanoCMOS Devices 19 19 RPS Electronic Device Architectures for the Nano -CMOS Era “ch01” 2008/7/28 20 Electronic Device Architectures for the Nano -CMOS Era Fig 7 (a) Degradation of electron mobility with HfO2 /Si43 ; (b) Leakage current as a function of EOT for various HiK materials reported from Ref 52 a SiON interface could be helpful to reduce the leakage current thanks to the higher bandgap . written permission from the Publisher. Copyright © 2009 by Pan Stanford Publishing Pte. Ltd. ELECTRONIC DEVICE ARCHITECTURES FOR THE NANO -CMOS ERA From Ultimate CMOS Scaling to Beyond CMOS Devices Rhaimie. alt="" Electronic Device Architectures Nano -CMOS Era From Ultimate CMOS Scaling to Beyond CMOS Devices for the V015tp.indd 1 9/1/08 5:18:18 PM This page intentionally left blankThis page intentionally. Devices Rhaimie - Electronic device Archi.pmd 12/29/2008, 2:21 PM1 A-PDF Merger DEMO : Purchase from www.A-PDF.com to remove the watermark RPS Electronic Device Architectures for the Nano -CMOS Era “Preface”