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TR8000 Series Smart In-Circuit Test System User Guide – Analog/Digital Test Theory ver 2.0.0 March 1, 2008 Test Research Inc TR8000 Series – Smart In-Circuit Test System User Guide – Analog/Digital Test Theory v.2.0.0 Copyright © 2008 Test Research Inc All rights reserved This document may be printed or photocopied only by customers or authorized agents of Test Research Inc (TRI) for sole use by their employees working with TRI test systems Any other use of this document must be approved by TRI Specifications and software are subject to change without notice TRI will make all best efforts to let existing customers know of any product upgrade, change or phaseout All trade names and trademarks are the property of their owners For any comments/corrections to this guide, please address them to – sales@tri.com.tw with “TR8000 USER GUIDE” in the Subject field www.tri.com.tw TR8000 User Guide – Analog/Digital Test Theory v.2.0.0 Test Research Inc Contents 1 INTRODUCTION _ 1 2 TEST THEORY OF ANALOG COMPONENTS _ 2 2.1 Open/Short Test Theory 2 2.2 Why Short Groups Are Used 3 2.3 How to Form a Short Group 4 2.3.1 Determine Value of Raw THD 5 2.3.2 Short Test Theory 6 2.3.3 Setup Delay Time for Short Test 7 2.3.4 OPI and SPI Test .9 2.4 Jumper Test Theory 10 2.4.1 Mode (Adjust by OPS Range Measure) 10 2.4.2 Mode (Adjust by Resister Measure) 10 2.4.3 Mode (Adjust by Resistor Measure) 10 2.5 Measurement of Resistor 11 2.5.1 Resistance Test Theory 11 2.5.2 Constant Current Mode .12 2.5.3 Low Constant Current Mode .12 2.5.4 High-Speed Test Mode .13 2.5.5 Guarding Theory for Mode and Mode 13 2.5.6 Guarding Theory for Mode 15 2.5.7 AC Phase Test (Mode 3, Mode 4, Mode 5) 16 2.5.8 4-Wires Resistor Measurement .17 2.6 Measurement of Capacitor 20 2.6.1 Using DC Source Test Method 20 2.6.2 Using AC Source Test Method 21 2.6.3 AC Phase Test Method 21 2.6.4 AC Measure (Modes 0, 1, 2, 3) 23 2.6.5 CX // RX (Modes 5, 6, 7) 24 2.6.6 DC Constant Current Test Modes 4, 25 2.6.7 AC 1K Phase, Wide Range Mode 12 26 2.6.8 AC 100K Phase, Wide Range, Mode 14 26 2.6.9 AC 1M 4-Wire, Mode 15 27 2.6.10 Mode 11, AC 1K SMD 27 2.7 Measurement of Inductor 28 2.7.1 Inductor Test Theory 28 2.7.2 Measure (Modes 0, 1, 2, 3, 9) 30 2.7.3 Lx // Rx (Modes 5, 6, 7) 30 2.8 Measurement of Transistor .32 2.8.1 Measurement of VCE (Modes 3, 4) .33 2.8.2 Measurement of Hfe 35 2.9 Measurement of FET 40 2.9.1 Test Mode 40 2.9.2 Mode 14 41 TR8000 User Guide – Analog/Digital Test Theory v.2.0.0 i Test Research Inc 2.9.3 2.9.4 2.9.5 2.9.6 2.9.7 2.9.8 2.9.9 2.9.10 2.9.11 2.9.12 2.9.13 2.9.14 Mode 15 42 Mode 18 43 Mode 19 44 Mode 20 45 Mode 21 46 Mode 28 47 Mode 29 48 Mode 30 48 Mode 31 48 Qual Source Test Method for FET 49 Mode 26 49 Mode 27 50 2.10 Clamping Diode Test Theory 51 2.10.1 Hardware Setup for Clamping Diode Test .51 2.11 Theory and Application of Agilent TestJet Technology 52 2.12 3-Way Capacitor Polarity Test Skill .54 2.12.1 3-way Capacitor Polarity H/W & S/W Requirements .54 2.12.2 3-way Capacitor Polarity Test Theory 54 2.12.3 Description of 3-way Capacitor Polarity Test Program 57 2.13 Diode Test .59 2.13.1 Diode Test Mode 59 2.13.2 Hardware Configuration for Diode at Modes 0, 1, 24, 25 .59 2.13.3 Hardware Configuration for Type D at Modes 5, .60 2.13.4 Hardware Configuration for Type HV at Modes 5, 61 2.14 SCR Test 63 2.14.1 Test Mode 63 2.14.2 Test Type .63 2.14.3 Test Specification 63 2.14.4 Test Theory 63 2.15 Photo Coupler Test (Photo Transistor Test) 65 2.15.1 Test Mode 65 2.15.2 Test Type .65 2.15.3 Test Theory 65 3 ii DIGITAL COMPONENT TEST THEORY 67 3.1 TTL Logic Test Theory 67 3.1.1 Input and Output Sequence 67 3.1.2 Group Setup Technique 68 3.2 Tree-Chain Test Theory 69 3.2.1 Executing Test Command 69 3.2.2 Tree Chain Test Algorithm .70 3.3 Memory Test Theory .71 3.3.1 Walking One for Address Bus 71 3.3.2 Walking Zero for Address Bus .72 3.3.3 Data bus .73 3.4 Basic Concept of I2C 74 3.5 Basic Concept of P2C .77 TR8000 User Guide – Analog/Digital Test Theory v.2.0.0 Test Research Inc 3.6 Boundary-Scan Test Theory 78 3.6.1 Basic Concept of Boundary-Scan 78 3.6.2 Boundary-Scan Test Theory 78 3.7 Flash Memory Test Theory .84 3.8 Basic Concept of MWIRE Serial EEPROM .85 3.9 ISP Test Theory 85 3.10 Basic Concept of SPI Serial Memory 85 TR8000 User Guide – Analog/Digital Test Theory v.2.0.0 iii Test Research Inc Figures Figure 1: Example – Calculating Resistance 2 Figure 2: Relation Between Voltage & Resistance 3 Figure 3: Short Group Example 4 Figure 4: Short Group Example 4 Figure 5: Short Group Example 5 Figure 6: Short Group Example 5 Figure 7: Hardware Setup for Raw Short Test 6 Figure 8: Hardware Setup for Raw Short Test 6 Figure 9: Phantom Short 7 Figure 10: Test Time Setup for Short Test 8 Figure 11: Jumper Test Example 10 Figure 12: Constant Current Source - Example 11 Figure 13: Constant Voltage Source - Example 11 Figure 14: Constant Current Mode - Example 12 Figure 15: High-Speed Test Mode - Example 13 Figure 16: Mode Circuit Without Guarding 13 Figure 17: Circuit With Guarding 14 Figure 18: Mode Circuit Without Guarding 15 Figure 19: Mode Circuit With Guarding 15 Figure 20: AC Phase Test - Example 16 Figure 21: 4-Wire Test – Mode Example 17 Figure 22: 4-Wire Test – Mode Example 18 Figure 23: 6-Wire Circuit with Guard Nail 19 Figure 24: Circuit for Testing Large Capacitors 20 Figure 25: Relation Between V & T 20 Figure 26: Add Fixed Frequency to Test Object 21 Figure 27: Capacitor Alternate Impedance 21 Figure 28: Voltage/Current Waveform 22 Figure 29: Calculating Length & Phase Angle 22 Figure 30: Modes 0, 1, 2, & 23 Figure 31: Modes 5, & 24 Figure 32: Modes & 25 Figure 33: Mode 12 26 Figure 34: Mode 15 H/W Configuration 27 Figure 35: Apply Fixrd-Frequency Sine Wave to DUT 28 Figure 36: Inductor Alternate Impedance 28 Figure 37: Waveform of Voltage/Current 29 Figure 38: Calculating Alternate Impedance 29 Figure 39: Lx & Rx Measurements 31 Figure 40: Transistor Test Concept 32 iv TR8000 User Guide – Analog/Digital Test Theory v.2.0.0 C.33.44.55.54.78.65.5.43.22.2.4 22.Tai lieu Luan 66.55.77.99 van Luan an.77.99.44.45.67.22.55.77.C.37.99.44.45.67.22.55.77.C.37.99.44.45.67.22.55.77.C.37.99.44.45.67.22.55.77.C.33.44.55.54.78.655.43.22.2.4.55.22 Do an.Tai lieu Luan van Luan an Do an.Tai lieu Luan van Luan an Do an C.33.44.55.54.78.65.5.43.22.2.4 22.Tai lieu Luan 66.55.77.99 van Luan an.77.99.44.45.67.22.55.77.C.37.99.44.45.67.22.55.77.C.37.99.44.45.67.22.55.77.C.37.99.44.45.67.22.55.77.C.33.44.55.54.78.655.43.22.2.4.55.22 Do an.Tai lieu Luan van Luan an Do an.Tai lieu Luan van Luan an Do an Test Research Inc Figure 41: H/W Configuration for Transistor Mode 33 Figure 42: H/W Configuration for Transistor Mode 34 Figure 43: H/W Configuration for NPN Transistor Mode12 36 Figure 44: PNP-HFE Transistor Test Step, Mode 12 37 Figure 45: PNP-HFE Transistor Hardware Configuration, Mode 13 37 Figure 46: PNP-HFE Transistor Test Step, Mode 13 38 Figure 47: PNP-HFE Transistor Test Step, Mode 34 38 Figure 48: PNP-HFE Transistor Test Step, Mode 35 39 Figure 49: FET Hardware Configuration, Mode 14 41 Figure 50: FET Test Step, Mode 14 41 Figure 51: FET Hardware Configuration, Mode 15 42 Figure 52: FET Test Step, Mode 15 42 Figure 53: FET Hardware Configuration, Mode 18 43 Figure 54: FET Test Step, Mode 18 43 Figure 55: FET Hardware Configuration, Mode 19 44 Figure 56: FET Test Step, Mode 19 44 Figure 57: FET Hardware Configuration, Mode 20 45 Figure 58: FET Test Step, Mode 20 45 Figure 59: FET Hardware Configuration, Mode 21 46 Figure 60: FET Test Step, Mode 21 46 Figure 61: FET Hardware Configuration, Mode 28 47 Figure 62: FET Test Step, Mode 28 47 Figure 63: FET Hardware Configuration, Mode 29 48 Figure 64: FET Test Step, Mode 29 48 Figure 65: FET Hardware Configuration, Mode 26 49 Figure 66: FET Test Step, Mode 26 49 Figure 67: FET Hardware Configuration, Mode 27 50 Figure 68: FET Test Step, Mode 27 50 Figure 69: IC with Clamping Diode 51 Figure 70: Clamping Diode Hardware Configuration 51 Figure 71: Internal Wire Connections of an IC 52 Figure 72: Test Structure & Schematic for TestJet Test 52 Figure 73: Equivalent Circuit of Vertical-Type Electrolytic Polarity Capacitor 54 Figure 74: Normal Capacitance 55 Figure 75: Reverse Capacitance (Vo2
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