Thesis presents a hardware architecture to implement the HOGSVM algorithm on a SystemonChip. To accomplish this goal, we packaged the HOGSVM IP with a HOGSVM computation block and a RAM memory block that stores the pixel values of the images. In addition, the AXI interface is used to connect the HOGSVM IP core and other components in the SoC system. After synthesizing the hardware and simulating the design, the results obtained met the desired requirements.The HOGSVM IP operates at a frequency of 40 MHz and a frame rate of 20 fps, accurately performing the generation of results on the location of people in the images with HD resolution. Additionally, the design also has low hardware resource utilization of FPGA at 40,547 LUTs and 20,298 registers. Moreover, the design has demonstrated excellent performance in terms of power consumption and costeffectiveness, which are crucial factors in the development of IoT systems. With the proposed hardware architecture, the HOGSVM algorithm can be implemented efficiently on an SoC system, enabling realtime processing of images and improving the overall system performance. In conclusion, the proposed hardware architecture on FPGA for the implementation HOGSVM algorithm is a viable solution for implementing person recognition in lowpower and lowcost IoT systems. The design has shown promising results in terms of accuracy, speed, and hardware resource utilization, making it a practical solution for various IoT applications.
VIETNAM NATIONAL UNIVERSITY UNIVERSITY OF ENGINEERING AND TECHNOLOGY Nguyen The Anh FPGA-BASED IMPLEMENTATION OF THE HOG-SVM ALGORITHM BACHELOR’S FINAL THESIS Major: Electronics and Communications Engineering Technology HA NOI - 2023 VIETNAM NATIONAL UNIVERSITY UNIVERSITY OF ENGINEERING AND TECHNOLOGY Nguyen The Anh FPGA-BASED IMPLEMENTATION OF THE HOG-SVM ALGORITHM BACHELOR’S FINAL THESIS Major: Electronics and Communications Engineering Technology Supervisor: Dr Bui Duy Hieu Co-supervisor: Dr Tran Thi Thuy Quynh HA NOI - 2023 AUTHORSHIP I hereby declare that the FPGA-based implementation of the HOG-SVM algorithm is of my own and has not been previously submitted for a degree or diploma at this any other higher education previously published or written by another person except where due reference or acknowledgment is made I understand the importance of responsible research conduct and the impact that my work may have on society, and I pledge to my utmost to ensure that my research makes a positive contribution to the world Ha Noi, 05/ 05/ 2023 Student Nguyen The Anh i ACKNOWEDGEMENT First of all, I would like to express my deepest gratitude to the teachers of the Faculty of Electronic and Telecommunications at the University of Engineering and Technology, along with my supervisors Dr Bui Duy Hieu and my co-supervisor Dr Tran Thi Thuy Quynh for their invaluable guidance, continuous support, and encouragement throughout my thesis Without their insightful feedback and constructive criticism, this work would not have been possible I am also grateful to Information Technology Institute (ITI-VNU), who have provided me with valuable suggestions and feedback during my research Last but not least, I would like to thank my family for their unconditional love, patience, and support throughout my academic journey Ha Noi, 05/ 05/ 2023 Student Nguyen The Anh ii ABSTRACT The problem of human detection is an important task in the field of computer vision Currently, there are many methods and algorithms to solve this problem, such as using CNN, RNN models, etc However, CNNs and RNNs need hardware resources and large memory space to calculate complex computations which are not suitable for lowpower and low-cost IoT systems In contrast, the HOG-SVM algorithm is the most appropriate choice because of its higher performance and faster computation speed Based on this approach, this thesis presents a hardware architecture to implement the HOG-SVM algorithm on a System-on-Chip To accomplish this goal, we packaged the HOG-SVM IP with a HOG-SVM computation block and a RAM memory block that stores the pixel values of the images In addition, the AXI interface is used to connect the HOG-SVM IP core and other components in the SoC system After synthesizing the hardware and simulating the design, the results obtained met the desired requirements The HOG-SVM IP operates at a frequency of 40 MHz and a frame rate of 20 fps, accurately performing the generation of results on the location of people in the images with HD resolution Additionally, the design also has low hardware resource utilization of FPGA at 40,547 LUTs and 20,298 registers Moreover, the design has demonstrated excellent performance in terms of power consumption and cost-effectiveness, which are crucial factors in the development of IoT systems With the proposed hardware architecture, the HOG-SVM algorithm can be implemented efficiently on an SoC system, enabling real-time processing of images and improving the overall system performance In conclusion, the proposed hardware architecture on FPGA for the implementation HOGSVM algorithm is a viable solution for implementing person recognition in low-power and low-cost IoT systems The design has shown promising results in terms of accuracy, speed, and hardware resource utilization, making it a practical solution for various IoT applications Key words: Human detection, Histogram of oriented gradient, SVM, FPGA, IP core, SoC iii Contents AUTHORSHIP i ACKNOWEDGEMENT ii ABSTRACT iii List of Figures v List of Tables viii List of Acronyms ix Introduction Chapter An overview of Human detection and HOG-SVM algorithm 1.1 Human detection methods 1.2 HOG-SVM algorithm 1.2.1 HOG-Histogram of oriented gradient 1.2.2 SVM-Support vector machine 1.3 Related work 12 1.4 Conclusion 15 Chapter Proposed hardware architecture on FPGA 16 2.1 Reuse adaptive hardware architecture 16 2.2 Proposed method 17 iv 2.3 2.4 HOG-SVM IP based on adaptive hardware architecture 18 2.3.1 HOG-SVM IP architecture design 18 2.3.2 HOG-SVM IP memory map 21 2.3.3 HOG-SVM IP control finite state machine 23 Conclusion 25 Chapter 3.1 Implementation and Verification 26 Simulation and Validation 27 3.1.1 FPGA implementation flow 27 3.1.2 Validation method 31 3.2 Hardware implementation results 34 3.3 Conclusion 36 Conclusion 38 Bibliography 42 v List of Figures 1.1 Overview of the HOG-SVM algorithm 1.2 Mapping magnitudes of the gradient with bins 1.3 Hyperplanes in 2D and 3D space 11 1.4 Hyperplanes representation with maximum margin 11 2.1 System hardware architecture 18 2.2 HOG-SVM IP architecture 19 2.3 HOG-SVM computation block hardware architecture [1] 20 2.4 Control finite state machine 24 3.1 Integration flow 26 3.2 HOG-SVM IP package steps 27 3.3 Code file for three main components of the HOG-SVM IP 27 3.4 Synthesis successfully 28 3.5 Package successfully 28 3.6 Validation step 29 3.7 Simulation step 29 3.8 Image under test 30 3.9 Simulation result of test image in Fig.3.8 30 3.10 Intergrate HOG-SVM IP into Zynq UltraScale + MPSoC ZCU106 core vi 31 3.11 Validation process 32 3.12 Simulation process 32 3.13 HOG-SVM IP and VIP module connection in Vivado 33 vii List of Tables 2.1 Memory map of HOG-SVM IP 21 3.1 System synthesis result 35 3.2 HOG-SVM IP synthesis result 36 3.3 Comparasion with others works 37 viii After the VHDL code for the HOG-SVM block, RAM block, and AXI4 interface have been written, checked for syntax errors, and debugged, we move on to synthesizing the hardware architecture using Vivado The synthesis process takes the VHDL code and generates a gate-level netlist that describes the hardware architecture This netlist is optimized for the target FPGA device and can be used to program the device to implement the HOG-SVM IP Once the synthesis process is complete, Vivado generates a synthesis report file that provides information about the design’s performance, resource utilization, and timing constraints (Fig.3.4) We review this report to ensure that there are no critical errors and that the design meets our performance requirements If the synthesis report shows no errors, we can proceed to package the HOG-SVM IP After successful this step, we can package the HOG-SVM IP (Fig.3.5) Figure 3.4: Synthesis successfully Figure 3.5: Package successfully After packaging HOG-SVM IP successfully, the next step is to validate the IP using Vivado and QuestaSim This step is described in Fig.3.6 Simulation allows us to validate that the IP operates as expected and produces the desired results We create a project in Vivado and connect HOG-SVM IP and VIP (Verification IP) module to validate the design (Fig.3.7) We can input sample images to the IP and observe the output to ensure that human detection is performed accurately and efficiently The testbench for simulation and validation is written in SystemVerilog languages During simulation, we can input sample images to the IP and observe the output to ensure that human detection is performed accurately and efficiently The IP operates with the expected results during the simulation 28 Error Package Connect HOG-SVM IP with VIP module Evaluate report Simulation success Implementation Figure 3.6: Validation step VIP module and HOG-SVM IP conection Testbenches file Figure 3.7: Simulation step After the simulation was carried out, the HOG-SVM IP functioned as expected, detecting humans in the test images For example, an image with a size of 98x162 pixels, we need 25 detection windows to scan full of the image The simulation result is described in Fig.3.9 There are 18 detection windows that produce results similar to the results obtained from the HOG-SVM algorithm on MATLAB , while detection windows not have similar results The diffrence in results occurs because when executing the algorithm on hardware, the calculations are approximated, whereas on MATLAB, the calculations are performed accurately Additionally, when executing on hardware, our system can detect person in the image However, the number of detection windows that detect a person is different from the results on MATLAB Next, we proceeded to the next step of implementing and integrating the IP into the Zynq ZUC106 core As shown in Fig.3.10, the HOG-SVM IP block is integrated into the processing system (PS) of the Zynq UltraScale + MPSoC ZCU106 development kit The PS consists of a processing unit (CPU) and various other peripherals, such as memory 29 Figure 3.8: Image under test Figure 3.9: Simulation result of test image in Fig.3.8 30 controllers and input/output (I/O) interfaces The HOG-SVM IP block communicates with the PS through the AXI bus interface designed in the previous chapter, which allows for efficient data transfer and control The PS is responsible for configuring the FPGA and programming the HOG-SVM IP block To configure the FPGA and program the HOG-SVM IP block, the PS loads the bitstream file generated from the design into the FPGA’s configuration memory The bitstream file contains the configuration settings for the FPGA and the HOG-SVM IP block, which determine how the IP block will operate Once programmed, the FPGA runs the HOG-SVM IP block as configured, allowing for efficient and highly parallelized image processing The integration between the HOGSVM IP block and the Zynq ZCU106 core enables high-performance image processing capabilities for a wide range of applications Figure 3.10: Intergrate HOG-SVM IP into Zynq UltraScale + MPSoC ZCU106 core Overall, the process of our hardware architecture implementation for human detection involves several steps, including VHDL code development, synthesis, packaging, simulation, and implementation Specifically, in the next section, we present the results on the size and resource utilization of the FPGA after the design is implemented 3.1.2 Validation method The human detection algorithm hardware block and the AXI interface are designed in VHDL, a powerful hardware description language for describing large and complex numerical systems Therefore, to verify the results and hardware feasibility, this thesis will use the Questasim simulator and Xilinx Vivado The validation process is described in Fig.3.11 To check if the hardware system 31 ERROR Design START Grayscale images and SVM weights (Matlab) Create project to connect HOG-SVM IP with VIP module (Vivado) Simulation (Questasim) Evaluate result SUCCESS END Figure 3.11: Validation process is working correctly, we will check through the simulation results First, we will connect the HOG-SVM IP with the VIP module Using Verification IP (VIP) module for simulating the operation of the HOG-SVM IP has many advantages compared to using a CPU for simulation Firstly, VIP provides an independent testing solution that is not dependent on any specific hardware and software system This ensures the correctness and reliability of the designed system before implementation on real-time hardware Secondly, using VIP saves time and cost because it allows simulation in virtual environments without the need for actual hardware devices This helps designers evaluate the performance and features of the system before building actual hardware while reducing development costs and time Finally, VIP provides the ability to automatically and accurately check and analyze simulation results This helps designers quickly identify and fix errors in the system development process In summary, using Verification IP is an effective and time-saving solution for simulating IP operations before implementation on actual hardware Matlab Image (.png, jpg, ) Questasim pixel data (.txt ) Pixel data Start VIP SVM weights SVM weights HOG-SVM IP Result SVM data (.txt) AXI4 Interface Person or no person End Figure 3.12: Simulation process After connecting the HOG-SVM IP with the VIP module, the design will be simu32 lated through Questasim software Observing the results, we will verify the correctness of the HOG-SVM IP According to Fig.3.12, images saved in file formats such as PNG, JPG, etc will be converted from pixel data to text file format This pixel data will be read by the VIP module and loaded into the RAM storage of the HOG-SVM IP core In addition, the SVM training weights data will be computed in MATLAB and saved in text file format The VIP module will also read and directly load these weights into the HOG-SVM IP core Next, the VIP module will send an activation signal to the HOGSVM IP to start computing the data set stored in RAM The computed results will be verified using a test bench in the Questasim simulation program Figure 3.13: HOG-SVM IP and VIP module connection in Vivado The test system will have two main components: Vivado’s Verification IP module and HOG-SVM IP The connection between HOG-SVM IP and VIP module is described in Fig.3.13 The Vivado VIP module is a collection of pre-built test benches and verification IPs that help to speed up the process of verifying digital designs This VIP module will act as a CPU in practice It includes verification IP for various interfaces, such as PCIe, USB, and Ethernet, and provides a standardized interface for verifying these protocols The simulation is performed on Questasim software with test benches written in SystemVerilog language SystemVerilog is a hardware description and verification language that combines elements of Verilog HDL with features from the C programming language It provides constructs for specifying design structures, specifying constraints, and creating test benches to verify the functionality of digital circuits The use of test benches written in SystemVerilog enables engineers to create comprehensive test suites that can detect bugs and design flaws in the hardware design These test scripts can be 33 used to simulate a wide range of scenarios and edge cases, ensuring that the design is robust and reliable Overall, the combination of Vivado’s Verification IP module and the HOG-SVM IP provides a powerful toolset for verifying the functionality and robustness of digital designs that incorporate object detection and tracking algorithms This system can be used in various applications, such as autonomous vehicles and robotics, where the accurate detection of objects is critical for ensuring safe and reliable operation 3.2 Hardware implementation results The synthesis process was performed on the Xilinx Zynq UltraScale+ MPSoC ZCU106 FPGA development kit This kit provides a powerful platform for SoC development, with an FPGA chip that combines programmable logic and processing elements on a single device The ZCU106 kit includes a variety of interfaces and peripherals, such as Ethernet, USB, HDMI, and DDR4 memory, which make it suitable for a wide range of IoT and embedded applications Therefore, we chose to integrate the HOG-SVM IP core in this thesis After the synthesis process, the hardware implementation results of the HOG-SVM IP are described in Table 3.1 The total number of LUTs used is 40,547, of which the HOG-SVM block requires 39,624 LUTs, accounting for the majority of hardware resources at 97(%) In addition, the RAM block with 33 LUTs accounts for 0.08(%) and the AXI4 interface accounts for 2.2(%) These results provide insight into the resource utilization of the HOG-SVM IP and can be used to optimize the design for more efficient resource utilization In addition, after executing the hardware system designed in 2, combining the optimized methods of hardware cost, the hardware of the entire SoC system used 40,547 LUTs, accounting for 17.6(%), 20,298 registers accounting for 4.4(%), and 12 BRAM blocks accounting for 3.85(%) of the available resources on the FPGA This result is described in Table 3.2 In addition, we also compare the results obtained from our HOG-SVM IP with those from other research works This comparison allows us to evaluate the performance 34 Table 3.1: System synthesis result Total Logic LUTs LUTs 40547 40547 20298 10 HOG-SVM block 39624 39624 19436 RAM block 33 33 0 AXI4 interface 891 891 862 0 Instance HOG-SVM IP and AXI4 interface FFs RAMB36 RAMB18 URAM and effectiveness of our IP design compared to existing state-of-the-art human detection methods This comparison is described in Table 3.3 The paper [13] proposed a hardware accelerator for HOG feature extraction that can process an HDTV frame at a speed of 60 frames per second and a frequency of 125 MHz This hardware accelerator is designed to be followed by multiple SVM classifiers to achieve higher throughput The HOG descriptor is generated within less than millisecond for 256x256 image and 16.6 ms for HDTV stream In this work, the authors also used a parallel hardware architecture that allows multiple access to memory at different computation stages, thereby reducing hardware utilization In our work, the HOG-SVM block uses a data reuse strategy to minimize hardware cost and increase computation speed, suitable for parallel execution of the Normalization and Classification stages Therefore, our hardware design uses more registers, it does not require DSPs like the architecture in [13] because our images are preprocessed to grayscale images Besides, the work in [16] also proposes a HOG-based hardware architecture system that can process the image with a resolution of 800x600 pixels on FPGA for the pedestrian detector The advantage of this work is that it provides a real-time and multi-scale system on an FPGA platform The proposed system can detect pedestrians at multiple scales with high accuracy (decrease the detection performance by approximately 3% at 10−4 FPPW) The disadvantage of the work is that it only demonstrated on a small dataset 20 SVGA frames per second at the frequency of 50 MHz On the contrary, our design only runs at a frequency of 40MHz, but it achieves a speed of 20 fps with HD resolution and uses fewer hardware resources (40547 LUTs and 20298 FFs) 35 Table 3.2: HOG-SVM IP synthesis result Resources on chip Used Available Utilization(%) Configurable Logic Block 67012 — — LUT as Logic 40547 230400 17.6 CARRY8 2257 7.84 Register 20298 460800 4.4 BUFG 64 1.56 F7/F8 Muxes 1061 230400 0.46 Signals 28800 60941 — — Block RAM 12 312 3.85 URAM 96 1.04 I/O 94 360 26.11 Finally, the work in [21] presents a hardware-software implementation of the HOGSVM algorithm in an SoC FPGA device This system is verified for 4K/UHD resolution with a speed of 60 fps and a frequency of 150 MHz Moreover, the design can be able to obtain real-time processing with estimated energy consumption of approximately 9.579 W These are far better results than our design These results in [21] will be the target for us to improve our designs in the future 3.3 Conclusion In conclusion, this chapter has presented the step to validate the proposed hard- ware architecture in chapter for the HOG-SVM algorithm on FPGA We packaged a HOG-SVM IP and wrote a testbench for HOG-SVM IP simulation, which allowed us to simulate the system’s behavior and performance using SystemVerilog HDL The testbench included a set of preprocessed input images and trained SVM classifiers Next, we synthesized our design and implemented the hardware architecture on the Xilinx UltraScale+ MPSoC ZCU106 FPGA development kit using the Vivado design suite Overall, the synthesis process and validation process was successful and we obtained the expected hardware synthesis results The obtained results have been compared with 36 Table 3.3: Comparasion with others works FPGA BRAMs DSP Fps Freq LUTs FFs 7226 12462 12 26 60 125 1920x1080 47175 25158 1222 491 20 50 800x600 38.5 818 60 15000 3840x2160 12 20 40 1920x1080 (MHz) Resolution AMD [13] Xilinx Zynq Altera [16] Cyclone IV AMD [21] Xilinx 126050 270817 ZCU104 Our work AMD Xilinx 40547 20298 ZCU106 some other works Although there are still some limitations in our design, the work in this thesis will continue to be researched and improved in the future 37 Conclusion Deep learning-based methods and Hand feature-based methods are two different approaches used in computer vision for object recognition and image classification However, Deep learning algorithms such as CNNs, RNNs, etc have complex computational requirements, require a lot of hardware resources, and have high energy consumption, which is not suitable in the context of edge computing Moreover, in the Hand features such as Haar Cascade, LBP, etc are affected by the brightness of the image In contrast, the HOG feature can handle more complex datasets, improving accuracy Therefore, HOG-SVM is the chosen algorithm in the thesis to solve the problem of human detection With fast computation speed, high performance, and lower energy consumption than CNNs and RNNs, HOG-SVM is suitable for IoT and embedded systems With the goal of building an SoC system that executes the HOG-SVM algorithm, we focus on optimizing and packaging a hardware design of the HOG-SVM algorithm into an IP core Next, we propose a hardware architecture to integrate the HOG-SVM IP into the SoCs Our hardware architecture consists of a block for computing the HOGSVM algorithm, a block of RAM to store data of the image’s pixels, and an AXI4 interface for communication between the IP core and other blocks in the system The HOG-SVM computation block is reused adaptive hardware architecture in [1], which together provides high accuracy in human detection tasks In addition, the RAM block is used to store image data, which can be accessed and processed by the HOG-SVM computation block Finally, the AXI interface, which is a widely-used communication standard in SoC design, is designed to transfer data and send control signals between different blocks in the system Besides, after the synthesis and simulation process, we obtained some promising 38 results The HOG-SVM IP core was integrated into the SoC system and could run at a frequency of 40 MHz, with HD resolution images, at a speed of 20 fps In addition, the design was synthesized on an FPGA and showed low hardware costs with 40,547 LUTs, and 20,298 registers (without using DSP), which met the stated objectives of the thesis Further improvements can be made to the HOG-SVM IP core to enhance its performance and flexibility For instance, we can investigate methods for optimizing the processing pipeline and reducing memory access times In the near future, we will continue to improve the design so that the HOG-SVM IP core can adapt to various resolutions and process data faster by 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