IEC 61691 5 ed1 0 INTERNATIONAL STANDARD IEC 61691 5 First edition 2004 10 IEEE 1076 4™ Behavioural languages – Part 5 VITAL ASIC (application specific integrated circuit) modeling specification Refer[.]
INTERNATIONAL STANDARD IEC 61691-5 First edition 2004-10 IEEE 1076.4™ Part 5: VITAL ASIC (application specific integrated circuit) modeling specification Reference number IEC 61691-5(E):2004 IEEE Std 1076.4(E):2000 LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU Behavioural languages – Publication numbering As from January 1997 all IEC publications are issued with a designation in the 60000 series For example, IEC 34-1 is now referred to as IEC 60034-1 Consolidated editions Further information on IEC publications The technical content of IEC publications is kept under constant review by the IEC, thus ensuring that the content reflects current technology Information relating to this publication, including its validity, is available in the IEC Catalogue of publications (see below) in addition to new editions, amendments and corrigenda Information on the subjects under consideration and work in progress undertaken by the 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THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU The IEC is now publishing consolidated versions of its publications For example, edition numbers 1.0, 1.1 and 1.2 refer, respectively, to the base publication, the base publication incorporating amendment and the base publication incorporating amendments and INTERNATIONAL STANDARD IEC 61691-5 First edition 2004-10 IEEE 1076.4™ Part 5: VITAL ASIC (application specific integrated circuit) modeling specification Copyright © IEEE 2004 ⎯ All rights reserved IEEE is a registered trademark in the U.S Patent & Trademark Office, owned by the Institute of Electrical and Electronics Engineers, Inc No part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher International Electrotechnical Commission, 3, rue de Varembé, PO Box 131, CH-1211 Geneva 20, Switzerland Telephone: +41 22 919 02 11 Telefax: +41 22 919 03 00 E-mail: inmail@iec.ch Web: www.iec.ch The Institute of Electrical and Electronics Engineers, Inc, Park Avenue, New York, NY 10016-5997, USA Telephone: +1 732 562 3800 Telefax: +1 732 562 1571 E-mail: stds-info@ieee.org Web: www.standards.ieee.org Com mission Electrotechnique Internationale International Electrotechnical Com m ission Международная Электротехническая Комиссия LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU Behavioural languages – CONTENTS IEC 61691-5:2004(E) IEEE 1076.4-2000(E) FOREWORD IEEE Introduction Overview 10 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Scope 10 Purpose 10 Intent of this standard 10 Structure and terminology of this standard .10 Syntactic description 11 Semantic description 12 Front matter, examples, figures, notes, and annexes 12 References 12 Basic elements of the VITAL ASIC modeling specification 13 3.1 VITAL modeling levels and compliance 13 3.2 VITAL standard packages 14 3.3 VITAL specification for timing data insertion 14 The Level specification 16 4.1 4.2 4.3 4.4 The VITAL_Level0 attribute 16 General usage rules .16 The Level entity interface 17 The Level architecture body 26 Backannotation 28 5.1 Backannotation methods 28 5.2 The VITAL SDF map 29 The Level specification 44 6.1 6.2 6.3 6.4 The VITAL_Level1 attribute 44 The Level architecture body 44 The Level architecture declarative part 45 The Level architecture statement part 45 Predefined primitives and tables 55 7.1 VITAL logic primitives 55 7.2 VitalResolve 57 7.3 VITAL table primitives 57 Timing constraints 63 8.1 Timing check procedures 63 8.2 Modeling negative timing constraints 68 Delay selection 79 9.1 VITAL delay types and subtypes 79 Published by IEC under licence from IEEE © 2004 IEEE All rights reserved Copyright © 2001 IEEE All rights reserved LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU IEC 61691-5:2004(E) IEEE 1076.4-2000(E) 9.2 Transition dependent delay selection 80 9.3 Glitch handling 80 9.4 Path delay procedures 81 9.5 Delay selection in VITAL primitives 83 9.6 VitalExtendToFillDelay 84 10 The Level Memory specification 85 10.1 The VITAL Level Memory attribute 85 10.2 The VITAL Level Memory architecture body 85 10.3 The VITAL Level Memory architecture declarative part 86 11 VITAL Memory function specification 96 11.1 VITAL memory construction 96 11.2 VITAL memory table specification 99 11.3 VitalDeclareMemory .108 11.4 VitalMemoryTable 110 11.5 VitalMemoryCrossPorts 112 11.6 VitalMemoryViolation 114 12 VITAL memory timing specification 117 12.1 VITAL memory timing types 117 12.2 Memory Output Retain timing behavior 118 12.3 VITAL Memory output retain timing specification 119 12.4 Transition dependent delay selection 119 12.5 VITAL memory path delay procedures 120 12.6 VITAL memory timing check procedures 125 13 The VITAL standard packages 130 13.1 VITAL_Timing package declaration 130 13.2 VITAL_Timing package body 145 13.3 VITAL_Primitives package declaration 172 13.4 VITAL_Primitives package body 241 13.5 VITAL_Memory package declaration 311 13.6 VITAL_Memory package body 332 Annex A (informative) Syntax summary 421 Annex B (informative) Glossary .427 Annex C (informative) Bibliography 429 Annex D (informative) List of Participants 430 Copyright © 2001 IEEE All rights reserved Published by IEC under licence from IEEE © 2004 IEEE All rights reserved LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU 10.4 The VITAL Level Memory architecture statement part 86 IEC 61691-5:2004(E) IEEE 1076.4-2000(E) INTERNATIONAL ELECTROTECHNICAL COMMISSION _ BEHAVIOURAL LANGUAGES – Part 5: VITAL ASIC (application specific integrated circuit) modeling specification FOREWORD 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested IEC National Committees 3) IEC Publications have the form of recommendations for international use and are accepted by IEC National Committees in that sense While all reasonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any misinterpretation by any end user 4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications transparently to the maximum extent possible in their national and regional publications Any divergence between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter 5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any equipment declared to be in conformity with an IEC Publication 6) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights IEC shall not be held responsible for identifying any or all such patent rights International Standard IEC/IEEE 61691-5 has been processed through IEC technical committee 93: Design automation The text of this standard is based on the following documents: IEEE Std FDIS Report on voting 1076.4 (2000) 93/194/FDIS 93/199/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table This publication has been drafted in accordance with the ISO/IEC Directives The committee has decided that the contents of this publication will remain unchanged until 2005 Published by IEC under licence from IEEE © 2004 IEEE All rights reserved LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees) The object of IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields To this end and in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)”) Their preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with may participate in this preparatory work International, governmental and non-governmental organizations liaising with the IEC also participate in this preparation IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions determined by agreement between the two organizations IEC 61691-5:2004(E) IEEE 1076.4-2000(E) IEC 61691 consists of the following parts, under the general title Behavioural languages: IEC/IEEE 61691-1-1, Part 1: VHDL language reference manual IEC 61691-2, Part 2: VHDL multilogic system for model interoperability IEC 61691-3-1, Part 3-1: Analog description in VHDL (under consideration) IEC 61691-3-2, Part 3-2: Mathematical operation in VHDL IEC 61691-3-3, Part 3-3: Synthesis in VHDL IEC 61691-3-4, Part 3-4: Timing expressions in VHDL (under consideration) IEC 61691-3-5, Part 3-5: Library utilities in VHDL (under consideration) IEC/IEEE 61691-4, Part 4: Verilog® hardware description language Published by IEC under licence from IEEE © 2004 IEEE All rights reserved LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU IEC/IEEE 61691-5, Part 5: VITAL ASIC (application specific integrated circuit) modeling specification IEC 61691-5:2004(E) IEEE 1076.4-2000(E) IEC/IEEE Dual Logo International Standards This Dual Logo International Standard is the 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required by an IEEE standard or for conducting inquiries into the legal validity or scope of those patents that are brought to its attention Published by IEC under licence from IEEE © 2004 IEEE All rights reserved LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU The IEC and IEEE not warrant or represent the accuracy or content of the material contained herein, and expressly disclaim any express or implied warranty, including any implied warranty of merchantability or fitness for a specific purpose, or that the use of the material contained herein is free from patent infringement IEC/IEEE Dual Logo International Standards documents are supplied “AS IS” IEC 61691-5:2004(E) IEEE 1076.4-2000(E) IEEE Standard for VITAL ASIC (Application Specific Integrated Sponsor Design Automation Standards Committee of the IEEE Computer Society Approved 21 September 2000 IEEE-SA Standards Board Abstract: The VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined in this standard This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL Keywords: ASIC, computer, computer languages, constraints, delay calculation, HDL, modeling, SDF, timing, Verilog, VHDL Published by IEC under licence from IEEE © 2004 IEEE All rights reserved LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU Circuit) Modeling Specification IEC 61691-5:2004(E) IEEE 1076.4-2000(E) IEEE Introduction The objectives of the VITAL (VHDL Initiative Towards ASIC Libraries) initiative can be summed up in one sentence: Accelerate the development of sign-off quality ASIC macrocell simulation libraries written in VHDL by leveraging existing methodologies of model development The VITAL ASIC modeling specification is a revision of the IEEE 1076.4-1995, IEEE Standard for VITAL ASIC Modeling Specification Several new modeling enhancements have been added to the standard and several usability issues which have been raised with the 1995 standard have been addressed The new enhancements and usability improvements addressed include: — — — Standardized ASIC memory models Support of IEEE VHDL93 and SDF 1497 standards Multisource interconnect timing simulation SKEW constraint timing checks Timing constraint checks feature enhancements Additional generics to control ‘X’ generation and message reporting for glitches and timing constraints Negative constraint calculation enhancement for vector signals to support memory models Fast delay path disable Negative glitch preemption These new features will improve the functional, timing accuracy significantly and aid performance of gate level VHDL simulations The major enhancement is the definition of a ASIC memory modeling standard With the addition of memory model package VITAL_Memory, a standard is defined which allow memory models to be coded in VHDL more efficiently The standard VITAL memory model package provides a method to represent memories, procedures and functions to perform various operations and the definition of a modeling style that promotes consistency, maintainability and tool optimization This standard does not define modeling behavior of specific memories The scope of the memory model standard is currently restricted to ASIC memory modeling requirement for static RAMs and ROMs The VITAL memory modeling enhancements are specified in Clause 10 through Clause 12 The VITAL standard memory package is found in Clause 13 The memory model standard is derived from contributed work from the LSI Logic VHDL behavioral model and Mentor Graphics Memory Table Model (MTM) techniques The generous support of VHDL International provided the needed funding to take these two contributed works and convert them into the memory specification and package code by the IEEE 1076.4 TAG (Technical Action Group) with significant contribution coming from leading EDA services company GDA Technologies The technical direction of the working group as well as the day to day activities of issue analysis and drafting of proposed wordings for the specification are the responsibility of the IEEE 1076.4 TAG This group consists of Ekambaram Balaji, Prakash Bare, Nitin Chowdhary, Jose De Castro, Martin Gregory, Rama Kowsalya, B Sudheendra Phani Kumar, William Yam, David Lin, Ashwini Mulgaonkar, Ajayharsh P Varikat, and Steve Wadsworth and is chaired by Dennis B Brophy Without the dedication and hard work of this group it would not have been possible to complete this work The VITAL effort germinated from ideas generated at the VHDL International Users’ Forum held in Scottsdale, Arizona in May 1992 Further discussions brought people to the conclusion that the biggest impediment to VHDL design was the lack of ASIC libraries; and that the biggest impediment to ASIC library Copyright © 2001 IEEE All rights reserved Published by IEC under licence from IEEE © 2004 IEEE All rights reserved LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU — — — — — — IEC 61691-5:2004(E) IEEE IEEE 1076.4-2000(E) 420 INTEGRATED CIRCUIT) MODELING SPECIFICATION MemoryTable DataAction CallerName PortName HeaderMsg MsgOn ); END IF; => => => => => => ViolationTable DataAction MsgVMV PortName HeaderMsg MsgOn Std 1076.4-2000 , , , , , LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU IF (PortType = WRITE OR PortType = RDNWR) THEN HandleMemoryAction( MemoryData => MemoryData , PortFlag => PortFlagTmp , CorruptMask => MemCorruptMask , DataInBus => DataInBus , Address => AddressValue , HighBit => HighBit , LowBit => LowBit , MemoryTable => ViolationTable , MemoryAction => MemoryAction , CallerName => MsgVMV , PortName => PortName , HeaderMsg => HeaderMsg , MsgOn => MsgOn ); END IF; Check if we need to turn off PF.OutputDisable IF (DataAction /= ‘S’) THEN PortFlagTmp.OutputDisable := FALSE; Set the output PortFlag(0) value Note that all bits of PortFlag get PortFlagTmp FOR i IN PortFlag’RANGE LOOP PortFlag(i) := PortFlagTmp; END LOOP; END IF; Set the candidate zero delay return value DataOutBus := DataOutTmp; END; PROCEDURE VitalMemoryViolation ( VARIABLE DataOutBus : VARIABLE MemoryData : VARIABLE PortFlag : CONSTANT DataInBus : CONSTANT AddressValue : CONSTANT ViolationFlags : CONSTANT ViolationTable : CONSTANT PortType : CONSTANT PortName : CONSTANT HeaderMsg : CONSTANT MsgOn : CONSTANT MsgSeverity : ) IS VARIABLE VFlagArrayTmp INOUT std_logic_vector; INOUT VitalMemoryDataType; INOUT VitalPortFlagVectorType; IN std_logic_vector; IN VitalAddressValueType; IN std_logic_vector; IN VitalMemoryTableType; IN VitalPortType; IN STRING := ““; IN STRING := ““; IN BOOLEAN := TRUE; IN SEVERITY_LEVEL := WARNING : X01ArrayT (0 TO 0); BEGIN VitalMemoryViolation ( DataOutBus MemoryData PortFlag DataInBus AddressValue ViolationFlags ViolationFlagsArray ViolationSizesArray ViolationTable PortType PortName HeaderMsg MsgOn MsgSeverity ); => => => => => => => => => => => => => => DataOutBus MemoryData PortFlag DataInBus AddressValue ViolationFlags VFlagArrayTmp ( => ) ViolationTable PortType PortName HeaderMsg MsgOn MsgSeverity , , , , , , , , , , , , , END; END Vital_Memory ; Copyright © IEC 2001 IEEE All from rights reserved Published by under licence IEEE © 2004 IEEE All rights reserved 411 IEC 61691-5:2004(E) IEEE IEEE 1076.4-2000(E) Std 1076.4-2000 421 IEEE STANDARD FOR VITAL ASIC (APPLICATION SPECIFIC Annex A (informative) Syntax summary VITAL_design_file ::= VITAL_design_unit { VITAL_design_unit } [ p ] VITAL_design_unit ::= context_clause library_unit | context_clause VITAL_library_unit [ p ] VITAL_entity_declarative_part ::= VITAL_Level0_attribute_specification [ p ] VITAL_entity_generic_clause ::= generic ( VITAL_entity_interface_list ) ; [ p ] VITAL_entity_header ::= [ VITAL_entity_generic_clause ] [ VITAL_entity_port_clause ] [ p ] VITAL_entity_interface_declaration ::= interface_constant_declaration | VITAL_timing_generic_declaration | VITAL_control_generic_declaration | VITAL_entity_port_declaration [ p ] VITAL_entity_interface_list ::= VITAL_entity_interface_declaration { ; VITAL_entity_interface_declaration } [ p ] VITAL_entity_port_clause ::= port ( VITAL_entity_interface_list ) ; [ p ] VITAL_entity_port_declaration ::= [ p ] [ signal ] identifier_list : [ mode ] type_mark [ index_constraint ] [ := static_expression ] ; VITAL_functionality_section ::= { VITAL_variable_assignment_statement | procedure_call_statement } [ p 43 ] VITAL_internal_signal_declaration ::= signal identifier_list : type_mark [ index_constraint ] [ := expression ] ; [ p 36 ] 412 Published by IEC under licence from IEEE © 2004 IEEE All rights reserved Copyright © 2001 IEEE All rights reserved LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU VITAL_control_generic_declaration ::= [ p 16 ] [ constant ] identifier_list ::= [ in ] type_mark [ index_constraint ] [ := static_expression ] ; 422 INTEGRATED CIRCUIT) MODELING SPECIFICATION IEC 61691-5:2004(E) IEEE IEEE 1076.4-2000(E) Std 1076.4-2000 VITAL_Level_0_architecture_body ::= architecture identifier of entity_name is VITAL_Level_0_ architecture_declarative_part begin architecture_statement_part end [architecture] [ architecture_simple_name ] ; [ p 17 ] VITAL_Level_0_architecture_declarative_part ::= VITAL_Level0_attribute_specification { block_declarative_item } [ p 17 ] [ p ] VITAL_Level_1_architecture_body ::= architecture identifier of entity_name is VITAL_Level_1_architecture_declarative_part begin VITAL_Level_1_architecture_statement_part end [architecture] [ architecture_simple_name ] ; [ p 35 ] VITAL_Level_1_architecture_declarative_part ::= VITAL_Level1_attribute_specification { VITAL_Level_1_block_declarative_item } [ p 36 ] VITAL_Level_1_architecture_statement_part ::= VITAL_Level_1_concurrent_statement { VITAL_Level_1_concurrent_statement } [ p 36 ] VITAL_Level_1_block_declarative_item ::= constant_declaration | alias_declaration | attribute_declaration | attribute_specification | VITAL_internal_signal_declaration [ p 36 ] VITAL_Level_1_ concurrent_statement ::= VITAL_wire_delay_block_statement | VITAL_negative_constraint_block_statement | VITAL_process_statement | VITAL_primitive_concurrent_procedure_call [ p 36 ] VITAL_Level1_Memory_architecture_body ::= architecture identifier of entity_name is VITAL_Level1_Memory_architecture_declarative_part begin VITAL_Level1_Memory_architecture_statement_part end [architecture] [ architecture_simple_name ] ; [ p 76 ] VITAL_Level1_Memory_architecture_declarative_part ::= VITAL_Level1_Memory_attribute_specification { VITAL_Level1_Memory_block_declarative_item } [ p 77 ] Copyright © IEC 2001 IEEE All from rights reserved Published by under licence IEEE © 2004 IEEE All rights reserved 413 LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU VITAL_Level_0_entity_declaration ::= entity identifier is VITAL_entity_header VITAL_entity_declarative_part end [entity] [ entity_simple_name ] ; IEC 61691-5:2004(E) IEEE IEEE 1076.4-2000(E) Std 1076.4-2000 423 IEEE STANDARD FOR VITAL ASIC (APPLICATION SPECIFIC [ p 77 ] VITAL_Level1_Memory_block_declarative_item ::= constant_declaration | alias_declaration | attribute_declaration | attribute_specification | VITAL_memory_internal_signal_declaration [ p 77 ] VITAL_Level1_Memory_concurrent_statement ::= VITAL_wire_delay_block_statement | VITAL_negative_constraint_block_statement | VITAL_memory_process_statement | VITAL_memory_output_drive_block_statement [ p 77 ] VITAL_Level0_attribute_specification ::= attribute_specification [ p ] VITAL_Level1_attribute_specification ::= attribute_specification VITAL_Level1_Memory_attribute_specification ::= attribute_specification VITAL_library_unit ::= VITAL_Level_0_entity_declaration | VITAL_Level_0_architecture_body | VITAL_Level_1_architecture_body | VITAL_Level_1_memory_architecture_body [ p 76 ] [ p ] VITAL_memory_functionality_section ::= [ p 82 ] { VITAL_variable_assignment_statement | VITAL_memory_procedure_call_statement } VITAL_memory_internal_signal_declaration ::= signal identifier_list : type_mark [ index_constraint ] [ := expression ] ; [ p 77 ] VITAL_memory_process_declarative_item ::= constant_declaration | alias_declaration | attribute_declaration | attribute_specification | VITAL_variable_declaration | VITAL_memory_variable_declaration [ p 79 ] VITAL_memory_process_declarative_part ::= { VITAL_memory_process_declarative_item } [ p 79 ] VITAL_memory_process_statement ::= process_label : process ( sensitivity_list ) VITAL_memory_process_declarative_part begin VITAL_memory_process_statement_part end process [ process_label ] ; [ p 78 ] 414 Published by IEC under licence from IEEE © 2004 IEEE All rights reserved Copyright © 2001 IEEE All rights reserved LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU VITAL_Level1_Memory_architecture_statement_part ::= VITAL_Level1_Memory_concurrent_statement { VITAL_Level1_Memory_concurrent_statement } 424 INTEGRATED CIRCUIT) MODELING SPECIFICATION IEC 61691-5:2004(E) IEEE IEEE 1076.4-2000(E) Std 1076.4-2000 [ p 78 ] VITAL_memory_timing_check_condition ::= generic_simple_name [ p 81 ] VITAL_memory_timing_check_section ::= if VITAL_memory_timing_check_condition then { VITAL_memory_timing_check_statement } end if ; [ p 81 ] VITAL_memory_timing_check_statement ::= procedure_call_statement [ p 81 ] VITAL_memory_variable_declaration ::= variable identifier_list : type_mark [ index_constraint ] [ := expression ] ; [ p 79 ] VITAL_negative_constraint_block_statement ::= block_label : block begin VITAL_negative_constraint_block_statement_part end block [ block_label ] ; [ p 39 ] VITAL_negative_constraint_block_statement_part ::= { VITAL_negative_constraint_concurrent_procedure_call | VITAL_negative_constraint_generate_statement _part} [ p 39 ] VITAL_negative_constraint_concurrent_procedure_call ::= concurrent_procedure_call [ p 39 ] VITAL_negative_constraint_generate_statement _part ::= VITAL_negative_constraint_generate_statement { VITAL_negative_constraint_generate_statement} [ p 39 ] VITAL_negative_constraint_generate_parameter_specification ::= identifier in range_attribute_name [ p 39 ] VITAL_negative_constraint_generate_statement ::= generate_label : for VITAL_negative_constraint_generate_parameter_specification generate { VITAL_negative_constraint_concurrent_procedure_call } end generate {generate_label } [ p 39 ] VITAL_output_drive_block_statement ::= block_label : block begin VITAL_output_drive_block_statement_part end block [ block_label ] ; [ p 85 ] VITAL_output_drive_block_statement_part ::= { VITAL_primitive_concurrent_procedure_call | concurrent_signal_assignment_statement } [ p 85 ] Copyright © IEC 2001 IEEE All from rights reserved Published by under licence IEEE © 2004 IEEE All rights reserved 415 LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU VITAL_memory_process_statement_part ::= [ VITAL_memory_timing_check_section ] [ VITAL_memory_functionality_section ] [ VITAL_memory_path_delay_section ] IEC 61691-5:2004(E) IEEE IEEE 1076.4-2000(E) Std 1076.4-2000 425 IEEE STANDARD FOR VITAL ASIC (APPLICATION SPECIFIC [ p 44 ] VITAL_process_declarative_item ::= constant_declaration | alias_declaration | attribute_declaration | attribute_specification | VITAL_variable_declaration [ p 41 ] VITAL_process_declarative_part ::= { VITAL_process_declarative_item } [ p 41 ] VITAL_process_statement ::= [ process_label : ] process ( sensitivity_list ) VITAL_process_declarative_part begin VITAL_process_statement_part end process [ process_label ] ; [ p 40 ] VITAL_process_statement_part ::= [ VITAL_timing_check_section ] [ VITAL_functionality_section ] [ VITAL_path_delay_section ] [ p 42 ] VITAL_target ::= unrestricted_variable_name | memory_unrestricted_variable_name [ p 43, 82 ] VITAL_timing_check_condition ::= generic_simple_name [ p 42 ] VITAL_timing_check_section ::= if VITAL_timing_check_condition then { VITAL_timing_check_statement } end if ; [ p 42 ] VITAL_timing_check_statement ::= procedure_call_statement [ p 42 ] VITAL_timing_generic_declaration ::= [ p ] [ constant ] identifier_list ::= [ in ] type_mark [ index_constraint ] [ := static_expression ] ; VITAL_variable_assignment_statement ::= VITAL_target := expression ; [ p 43 ] VITAL_variable_declaration ::= variable identifier_list : type_mark [ index_constraint ] [ := expression ] ; [ p 41 ] VITAL_wire_delay_block_statement ::= block_label : block begin VITAL_wire_delay_block_statement_part end block [ block_label ] ; [ p 37 ] 416 Published by IEC under licence from IEEE © 2004 IEEE All rights reserved Copyright © 2001 IEEE All rights reserved LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU VITAL_primitive_concurrent_procedure_call ::= VITAL_primitive_concurrent_procedure_call 426 INTEGRATED CIRCUIT) MODELING SPECIFICATION IEC 61691-5:2004(E) IEEE IEEE 1076.4-2000(E) Std 1076.4-2000 [ p 37 ] VITAL_wire_delay_concurrent_procedure_call ::= concurrent_procedure_call [ p 38 ] VITAL_wire_delay_generate_parameter_specification ::= identifier in range_attribute_name [ p 38 ] VITAL_wire_delay_generate_statement ::= generate_label : for VITAL_wire_delay_generate_parameter_specification generate { VITAL_wire_delay_concurrent_procedure_call } end generate [ generate_label ] ; [ p 38 ] Copyright © IEC 2001 IEEE All from rights reserved Published by under licence IEEE © 2004 IEEE All rights reserved LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU VITAL_wire_delay_block_statement_part ::= { VITAL_wire_delay_concurrent_procedure_call | VITAL_wire_delay_generate_statement } 417 IEC 61691-5:2004(E) IEEE IEEE 1076.4-2000(E) Std 1076.4-2000 427 IEEE STANDARD FOR VITAL ASIC (APPLICATION SPECIFIC Annex B (informative) Glossary This glossary contains brief, informal definitions of a number of hardware-specific terms and phrases that are used in the VITAL ASIC modeling specification The definitions in this annex are not a part of the formal definition of the VITAL ASIC modeling specification B.2 address: the pins in the ASIC memory used to access a portion or a whole memory location B.3 ASIC cell: the building block of an Application Specific Integrated Circuit B.4 ASIC memory: a storage block embedded in an ASIC designed typically using array of latches in a rectangular grid which has specific row and column addresses e.g a 16 x memory means a memory array with 16 rows and there are bits per row B.5 cross port access: It is a multi-port memory access (read or write) in which an address port associates itself to the data output port of another address port B.6 device delay: the intrinsic delay of a cell; it represents the delay associated from each input path to the given output of the cell B.7 hold time: the time period following a clock edge during which an input signal value may not change value B.8 interconnect path delay: delays on the wires which connect various instantiations of ASIC cells in a design B.9 multiport memories: these are memories with multiple address and data output ports A single port memory can only perform either read or write at a given time A dual port memory (2 address ports, one read one write) can perform read operation at one port and write operation at the other port simultaneously B.10 no change time: a stable interval associated with a setup or hold constraint A signal checked against a control signal must remain stable during the setup period established before the start of the control pulse, the entire width of the pulse, and the hold period established after the pulse Each of these stable intervals is a no change time B.11 output Retain time: the time period in which the data output signal of ASIC memories retains the previous value before changing to a new value after the propagation delay Note that in the time period between the output retain time and propagation delay the output will go to an intermediate unknown state Output retain time is also known as data hold time B.12 period: the time delay from the specified edge of a clock pulse to the corresponding edge of the following clock pulse 418 Published by IEC under licence from IEEE © 2004 IEEE All rights reserved Copyright © 2001 IEEE All rights reserved LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU B.1 access time: the delay time valid data appears in the data output bus of a memory when a memory access is occurred 428 INTEGRATED CIRCUIT) MODELING SPECIFICATION IEC 61691-5:2004(E) IEEE IEEE 1076.4-2000(E) Std 1076.4-2000 B.13 propagation delay: the time delay from the arrival of an input signal value to the appearance of a corresponding output signal value B.14 pulse width: the time duration for which the value of signal remains unchanged at a low or high state B.15 recovery time: the minimal time interval by which a change to an unasserted value on an asynchronous (set, reset) input signal must precede the clock edge B.16 removal time: the minimal time interval for which an asserted condition must be present on an asynchronous (set, reset) input signal, following the clock edge B.18 setup time: the time period prior to a clock edge during which an input signal value may not change value B.19 skew time: the maximum allowable delay between two signals A delay which exceeds the skew time causes devices to behave unreliably B.20 subword memories: a set of contiguous bits of a memory word can be accessed in this kind of memory by an associated enable pin e.g A 4-bit wide memory can have bits per soberer - bits to is one soberer controlled by WEB(1) and bits to is another soberer controlled by WEB(0) B.21 synchronous memories: a clock signal is needed to trigger all read and write operations in this type of memory Copyright © IEC 2001 IEEE All from rights reserved Published by under licence IEEE © 2004 IEEE All rights reserved 419 LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU B.17 same port access: It is a multi-port memory access (read or write) in which an address port associates itself to its corresponding data output port ASIC memories are typically designed as addressable latches In such cases the read only and read/write ports are always associated with a corresponding data output ports However the write only ports not have any direct association with data output ports IEC 61691-5:2004(E) IEEE IEEE 1076.4-2000(E) Std 1076.4-2000 429 Annex C (informative) Bibliography [C1] EIA-567-A VHDL Hardware Component Modeling and Interface Standard.3 [C2] IEEE Std 1076-1993, IEEE Standard VHDL Language Reference Manual.4,5 NOTE An updated edition (2002) has been issued 3EIA publications are available from the Electronic Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201-3834, USA publications are available from the Institute of of Electrical and Electronics Engineers, 445 Hoes Lane, P.O Box 1331, Piscataway, NJ 08855-1331, USA 5ANSI publications are available from the Sales Department, American National Standards Institute, 11 West 42nd Street, 13th Floor, New York, NY 10036, USA 4IEEE 420 Published by IEC under licence from IEEE © 2004 IEEE All rights reserved Copyright © 2001 IEEE All rights reserved LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU [C3]IEEE Std 1076/INT-1991, IEEE Standards Interpretations: IEEE Standard VHDL Language Reference Manual.4 IEC 61691-5:2004(E) IEEE 1076.4-2000(E) 430 Annex D (informative) List of Participants The following persons were members of the 1076.4 Technical Action Group (TAG): Victor Berman, Chair Dennis B Brophy, Chair, 1076.4 Technical Action Group Ekambaram Balaji Martin Gregory B Sudheendra Prakash Bare Rama Kowsalya Ajayharsh P Varikat Nitin Chowdhary Phani Kumar Steven D Wadsworth Jose De Castro David Lin, William Yam Ashwini Mulgaonkar Peter J Ashenden Stephen A Bailey David L Barton Victor Berman J Bhasker William Billowitch Dennis B Brophy Brian A Dalio Timothy R Davis Ted Elkind Andrew Guyler Rich Hatcher Jim Heaton Neil G Jacobson Osamu Karatsu Jake Karrfalt Satoshi Kojima Gunther Lehmann Maqsoodul Mannan Paul J Menchini Jean P Mermet Quentin G Schmierer Steven E Schulz Francesco Sforza Joseph P Skudlarek Joseph J Stanco Steven D Wadsworth Ronald Waxman Ron Werner John M Williams John Willis Mark Zwolinski When the IEEE-SA Standards Board approved this standard on 21 September 2000, it had the following membership: Donald N Heirman, Chair James T Carlo, Vice Chair Judith Gorman, Secretary Satish K Aggarwal Mark D Bowman Gary R Engmann Harold E Epstein H Landis Floyd Jay Forster* Howard M Frazier Ruben D Garzon James H Gurney Richard J Holleman Lowell G Johnson Robert J Kennelly Joseph L Koepfinger* Peter H Lips L Bruce McClung Daleep C Mohla *Member Emeritus James W Moore Robert F Munzner Ronald C Petersen Gerald H Peterson John B Posey Gary S Robinson Akio Tojo Donald W Zipse Also included is the following nonvoting IEEE-SA Standards Board liaison: Alan Cookson, NIST Representative Donald R Volzka, TAB Representative Andrew D Ickowicz IEEE Standards Project Editor Published by IEC under licence from IEEE © 2004 IEEE All rights reserved LICENSED TO MECON Limited - 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