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Flip-Flops and Counters • Digital systems operate either asynchronously / synchronously General digital system diagram: consists of combinational logic gates and memory elements C.B Pham 3-1 Flip-Flop The most important memory element is the flip-flop, which is made up of an assembly of logic gates • In asynchronous system: outputs of logic circuit can change state any time one or more of the inputs change • In synchronous systems, the exact times at which any output can change states are determined by a signal commonly called the clock 3-2 C.B Pham NAND Gate Latch • Constructed using two NAND gates • Active-LOW C.B Pham 3-3 NAND Gate Latch Case 1: SET = CLEAR = The outputs will remain in whatever state they were prior to this input condition C.B Pham 3-4 NAND Gate Latch Case 2: SET = 0, CLEAR = Q = 1, setting the latch C.B Pham 3-5 NAND Gate Latch Case 3: SET = 1, CLEAR = Q = 0, clearing / resetting the latch C.B Pham 3-6 NAND Gate Latch Case 4: SET = 0, CLEAR = Q Q 1 This should not be used C.B Pham 3-7 “Switch debouncing” circuit C.B Pham 3-8 NOR Gate Latch • Constructed using two NOR gates • Active-HIGH Note: Do not know the starting state of a flip-flop’s output 3-9 C.B onPham power up Clock Signals and Clocked FFs • System outputs can change states only when the clock makes a transition • Most digital systems are principally synchronous C.B Pham 3-10 Clocked D Flip-Flop C.B Pham 3-17 Clocked D Flip-Flop Parallel transfer of binary data using D flip-flops C.B Pham 3-18 Asynchronous inputs • Most clocked FFs also have one or more asynchronous inputs which operate independently of the synchronous inputs and clock input • The most commonly used designations: Preset (Pr / Pre / Set): Q = Clear (Cl / Clr / Reset): Q = C.B Pham 3-19 Asynchronous inputs C.B Pham 3-20 Flip-Flops in counters • Different types of counter are formed from a combination of FFs and logic gates Asynchronous (ripple) counters C.B Pham Synchronous (parallel) counters 3-21 Asynchronous up counters C.B Pham 3-22 Asynchronous down counters C.B Pham 3-23 Counters with MOD numbers 2N C.B Pham 3-24 Synchronous (parallel) counters C.B Pham 3-25 Design Procedure • Step1: Determine the desire number of bits (FFs) and the desired counting sequence • Step2: Draw the state transition diagram showing all possible states, including those that are not part of the desired counting sequence • Step 3: Use the state-transition diagram to set up a table that lists all PRESENT states and their NEXT states • Step 4: Add a column to the above table for each J and K input to produce a circuit excitation table • Step 5: Design the logic circuits to generate the levels required at each J and K input • Step 6: Implement the final expressions C.B Pham 3-26 Synchronous counter design Problem: design a MOD-5 synchronous counter C.B Pham Step1 Step Step 3-27 Synchronous counter design Step 4: produce a circuit excitation table for J-K FFs C.B Pham 3-28 Synchronous counter design Step 5: Design the logic circuits to generate the levels required at each J and K input For FF A: C.B Pham JA C , KA 1 3-29 Synchronous counter design For FF B: J B AC KB A C J C AB KC 1 For FF C: C.B Pham 3-30 Synchronous counter design C.B Pham Step 3-31
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