Modelling and control of active neutral point clamped multi level inverter

VIETNAM NATIONAL UNIVERSITY HO CHI MINH CITY HO CHI MINH UNIVERSITY OF TECHNOLOGY TRAN DINH LONG MODELLING AND CONTROL OF ACTIVE NEUTRAL POINT CLAMPED MULTI-LEVEL INVERTER Major: Electrical Engineering Major ID: 8520201 MASTER THESIS HO CHI MINH CITY, February 2023 THIS RESEARCH IS COMPLETED AT: HO CHI MINH UNIVERSITY OF TECHNOLOGY – VNU HCM Instructor: Assoc Prof Nguyen Van Nho Examiner 1: Dr Truong Phuoc Hoa Examiner 2: Dr Tran Thanh Ngoc Master’s Thesis is defended at HCMC University of Technology, VNUHCM on February 04, 2023 The Board of The Master’s Thesis Defense Council includes: Chairman: Assoc Prof Nguyen Dinh Tuyen Secretary: Dr Nguyen Chan Viet Reviewer 1: Dr Truong Phuoc Hoa Reviewer 2: Dr Tran Thanh Ngoc Council Member: Dr Huynh Van Van Verification of the chairman of the Master’s Thesis Defense Council and the Dean of the Faculty of Electrical and Electronics Engineering after the defense is correct (if any) CHAIRMAN OF THE COUNCIL DEAN OF FACULTY OF (Full name and signature) ELECTRICAL AND ELECTRONICS ENGINEERING (Full name and signature) VIETNAM NATIONAL UNIVERSITY HCMC VNUHCM UNIVERSITY OF TECHNOLOGY SOCIALIST REPUBLIC OF VIETNAM Independent – Liberty - Happiness MASTER’S THESIS ASSIGNMENTS Full name: TRAN DINH LONG ID:2070347 Date of birth: October 24th,1997 Place of birth: HCMC Major: Electrical Engineering Major ID : 8520201 I TITTLE: Modelling and Control of Active Neutral Point Clamped Multi-level Inverter Mơ hình hố điều khiển nghịch lưu tích cực II ASSIGNMENTS AND CONTENTS: Modelling the 5L ANPC with CBPWM method Modelling the 5L ANPC with SVPWM method Proposed SVPWM method to reduce Common-mode voltage III ASSIGNMENT DELIVERING DATE : September 5th,2022 IV ASSIGNMENT COMPLETING DATE: December 18th,2022 V INSTRUCTOR : Assoc Prof Nguyen Van Nho Ho Chi Minh City, December 16th, 2022 INSTRUCTOR (Full name and signature) HEAD OF DEPARTMENT (Full name and signature) DEAN OF FACULTY OF ELECTRICAL AND ELECTRONICS ENGINEERING (Full name and signature) i ACKNOWLEDGEMENTS Give the best sincerely to Associate Professor Nguyen Van Nho who has guided me through the thesis process His expertise in this field of study is exceptional, and it was a pleasure and honour for me to have him as an advisor I would like to thank Mr Pham Dang Khoa and the members of PERLAB for assisting and encouraging me Finally, I sincerely thank my family for all the support they have given to me over the years Ho Chi Minh City, December 19th 2022 Student Tran Dinh Long ii ABSTRACT Multi-level inverters (MLIs) have been increasingly used practically There are three main types: Neutral-Point-Clamped (NPC), Flying Capacitor (FC), and Cascade where NPCs are mostly used due to the simple structure and low cost Three-level (3L) and five-level (5L) NPC have become the solution for higher power applications, which create better THD and CMV performance The 5L NPC inverter has several problems such as different voltage ratings of diodes, and difficulty in balancing DC link voltage Active NPC (ANPC) has been introduced combining the robustness of the NPC and the d flexibility of the FC There are many PWM methods to control the ANPC as CBPWM and SVPWM: CBPWM is simple and SVPWM is effective to reduce or eliminate the CMV The proposed content of this thesis: SVPWM, CMV reduction and FC balancing TÓM TẮT LUẬN VĂN Bộ nghịch lưu ngày sử dụng phổ biến thực tế Có dạng nghịch lưu NPC, FC cascade, NPC sử dụng nhiều cấu trúc đơn giản giá thành tiết kiệm Với thiếu bị địi hỏi cơng suất điện áp cao, NPC bậc bậc phát triển nhằm tăng THD giảm CMV Bộ nghịch lưu NPC bậc xảy khuyết điểm khó cân điện áp DC link, điện áp diode khác Vì thế, nghịch lưu tích cực đời, kết hợp NPC FC ANPC thường điều khiển phương pháp CBPWM phương pháp đơn giản, SVPWM lại mang hiệu cao việc giảm triệt tiêu CMV Mục tiêu đề luận văn nhằm đề xuất phương pháp SVPWM giảm dòng CMV cân điện áp FC iii DECLARATION I certify that the work has not been submitted previously The content of the thesis is the result of work which has been carried out since the official commencement date of the thesis Tran Dinh Long iv TABLE OF CONTENTS ACKNOWLEDGEMENTS i ABSTRACT… ii TÓM TẮT LUẬN VĂN ii DECLARATION iii LIST OF FIGURES vi LIST OF TABLES viii Chapter Introduction 1.1 Background 1.2 Problem Definition 1.3 Thesis agenda Chapter Overview of the 5L-ANPC 2.1 The 5L-ANPC Topology 2.2 Analysis of the 5L-ANPC 2.3 Principle of Capacitor Voltage Balancing 17 Chapter Carrier-based PWM for the 5L-ANPC inverter 18 3.1 Literature review for the CB-PWM 18 3.2 Flow chart of the CB-PWM algorithm 20 Chapter Space Vector PWM for the 5L-ANPC 22 4.1 Proposed SVPWM for 5L-ANPC 22 4.2 Voltage balancing of the FC 33 Chapter Proposed SVPWM to reduce Common mode voltage 34 5.1 Common mode voltage (CMV) 34 5.2 Proposed SVPWM method to reduce CMV 34 Chapter Simulation Results 38 6.1 Carrier-based PWM 38 6.2 Proposed SVPWM 42 Chapter 7.1 Losses Calculation 46 Overview of losses calculation method 46 7.1.1 Conduction losses 46 7.1.2 Switching losses 47 7.2 PLECS calculation 47 Chapter Conclusion and Future Works 50 List of Publications 51 v Reference……… 62 Background…… 65 vi LIST OF FIGURES Figure 1-1:NPC inverter topology and FC inverter topology Figure 2-1: Structure of 5L-ANPC inverter Figure 2-2: Switching state S1 Figure 2-3: Switching state S2 Figure 2-4: Switching state S3 Figure 2-5 Switching state S4 11 Figure 2-6: Switching state S5 12 Figure 2-7: Switching state S6 13 Figure 2-8 Switching state S7 15 Figure 2-9 Switching state S8 16 Figure 2-10 Algorithm for balancing Flying capacitor 17 Figure 3-1: Carrier wave for CB-PWM case 18 Figure 3-2 Flowchart of the 5L ANPC using CB PWM 20 Figure 4-1 Space vectors of 5L-ANPC inverter 23 Figure 4-2 Diving hexagon into sectors 27 Figure 4-3 Space vector in sector1 28 Figure 4-4 Determine m1, m2 of Vref 29 Figure 4-5 Switching sequence arranged in a symmetrical pattern 33 Figure 4-6 Effect of redundant switching states on the FC voltages 33 Figure 5-1 Space vector diagram for the 5L ANPC reducing CMV 35 Figure 5-2 Switching voltage vector in Sector I to reduce CMV 36 Figure 5-3 Switching sequence in region 37 Figure 6-1 Model of 5L ANPC in MATLAB Simulink 38 Figure 6-2 Vpp, Vpn, and I phase for CBPWM with m = 0.2 39 Figure 6-3 Vpp, Vpn, and I phase for CBPWM with m = 0.4 39 Figure 6-4 Vpp, Vpn, and I phase for CBPWM with m = 0.6 40 vii Figure 6-5 Vpp, Vpn, and I phase for CBPWM with m = 0.8 40 Figure 6-6 Common-mode voltage when m =0.2 and m = 0.8by using SinPWM 41 Figure 6-7 THD I of SinPWM 41 Figure 6-8 THD Vpn and Vpp of Sin PWM 42 Figure 6-9 Vpp, Vpn, and I phase for SVPWM with m = 0.2 42 Figure 6-10 Vpp, Vpn, and I phase for SVPWM with m = 0.5 43 Figure 6-11 Vpp, Vpn, and I phase for SVPWM with m = 0.9 43 Figure 6-12 Common-mode voltage when m = 0.2 and m = 0.9, SVPWM 44 Figure 6-13 THD I of SVPWM 44 Figure 6-14 THD Vpn and Vpp of Sin PWM 45 Figure 7-1 Summary the losses in IGBT module 46 Figure 7-2 Specification of RGW60TS65CHR 48 Figure 7-3 The total losses of the ANPC when m = 0.2 and m = 0.9 48 Figure 7-4 CMV voltage at m = 0.2 in CBPWM and SVPWM 49 51 List of Publications International Conference L.Tran, and N Nguyen, “SVPWM Strategies to Reduce Common-Mode Voltage for FiveLevel ANPC inverter,” AETA 2022 The 7th International Conference on Advanced Engineering - Theory and Applications, Ho Chi Minh City, Vietnam, 2022 52 SVPWM Strategies to Reduce Common-Mode Voltage for Five-Level ANPC inverter Long Dinh Tran1,2 and Nho Van Nguyen1,2 Faculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology (HCMUT), 268 Ly Thuong Kiet Street, District 10, Ho Chi Minh City, Vietnam Vietnam National University Ho Chi Minh City, Linh Trung Ward, Thu Duc City, Ho Chi nvnho@hcmut.edu.vn Abstract In this paper, a novel space vector pulse width modulation (SVPWM) is proposed to reduce common-mode voltage (CMV) of the three-phase five-level active neutral-point clamped (5L-ANPC), by utilizing only 55 selected voltage vectors among 125 voltage vectors to produce low values of the CMVs with the maximum modulation index (MI) A novel method to detect reference voltage vector and calculate its dwelling time is proposed Besides, the flying capacitor (FC) voltages are controlled by the redundant switches of the 5L-ANPC inverters, making it balanced This balancing method is derived by using the instantaneous measurements of output current and FC’s voltages The simulation results showed that the peak of the CMV is decreased significantly to one twelfth of the DC link voltage, decrease in total harmonic distortion (THD) of the output voltages with out increasing the switching losses Keywords: 3P-5L-ANPC inverter, CMV, SVPWM Introduction Multi-level voltage source converters (MLVSCs) have been widely used in motor drives and distributed generation systems due to their advantages with low-voltage devices, low harmonics, reduced switching losses [1]-[3] For instance, the three-level three-phase converters have been widely used for electric vehicles (EV) [4]-[5] Furthermore, many MLVSC topologies have been proposed in recent years to adapt to high voltage application and reduce the output harmonics [6][8] One key drawback of MLVSCs is the common-mode voltages (CMV), leading to high leakage current, increase loss, high harmonics, damaging the converters and shortening electric machine life Hence, conventional control strategies as sinusoidal pulse width modulation (SPWM) and space vector pulse width modulation (SVPWM) have been modified to reduce the CMVs In [9], two SVPWM modulation techniques were used to reduce CMV for T type three phase three level VSC in photovoltaic system using appropriate voltage vectors To extend the output voltage level, the 3P-5L-ANPC converter has been proposed and is considered a compromising multilevel topology [10] For the 3P-5L-ANPC inverter, the PWM scheme can reduce up to Vdc/12 by utilizing only 55 voltage vectors creating low CMV values [11] The flying capacitor voltages are controlled by values of current and the flying capacitor voltage in the redundant states This topology is an appropriate option for high power motor drive applications due to its advantages as high efficiency, simple structure and control [12] However, the peak of CMV is high, and the DC-link capacitor has not been eliminated Therefore, this paper provides the SVPWM method to reduce CMV to Vdc/12 This paper is organized in the following way In section II, the principles of the ANPC inverter, operation principle and CMV are presented Section III, IV, and V describe the effect of the switching states on flying capacitors, the modulation technique to reduce CMV and the simulation results respectively Lastly, conclusions are presented in Section VI The effectiveness of the proposed SVPWM scheme is verified by the simulation results 53 Five-Level ANPC Inverter 2.1 Configuration Fig.1 illustrates the three-phase 5L-ANPC inverters, each phase leg of 5L-ANPC inverters comprise eight switches, one flying capacitor (FC) and two DC-link capacitors The DC-link capacitors are rated at half of the dc link voltage This topology requires a flying capacitor voltage should normally one quarter of the dc-link voltage to generate uniform step levels at the output phase voltage In each leg of 5L-ANPC inverters, there are four complementary switch pairs such as (S1 and S2), (S3 and S4), (S5 and S6), (S7 and S8) S5a + C1 Vdc/2 - S5b S5c S3a S6a S6b S1a ICj + ia Ci - + ib - S2a S1c ICj S1b Ci S7a + C2 Vdc/2 - S6c ICj + O S3c S3b Ci - S2b S7b S7c S4c S4b S4a S8a ic S2c S8b S8c R1 R3 R2 N Fig1: Structure of 3P-5L-ANPC inverter Define: van, vbn, vcn: phase-to-neutral voltages of phases A, B, and C, respectively Vao, vbo,vco: pole voltages of phases A, B, and C, respectively The output levels of each phase, vxo (x=a, b, c) can be expressed as: ( = 2.2 − 2)/2 (1) Operating Principle The switching states of the 5L-ANPC inverter are listed on table I, where “0” and “1” represent the off and on states of the switches If the voltages across the dc-link capacitors are balanced and voltage across FC is Vdc/4, there are possible five levels of output voltage Vxo (x = a,b,c) generated based on the different switching states combinations S1, S3, S5, S7 in Table I There are several phase voltage redundancies For instances, V6 and V7 are the redundant switching states to generate Vdc/2 Similarly (V2 V3) and (V4 V5) are redundant states to generate -Vdc/2 and respectively However, despite generating the same output voltage level, redundant switching states (V2 V3) and (V6 V7) affecting on FC voltage are opposite due to the FC current direction Table I: Switching states of 5L-ANPC Inverter Switching State VXO Switching Function (Sx) S1 S3 S5 S7 V1 -Vdc 0 0 V2 -Vdc/2 1 0 V3 -Vdc/2 1 0 V4 1 0 V5 0 1 V6 Vdc/2 1 V7 Vdc/2 1 Ifc Vfc >0 0 0 0 0 0 0 0