Bài tập lập trình VLSI Lab programs

Bài tập lập trình VLSI Lab programs

EX.NO:1(a) Design and Simulation of Half Adder using VHDL AIM: To design and verify the Half Adder using VHDL. TOOLS REQUIRED: 1. Computer with ModelSim Software THEORY: Let's start by adding two binary bits. Since each bit has only two possible values, 0 or 1, there are only four possible combinations of inputs. These four possibilities, and the resulting sums, are: 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 10 That fourth line indicates that we have to account for two output bits when we add two input bits: the sum and a possible carry. Let's set this up as a truth table with two inputs VHDL CODING: library ieee; use ieee.std_logic_1164.all; entity halfadder is port (a,b:in bit; sum,carry: out bit); end halfadder; architecture arch_halfadder of halfadder is begin sum<= a xor b; carry<= a and b; end arch_halfadder; 080290044 & VLSI Lab 1 PROCEDURE 1. Open new file in VHDL source editor 2. Type the VHDL coding for Half Adder in the new file. 3. Save the file with the extension of .vhd 4. Compile and Simulate the Program. 5. Add the selected signal to the wave form window. 6. Force the input signals values and verify the output signal values. RESULT: Thus the Half adder is designed and verified using VHDL. EX.NO:1(b) Design and Simulation of Full Adder using VHDL AIM: To design and verify the Full Adder using VHDL. TOOLS REQUIRED: 1. Computer with ModelSim Software THEORY: To construct a full adder circuit, we'll need three inputs and two outputs. Since we'll have both an input carry and an output carry, we'll designate them as C IN and C OUT . At the same time, we'll use S to designate the final Sum output. The resulting truth table is shown to the right. VHDL CODING: library ieee; use ieee.std_logic_1164.all; entity fulladder is port (x, y, Cin: in bit; Cout,S :out bit); 080290044 & VLSI Lab 2 end fulladder; architecture arch_fulladder of fulladder is begin S<= (x xor y) xor Cin; Cout<= (x and y) or (y and Cin) or (Cin and x); end arch_fulladder; PROCEDURE 1. Open new file in VHDL source editor 2. Type the VHDL coding for Full Adder in the new file. 3. Save the file with the extension of .vhd 4. Compile and Simulate the Program. 5. Add the selected signal to the wave form window. 6. Force the input signals values and verify the output signal values RESULT: Thus the Full adder is designed and verified using VHDL. EX.NO:2(a) Design and Simulation of 4:2 Encoder using VHDL AIM: To design and verify the 4:2 Encoder using VHDL. TOOLS REQUIRED: 1. Computer with ModelSim Software Theory: The encoder is a combinational circuit that performs the reverse operation of the decoder. The encoder has a maximum of 2 n inputs and n outputs. An encoder performs the opposite function of a decoder. An encoder takes a input on one of its 2n input lines and converts it to a coded output with n lines. VHDL CODING: 080290044 & VLSI Lab 3 library ieee; use ieee.std_logic_1164.all; entity encoder is port (a,b,c,d:in bit; y:out bit_vector(1 downto 0)); end encoder; architecture arch_encoder of encoder is begin process (a,b,c,d) begin if (a='1')then y<="00"; elsif (b='1')then y<="01"; elsif (c='1')then y<="10"; elsif (d='1')then y<="11"; end if; end process; end arch_encoder; PROCEDURE 1. Open new file in VHDL source editor 2. Type the VHDL coding for 4:2 Encoder in the new file. 3. Save the file with the extension of .vhd 4. Compile and Simulate the Program. 5. Add the selected signal to the wave form window. 6. Force the input signals values and verify the output signal values RESULT: Thus the 4:2 Encoder is designed and verified using VHDL. 080290044 & VLSI Lab 4 EX.NO:2(b) Design and Simulation of 2:4 Decoder using VHDL AIM: To design and verify the 2:4 Decoder using VHDL. TOOLS REQUIRED: 1. Computer with ModelSim Software Theory: The basic function of a decoder is to detect the presence of a particular combination of bits at the inputs and indicate the presence of that particular set of bits by outputting a specified output level. Typically a decoder with n input lines requires 2n output lines to decode every possible combination of bits. BCD to decimal conversion, looked at in part3 of this lab, is accomplished using a decoder which has 4 input lines and 10 output lines (the 10 output lines correspond to the decimal numbers 0-9). This device is used to convert between binary numbers and decimal numbers VHDL CODING: library ieee; use ieee.std_logic_1164.all; entity decoder is port (a,b:in bit; y:out bit_vector(3 downto 0)); end decoder; architecture arch_decoder of decoder is begin process (a,b) begin if (a='0' and b='0' )then y<="0001"; elsif (a='0' and b='1' )then y<="0010"; elsif (a='1' and b='0' )then y<="0100"; 080290044 & VLSI Lab 5 elsif (a='1' and b='1' )then y<="1000"; end if; end process; end arch_decoder; PROCEDURE 1. Open new file in VHDL source editor 2. Type the VHDL coding for 2:4 Decoders in the new file. 3. Save the file with the extension of .vhd 4. Compile and Simulate the Program. 5. Add the selected signal to the wave form window. 6. Force the input signals values and verify the output signal values RESULT: Thus the 2:4 Decoder is designed and verified using VHDL. EX.NO:3(a) Design and Simulation of 8:1 Multiplexer using VHDL AIM: To design and verify the 8:1 Multiplexer using VHDL. TOOLS REQUIRED: 1. Computer with ModelSim Software THEORY: A multiplexer or MUX is a device that allows digital information from several different sources on different input lines to be routed onto a single line. A basic MUX has several input lines, several data select lines or control signals and one output signal. The input that gets selected to pass to the output is determined by the control signals. VHDL CODING: 080290044 & VLSI Lab 6 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mux8to1 is port(y:out std_logic; s:in std_logic_vector(2 downto 0); i:in std_logic_vector(0 to 7)); end mux8to1; architecture arch_mux8to1 of mux8to1 is begin process(s,i) begin case s is when "000" => y <=i(0); when "001" => y <=i(1); when "010" => y <=i(2); when "011" => y <=i(3); when "100" => y <=i(4); when "101" => y <=i(5); when "110" => y <=i(6); when "111" => y <=i(7); when others =>null; end case; end process; end arch_mux8to1; PROCEDURE 1. Open new file in VHDL source editor 2. Type the VHDL coding for 8:1 Multiplexer in the new file. 3. Save the file with the extension of .vhd 4. Compile and Simulate the Program. 5. Add the selected signal to the wave form window. 6. Force the input signals values and verify the output signal values 080290044 & VLSI Lab 7 RESULT: Thus the 8:1 Multiplexer is designed and verified using VHDL. EX.NO:3(b) Design and Simulation of 1:8 Demultiplexer using VHDL AIM: To design and verify the 1:8 Demultiplexer using VHDL. TOOLS REQUIRED: 1. Computer with ModelSim Software THEORY: A demultiplexer is the opposite of a multiplexer. In electronic devices, demultiplexer is a logical circuit which takes a single input and sends out this input to one of several outputs available. During this process the output that has been selected is assigned the value 1, while the other outputs are assigned the value 0. The definition is slightly different when we are talking about demultiplexers in the context of networking. In the networking context, a demultiplexer is a device that receives multiple signals that have been transmitted on one line and then decodes these single line signals into separate multiple signals. A demultiplexer is usually always used in tandem with a multiplexer. Demultiplexers can be analog demultiplexers or digital demultiplexers. Digital demultiplexers generally function as decoders. VHDL CODING: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; 080290044 & VLSI Lab 8 entity demux1to8 is port(y:out std_logic_vector(0 to 7); s:in std_logic_vector(2 downto 0); i:in std_logic); end demux1to8; architecture arch_demux1to8 of demux1to8 is begin process(s,i) begin case s is when "000" => y(0)<=i; when "001" => y(1)<=i; when "010" => y(2)<=i; when "011" => y(3)<=i; when "100" => y(4)<=i; when "101" => y(5)<=i; when "110" => y(6)<=i; when "111" => y(7)<=i; when others =>null; end case; end process; end arch_demux1to8; PROCEDURE 1. Open new file in VHDL source editor 2. Type the VHDL coding for 1:8 Demultiplexers in the new file. 3. Save the file with the extension of .vhd 4. Compile and Simulate the Program. 5. Add the selected signal to the wave form window. 6. Force the input signals values and verify the output signal values RESULT: Thus the 1:8 Demultiplixer is designed and verified using VHDL. 080290044 & VLSI Lab 9 EX.NO:4 Design and Simulation of 4x4 Multiplier using VHDL AIM: To design and verify the 4X4 Array Multiplier using VHDL. TOOLS REQUIRED: 1.Computer with ModelSim Software THEORY The simple serial by parallel booth multiplier is particularly well suited for bit serial processors implemented in FPGAs without carry chains because all of its routing is to nearest neighbors with the exception of the input. The serial input must be sign extended to a length equal to the sum of the lengths of the serial input and parallel input to avoid overflow, which means this multiplier takes more clocks to complete than the scaling accumulator version. VHDL CODING: // 4X4 Array Multiplier library ieee; use ieee.std_logic_1164.all; entity a1 is port(a,b:in std_logic;c:out std_logic); end a1; architecture a of a1 is begin c <= a and b; end a; library ieee; use ieee.std_logic_1164.all; 080290044 & VLSI Lab 10 [...]... file with the extension of vhd 080290044 & VLSI Lab 35 4 5 6 7 8 Assign the I/O Signal to the FPGA package pins Synthesis the VHDL Code Place and Route the Design by click on Implement Design Generate the bit file Configure the bit file on Spartan IIIE FPGA and verify the result RESULT: Thus the real time clock is designed and verified using VHDL 080290044 & VLSI Lab 36 ... file with the extension of vhd Compile and Simulate the Program Add the selected signal to the wave form window Force the input signals values and verify the output signal values RESULT: 080290044 & VLSI Lab 12 Thus the 4X4 Array Multiplier Half adder is designed and verified using VHDL EX.NO:5(a) Design and Simulation of JK Flip Flop using VHDL AIM: To design and verify the JK Flipflop using VHDL TOOLS... flip-flops VHDL CODING: // JK Flipflop library ieee; use ieee.std_logic_1164.all; entity jkff is port (j,k,clk:in std_logic; q,qb:inout std_logic); end jkff; architecture arch_jkff of jkff is 080290044 & VLSI Lab 13 begin process (j,k,clk) begin if (rising_edge(clk))then if (j='0' and k='0')then q . halfadder is begin sum<= a xor b; carry<= a and b; end arch_halfadder; 080290044 & VLSI Lab 1 PROCEDURE 1. Open new file in VHDL source editor 2. Type the VHDL coding for Half Adder. ieee.std_logic_1164.all; entity fulladder is port (x, y, Cin: in bit; Cout,S :out bit); 080290044 & VLSI Lab 2 end fulladder; architecture arch_fulladder of fulladder is begin S<= (x xor y) xor. 2n input lines and converts it to a coded output with n lines. VHDL CODING: 080290044 & VLSI Lab 3 library ieee; use ieee.std_logic_1164.all; entity encoder is port (a,b,c,d:in bit; y:out